CA2159459A1 - Method and System for Managing Memory in a High Speed Network - Google Patents

Method and System for Managing Memory in a High Speed Network

Info

Publication number
CA2159459A1
CA2159459A1 CA2159459A CA2159459A CA2159459A1 CA 2159459 A1 CA2159459 A1 CA 2159459A1 CA 2159459 A CA2159459 A CA 2159459A CA 2159459 A CA2159459 A CA 2159459A CA 2159459 A1 CA2159459 A1 CA 2159459A1
Authority
CA
Canada
Prior art keywords
virtual
memory
atm
managing memory
high speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2159459A
Other languages
French (fr)
Other versions
CA2159459C (en
Inventor
Cesar Augusto Johnston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telcordia Licensing Co LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2159459A1 publication Critical patent/CA2159459A1/en
Application granted granted Critical
Publication of CA2159459C publication Critical patent/CA2159459C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/108—ATM switching elements using shared central buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9057—Arrangements for supporting packet reassembly or resequencing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/563—Signalling, e.g. protocols, reference model
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Abstract

A method and system are provided for managing memory to reassemble data packets received from different virtual channels in an ATM network. The method and system recognizes that both reliable and best effort traffic must be supported by a network interface. The system makes use of a virtual First-In-First-Out (FIFO) concept that partitions random access memory (RAM) space into multiple FIFO queues. The virtual FIFOs can have different sizes, and can be allocated to connections depending on quality of service requirements. A
dedicated embedded controller (721) to provide flexibility is used in the system, as well as Content Addressable Memory (CAM) devices (723, 724) and external logic. The method and system can also be applied at ATM transmitters in the implementation of congestion control algorithms.
CA002159459A 1993-12-01 1994-11-29 Method and system for managing memory in a high speed network Expired - Fee Related CA2159459C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/160,525 US5600820A (en) 1993-12-01 1993-12-01 Method for partitioning memory in a high speed network based on the type of service
US160,525 1993-12-01
PCT/US1994/013644 WO1995015526A1 (en) 1993-12-01 1994-11-29 Method and system for managing memory in a high speed network

Publications (2)

Publication Number Publication Date
CA2159459A1 true CA2159459A1 (en) 1995-06-08
CA2159459C CA2159459C (en) 2000-04-18

Family

ID=22577245

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002159459A Expired - Fee Related CA2159459C (en) 1993-12-01 1994-11-29 Method and system for managing memory in a high speed network

Country Status (3)

Country Link
US (1) US5600820A (en)
CA (1) CA2159459C (en)
WO (1) WO1995015526A1 (en)

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US5956342A (en) 1995-07-19 1999-09-21 Fujitsu Network Communications, Inc. Priority arbitration for point-to-point and multipoint transmission
GB2304210B (en) * 1995-08-11 2000-02-16 Fujitsu Ltd Data receiving devices
US5832262A (en) * 1995-09-14 1998-11-03 Lockheed Martin Corporation Realtime hardware scheduler utilizing processor message passing and queue management cells
US5838994A (en) * 1996-01-11 1998-11-17 Cisco Technology, Inc. Method and apparatus for the dynamic allocation of buffers in a digital communications network
US6034945A (en) * 1996-05-15 2000-03-07 Cisco Technology, Inc. Method and apparatus for per traffic flow buffer management
US6430191B1 (en) 1997-06-30 2002-08-06 Cisco Technology, Inc. Multi-stage queuing discipline
US6487202B1 (en) 1997-06-30 2002-11-26 Cisco Technology, Inc. Method and apparatus for maximizing memory throughput
US7145868B2 (en) * 1997-11-28 2006-12-05 Alcatel Canada Inc. Congestion management in a multi-port shared memory switch
US6526060B1 (en) 1997-12-05 2003-02-25 Cisco Technology, Inc. Dynamic rate-based, weighted fair scheduler with explicit rate feedback option
US6147890A (en) * 1997-12-30 2000-11-14 Kawasaki Steel Corporation FPGA with embedded content-addressable memory
US6279035B1 (en) * 1998-04-10 2001-08-21 Nortel Networks Limited Optimizing flow detection and reducing control plane processing in a multi-protocol over ATM (MPOA) system
US6085254A (en) * 1998-04-10 2000-07-04 Telefonaktiebolaget Lm Ericsson (Publ) Dynamic size alteration of memory files
US6446122B1 (en) * 1998-06-24 2002-09-03 Cisco Technology, Inc. Method and apparatus for communicating quality of service information among computer communication devices
DE19904084B4 (en) * 1999-02-02 2008-12-11 Force Computers Gmbh computer
US6775292B1 (en) 2000-01-24 2004-08-10 Cisco Technology, Inc. Method for servicing of multiple queues carrying voice over virtual circuits based on history
US7142558B1 (en) 2000-04-17 2006-11-28 Cisco Technology, Inc. Dynamic queuing control for variable throughput communication channels
US6829678B1 (en) * 2000-07-18 2004-12-07 International Business Machines Corporation System for determining the order and frequency in which space is allocated on individual storage devices
TW516118B (en) * 2001-09-11 2003-01-01 Leadtek Research Inc Decoding conversion device and method capable of supporting multiple memory chips and their application system
US6996663B1 (en) * 2001-09-12 2006-02-07 Cisco Technology, Inc. Method and apparatus for performing address translation using a CAM
US20030056073A1 (en) * 2001-09-18 2003-03-20 Terachip, Inc. Queue management method and system for a shared memory switch
US6687786B1 (en) * 2001-09-28 2004-02-03 Cisco Technology, Inc. Automated free entry management for content-addressable memory using virtual page pre-fetch
US20050091467A1 (en) * 2003-10-22 2005-04-28 Robotham Robert E. Method and apparatus for accessing data segments having arbitrary alignment with the memory structure in which they are stored
KR100548214B1 (en) * 2003-12-10 2006-02-02 삼성전자주식회사 Packet forwarding system capable of transferring packets fast through plurality of interfaces by reading out information beforehand to transfer packets and a method thereof
US7523232B2 (en) * 2004-07-26 2009-04-21 Integrated Device Technology, Inc. Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system
US8230174B2 (en) * 2004-07-26 2012-07-24 Integrated Device Technology, Inc. Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system
US7805552B2 (en) * 2004-07-26 2010-09-28 Integrated Device Technology, Inc. Partial packet write and write data filtering in a multi-queue first-in first-out memory system
US7870310B2 (en) * 2004-07-26 2011-01-11 Integrated Device Technology, Inc. Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system
US7333279B2 (en) * 2005-03-22 2008-02-19 Seagate Technology Llc System and method for drive-side guarantee of quality of service and for extending the lifetime of storage devices
US8392565B2 (en) * 2006-07-20 2013-03-05 Oracle America, Inc. Network memory pools for packet destinations and virtual machines
JP5016880B2 (en) * 2006-09-21 2012-09-05 富士通株式会社 Memory management method and apparatus according to priority class
US8239866B2 (en) * 2009-04-24 2012-08-07 Microsoft Corporation Reduction of memory latencies using fine grained parallelism and FIFO data structures

Family Cites Families (11)

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Publication number Priority date Publication date Assignee Title
US5130984A (en) * 1990-12-18 1992-07-14 Bell Communications Research, Inc. Large fault tolerant packet switch particularly suited for asynchronous transfer mode (ATM) communication
US5367643A (en) * 1991-02-06 1994-11-22 International Business Machines Corporation Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets
US5274768A (en) * 1991-05-28 1993-12-28 The Trustees Of The University Of Pennsylvania High-performance host interface for ATM networks
DE69130392T2 (en) * 1991-07-10 1999-06-02 Ibm High speed buffer management
US5379297A (en) * 1992-04-09 1995-01-03 Network Equipment Technologies, Inc. Concurrent multi-channel segmentation and reassembly processors for asynchronous transfer mode
US5241536A (en) * 1991-10-03 1993-08-31 Northern Telecom Limited Broadband input buffered atm switch
US5309432A (en) * 1992-05-06 1994-05-03 At&T Bell Laboratories High-speed packet switch
US5383146A (en) * 1992-06-08 1995-01-17 Music Semiconductors, Inc. Memory with CAM and RAM partitions
US5303302A (en) * 1992-06-18 1994-04-12 Digital Equipment Corporation Network packet receiver with buffer logic for reassembling interleaved data packets
US5452330A (en) * 1992-07-06 1995-09-19 Digital Equipment Corporation Bus-oriented switching system for asynchronous transfer mode
US5359592A (en) * 1993-06-25 1994-10-25 Stratacom, Inc. Bandwidth and congestion control for queue channels in a cell switching communication controller

Also Published As

Publication number Publication date
WO1995015526A1 (en) 1995-06-08
US5600820A (en) 1997-02-04
CA2159459C (en) 2000-04-18

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