CA2170458A1 - Multi-Cluster Computer System - Google Patents

Multi-Cluster Computer System

Info

Publication number
CA2170458A1
CA2170458A1 CA2170458A CA2170458A CA2170458A1 CA 2170458 A1 CA2170458 A1 CA 2170458A1 CA 2170458 A CA2170458 A CA 2170458A CA 2170458 A CA2170458 A CA 2170458A CA 2170458 A1 CA2170458 A1 CA 2170458A1
Authority
CA
Canada
Prior art keywords
data
cluster
clusters
broadcast
destination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2170458A
Other languages
French (fr)
Other versions
CA2170458C (en
Inventor
Satoshi Zinguuzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2170458A1 publication Critical patent/CA2170458A1/en
Application granted granted Critical
Publication of CA2170458C publication Critical patent/CA2170458C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring

Abstract

A multi-cluster computer system includes a plurality of clusters and a crossbar network for connecting the clusters. Each cluster includes processors, a shared memory, local network, data holding memory, shared memory access mechanism, data transfer mechanism. The data holding memory stores data to be broadcasted. The shared memory access mechanism transfers broadcast data from the shared memory to the data holding memory when one of the processors requests a broadcast. The data transfer mechanism transfers the broadcast data from the data holding mechanism to a plurality of destination clusters one after another. Each cluster may include parameter holding memory. The parameter holding memory stores parameters for each of the destination clusters. Each parameter includes information indicative of a corresponding destination cluster and an address at which the broadcast data is stored. The data transfer mechanism transfers the broadcast data to a destination cluster along with corresponding one of the parameters.
CA002170458A 1995-02-28 1996-02-27 Multi-cluster computer system Expired - Fee Related CA2170458C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7039547A JPH08235141A (en) 1995-02-28 1995-02-28 Information processing system
JP39547/1995 1995-02-28

Publications (2)

Publication Number Publication Date
CA2170458A1 true CA2170458A1 (en) 1996-08-29
CA2170458C CA2170458C (en) 2000-04-25

Family

ID=12556090

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002170458A Expired - Fee Related CA2170458C (en) 1995-02-28 1996-02-27 Multi-cluster computer system

Country Status (4)

Country Link
US (1) US5890007A (en)
JP (1) JPH08235141A (en)
CA (1) CA2170458C (en)
DE (1) DE19607531C2 (en)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3169856B2 (en) * 1997-05-29 2001-05-28 甲府日本電気株式会社 Multi-node information processing system
JPH1185718A (en) * 1997-09-05 1999-03-30 Nec Corp Parallel computer system
US6185662B1 (en) 1997-12-22 2001-02-06 Nortel Networks Corporation High availability asynchronous computer system
US6779036B1 (en) 1999-07-08 2004-08-17 International Business Machines Corporation Method and apparatus for achieving correct order among bus memory transactions in a physically distributed SMP system
US6467012B1 (en) 1999-07-08 2002-10-15 International Business Machines Corporation Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors
US6442597B1 (en) 1999-07-08 2002-08-27 International Business Machines Corporation Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memory
US6484220B1 (en) * 1999-08-26 2002-11-19 International Business Machines Corporation Transfer of data between processors in a multi-processor system
US6591348B1 (en) 1999-09-09 2003-07-08 International Business Machines Corporation Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system
US6782537B1 (en) * 1999-09-23 2004-08-24 International Business Machines Corporation Establishing a communicator across multiple processes in a multithreaded computing environment
US6587930B1 (en) 1999-09-23 2003-07-01 International Business Machines Corporation Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock
US6725307B1 (en) 1999-09-23 2004-04-20 International Business Machines Corporation Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
US7891004B1 (en) 1999-10-06 2011-02-15 Gelvin David C Method for vehicle internetworks
US6457085B1 (en) 1999-11-04 2002-09-24 International Business Machines Corporation Method and system for data bus latency reduction using transfer size prediction for split bus designs
US6516379B1 (en) 1999-11-08 2003-02-04 International Business Machines Corporation Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system
US7529799B2 (en) 1999-11-08 2009-05-05 International Business Machines Corporation Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
US6523076B1 (en) 1999-11-08 2003-02-18 International Business Machines Corporation Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks
US6606676B1 (en) 1999-11-08 2003-08-12 International Business Machines Corporation Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system
US6684279B1 (en) 1999-11-08 2004-01-27 International Business Machines Corporation Method, apparatus, and computer program product for controlling data transfer
US6529990B1 (en) 1999-11-08 2003-03-04 International Business Machines Corporation Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system
US6542949B1 (en) 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for increased performance of a parked data bus in the non-parked direction
US6535941B1 (en) 1999-11-08 2003-03-18 International Business Machines Corporation Method and apparatus for avoiding data bus grant starvation in a non-fair, prioritized arbiter for a split bus system with independent address and data bus grants
US6965922B1 (en) 2000-04-18 2005-11-15 International Business Machines Corporation Computer system and method with internal use of networking switching
US6807557B1 (en) 2000-05-31 2004-10-19 International Business Machines Corporation Method, system and program products for providing clusters of a computing environment
US7487152B1 (en) 2000-05-31 2009-02-03 International Business Machines Corporation Method for efficiently locking resources of a global data repository
US7185076B1 (en) 2000-05-31 2007-02-27 International Business Machines Corporation Method, system and program products for managing a clustered computing environment
US6658525B1 (en) 2000-09-28 2003-12-02 International Business Machines Corporation Concurrent access of an unsegmented buffer by writers and readers of the buffer
WO2002097557A2 (en) * 2001-04-03 2002-12-05 Captaris, Inc. System, method, and computer program for flow control in a distributed broadcast-route network with reliable transport links
JP3508857B2 (en) * 2001-07-31 2004-03-22 日本電気株式会社 Data transfer method between nodes and data transfer device
WO2003034269A1 (en) * 2001-10-12 2003-04-24 Pts Corporation Method of performing a fft transform on parallel processors
JP4181839B2 (en) * 2002-09-30 2008-11-19 キヤノン株式会社 System controller
US6954821B2 (en) * 2003-07-31 2005-10-11 Freescale Semiconductor, Inc. Crossbar switch that supports a multi-port slave device and method of operation
US7694064B2 (en) * 2004-12-29 2010-04-06 Hewlett-Packard Development Company, L.P. Multiple cell computer systems and methods
US8122078B2 (en) * 2006-10-06 2012-02-21 Calos Fund, LLC Processor with enhanced combined-arithmetic capability
US7822841B2 (en) * 2007-10-30 2010-10-26 Modern Grids, Inc. Method and system for hosting multiple, customized computing clusters
FR2925187B1 (en) * 2007-12-14 2011-04-08 Commissariat Energie Atomique SYSTEM COMPRISING A PLURALITY OF TREATMENT UNITS FOR EXECUTING PARALLEL STAINS BY MIXING THE CONTROL TYPE EXECUTION MODE AND THE DATA FLOW TYPE EXECUTION MODE
JP5212478B2 (en) * 2008-11-06 2013-06-19 富士通株式会社 Control device, data transfer device, information processing device, arithmetic processing device, and control method for information processing device
CN101702721B (en) * 2009-10-26 2011-08-31 北京航空航天大学 Reconfigurable method of multi-cluster system
CN105988970B (en) * 2015-02-12 2019-10-01 华为技术有限公司 The processor and chip of shared storing data
GB2621195A (en) * 2022-08-01 2024-02-07 Advanced Risc Mach Ltd Complex rendering using tile buffers

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010477A (en) * 1986-10-17 1991-04-23 Hitachi, Ltd. Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations
US4933936A (en) * 1987-08-17 1990-06-12 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Distributed computing system with dual independent communications paths between computers and employing split tokens
EP0509055A4 (en) * 1990-01-05 1994-07-27 Maspar Computer Corp Parallel processor memory system
IL97315A (en) * 1990-02-28 1994-10-07 Hughes Aircraft Co Multiple cluster signal processor
JP2926859B2 (en) * 1990-04-04 1999-07-28 松下電器産業株式会社 Parallel processing system
JP2945726B2 (en) * 1990-08-03 1999-09-06 松下電器産業株式会社 Parallel processing system
JPH04287153A (en) * 1991-03-18 1992-10-12 Fujitsu Ltd Parallel computer system
US5428803A (en) * 1992-07-10 1995-06-27 Cray Research, Inc. Method and apparatus for a unified parallel processing architecture
EP0588030A3 (en) * 1992-09-17 1995-01-25 Ibm Master microchannel apparatus for converting to switch architecture.
JP2977688B2 (en) * 1992-12-18 1999-11-15 富士通株式会社 Multi-processing device, method, and processor used for the same
JP2819982B2 (en) * 1993-03-18 1998-11-05 株式会社日立製作所 Multiprocessor system with cache match guarantee function that can specify range
JP3639317B2 (en) * 1993-12-08 2005-04-20 富士通株式会社 Data transfer control device
JP2739830B2 (en) * 1995-02-08 1998-04-15 日本電気株式会社 Data communication device for multiprocessor system
US5590301A (en) * 1995-10-06 1996-12-31 Bull Hn Information Systems Inc. Address transformation in a cluster computer system

Also Published As

Publication number Publication date
DE19607531A1 (en) 1996-09-26
JPH08235141A (en) 1996-09-13
CA2170458C (en) 2000-04-25
DE19607531C2 (en) 1999-10-21
US5890007A (en) 1999-03-30

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