CA2177276C - Method for fabricating self-assembling microstructures - Google Patents
Method for fabricating self-assembling microstructures Download PDFInfo
- Publication number
- CA2177276C CA2177276C CA002177276A CA2177276A CA2177276C CA 2177276 C CA2177276 C CA 2177276C CA 002177276 A CA002177276 A CA 002177276A CA 2177276 A CA2177276 A CA 2177276A CA 2177276 C CA2177276 C CA 2177276C
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- Canada
- Prior art keywords
- substrate
- shaped blocks
- blocks
- top surface
- gallium arsenide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H01L2924/30—Technical effects
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- H01L2924/30105—Capacitance
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
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- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/023—Mount members, e.g. sub-mount members
- H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
- H01S5/02326—Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
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- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
Abstract
A method for assembling onto a substrate through fluid transport. The microstructures being shaped blocks (19) self-align into recessed regions (55) located on a substrate (50) such that the microstructure becomes integral with the substrate. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then ppoured evenl y over the top surface (53) of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the sur face of the substrate, self-aligns, and engages into a recessed region.
Description
METHOD FOR FABRICATING SELF-ASSEMBLING MICROSTRUCTURES
BACRGROUND OF THE INVENTION
The present invention relates to the field of electronic integrated circuits. The invention is illustrated in an example with regard to the manufacture of gallium arsenide microstructures onto a silicon substrate, but it will be recognized that the invention will have a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of devices containing silicon based electronic devices integrated with a gallium arsenide based microstructures (or devices) such as light emitting diodes (LED), lasers, tunneling transistors, Gunn oscillators, integrated circuits, solar collectors, and others.
Industry currently needs a cost effective, efficient, and practical method for assembling a higher cost microstructure onto a lower cost commercially available substrate. In particular, a material such as gallium arsenide possesses substantially better characteristics for some specific electronic and opto-electronic applications rather than materials such as silicon. However, in the fabrication of gallium arsenide devices, substantial regions of a gallium arsenide wafer are typically unused and wasted. Such unused regions generally create an inefficient use of precious die area. In addition, processing gallium arsenide typically requires special techniques, chemicals, and eguipment, and is therefore costly.
Other applications such as very large scale integrated (VLSI) circuits may be better fabricated in silicon rather than gallium arsenide. In still further applications, it may be desirable to produce integrated circuits having characteristics of both types of materials. Accordingly, industry needs to develop an effective method of fabricating a gallium arsenide device integrated with a silicon based integrated circuit. The resulting structure of such method includes advantages of both gallium arsenide and silicon based devices.
Methods such as flip chip bonding, lift off methods, and others, generally require large areas of a substrate and are incompatible with a micron sized state-of-art microstructure. Such methods often create.difficulty in positioning a particle onto a substrate. Accordingly, industry needs to develop an effective WO 95,17005 2 1 7 7 2 7 6 PCT/US94/14152 =
BACRGROUND OF THE INVENTION
The present invention relates to the field of electronic integrated circuits. The invention is illustrated in an example with regard to the manufacture of gallium arsenide microstructures onto a silicon substrate, but it will be recognized that the invention will have a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of devices containing silicon based electronic devices integrated with a gallium arsenide based microstructures (or devices) such as light emitting diodes (LED), lasers, tunneling transistors, Gunn oscillators, integrated circuits, solar collectors, and others.
Industry currently needs a cost effective, efficient, and practical method for assembling a higher cost microstructure onto a lower cost commercially available substrate. In particular, a material such as gallium arsenide possesses substantially better characteristics for some specific electronic and opto-electronic applications rather than materials such as silicon. However, in the fabrication of gallium arsenide devices, substantial regions of a gallium arsenide wafer are typically unused and wasted. Such unused regions generally create an inefficient use of precious die area. In addition, processing gallium arsenide typically requires special techniques, chemicals, and eguipment, and is therefore costly.
Other applications such as very large scale integrated (VLSI) circuits may be better fabricated in silicon rather than gallium arsenide. In still further applications, it may be desirable to produce integrated circuits having characteristics of both types of materials. Accordingly, industry needs to develop an effective method of fabricating a gallium arsenide device integrated with a silicon based integrated circuit. The resulting structure of such method includes advantages of both gallium arsenide and silicon based devices.
Methods such as flip chip bonding, lift off methods, and others, generally require large areas of a substrate and are incompatible with a micron sized state-of-art microstructure. Such methods often create.difficulty in positioning a particle onto a substrate. Accordingly, industry needs to develop an effective WO 95,17005 2 1 7 7 2 7 6 PCT/US94/14152 =
method of fabricating higher cost materials such as a gallium arsenide microstructure onto a lower cost substrate such as silicon.
industry utilizes or has proposed several methods for fabricating individual electronic components (or generally microstructures) and assembling such structures onto a substrate.
One approach is to grow gallium arsenide devices directly onto a silicon substrate. This approach becomes limiting because the lattice structure of gallium arsenide mismatches that of silicon. In addition, growing gallium arsenide onto silicon is inherently difficult and therefore costly. Accordingly, gallium arsenide can not efficiently be grown on a silicon substrate.
Another approach is described by Yando in U.S. Patent No.
industry utilizes or has proposed several methods for fabricating individual electronic components (or generally microstructures) and assembling such structures onto a substrate.
One approach is to grow gallium arsenide devices directly onto a silicon substrate. This approach becomes limiting because the lattice structure of gallium arsenide mismatches that of silicon. In addition, growing gallium arsenide onto silicon is inherently difficult and therefore costly. Accordingly, gallium arsenide can not efficiently be grown on a silicon substrate.
Another approach is described by Yando in U.S. Patent No.
3,439,416. Yando describes components or structures placed, trapped, or vibrated on an array of magnets. Such magnets include magnetized layers alternating with non-magnetized layers to form a laminated structure. Components are matched onto the array of magnets forming an assembly thereof. However, severe limitations exist on the shape, size, and distribution of the components. Component width must match the spacing of the magnetic layers and the distribution of components are constrained by the parallel geometry of lamination. In addition, self-alignment of components requires the presence of the laminated structure. Furthermore, the structures disclosed by Yando typically possess millimeter sized dimensions and are therefore generally incompatible with micron sized integrated circuit structures.
Accordingly, the method and structure disclosed by Yando is thereby too large and complicated to be effective for assembling a state-of-art microstructure or component onto a substrate.
Another approach involves mating physical features between a packaged surface mount device and substrate as described in U.S. Patent No. 5,034,802, Liebes, Jr. et al. The assembly process described requires a human or robotics arm to physically pick, align, and attach a centimeter sized packaged surface mount device onto a substrate. Such process is limiting because of the need for the human or robotics arm. The human or robotics arm assembles each packaged device onto the substrate one-by-one and not simultaneously, thereby limiting the efficiency and effectiveness of the operation.
Moreover, the method uses centimeter sized devices (or packed surface mount integrated circuits), and would have little applicability with micron sized integrated circuits in die form.
Another approach, such as the one described in U.S. =
Patent No. 4,542,397, Siegelsen et al. involves a method of placing parallelogram shaped structures onto a substrate by mechanical vibration. Alternatively, the method may also employ pulsating air through apertures in the support surface (or substrate). A
limitation to the method includes an apparatus capable of vibrating the structures, or an apparatus for pulsating air through the apertures. Moreover, the method described relies upon centimeter-sized dies and would have little applicability with state-of-art micron sized structures.
A further approach such as that described in U.S. Patent No. 4,194,668 by Akyurek discloses an apparatus for aligning and soldering electrode pedestals onto solderable ohmic anode contacts.
The anode contacts are portions of individual smiconductor chips located on a wafer. Assembling the structures requires techniques of sprinkling pedestals onto a mask and then electromagnetic shaking such pedestals for alignment. The method becomes limiting bacause of the need for a shaking apparatus for the electromaqnetic shakinq step. In addition, the method also requires a feed surface gestly sloping to the mask for transferring electronic pedestals onto the mask. Moreover, the method is solely in context to electrode pedestals and silicon wafers; thereby limiting the use of such method to these structures.
Still another approach requires assembling integrated circuits onto a substrate through electrostatic forces as described in US Patent No. 5,355,577 issued on October 18, 1994 by Cohn.
The electrostatic forces vibrate particles such that the particles are arranged at a state of minimum potential energy. A limitation with such method includes providing an apparatus capable of vibrating particles with electrostatic forces. Moreover, the method of Cohn creates damaqe to a portion of the inteqrated circuits by mechanically vibrating them against each other and is also generally ineffective. Accordinqly the method typically becomes incompatible with a state-of-art microstructure.
rrom the above it is seen that a method of assembling a microstructure onto a substrate that is compact, low cost, efficient, reliable, and requires little maintenance is desired.
SQldtARY oa THE INVlNTION
The present invention pertains to a method and resulting structure for assembling a microstructure onto a substrate. In particular, the method includes transferring shaped blocks or generally structures via a fluid onto a top surface of a substrate having recessed reqions or generally binding sites or receptors.
Upon transferring, the blocks self-aliqn through their shape into the recoassd regions, and integrate thereon. The resultinq structure may include a variety of useful electronic integrated circuits containing silicon based electronic devices integrated with a gallium arsenide based microstructures such as a light emitting diodes (LED), lasers, tunnelinq transistors, Gunn oscillator$, integrated circuits, solar collectors, and others.
Accordingly, the method and structure disclosed by Yando is thereby too large and complicated to be effective for assembling a state-of-art microstructure or component onto a substrate.
Another approach involves mating physical features between a packaged surface mount device and substrate as described in U.S. Patent No. 5,034,802, Liebes, Jr. et al. The assembly process described requires a human or robotics arm to physically pick, align, and attach a centimeter sized packaged surface mount device onto a substrate. Such process is limiting because of the need for the human or robotics arm. The human or robotics arm assembles each packaged device onto the substrate one-by-one and not simultaneously, thereby limiting the efficiency and effectiveness of the operation.
Moreover, the method uses centimeter sized devices (or packed surface mount integrated circuits), and would have little applicability with micron sized integrated circuits in die form.
Another approach, such as the one described in U.S. =
Patent No. 4,542,397, Siegelsen et al. involves a method of placing parallelogram shaped structures onto a substrate by mechanical vibration. Alternatively, the method may also employ pulsating air through apertures in the support surface (or substrate). A
limitation to the method includes an apparatus capable of vibrating the structures, or an apparatus for pulsating air through the apertures. Moreover, the method described relies upon centimeter-sized dies and would have little applicability with state-of-art micron sized structures.
A further approach such as that described in U.S. Patent No. 4,194,668 by Akyurek discloses an apparatus for aligning and soldering electrode pedestals onto solderable ohmic anode contacts.
The anode contacts are portions of individual smiconductor chips located on a wafer. Assembling the structures requires techniques of sprinkling pedestals onto a mask and then electromagnetic shaking such pedestals for alignment. The method becomes limiting bacause of the need for a shaking apparatus for the electromaqnetic shakinq step. In addition, the method also requires a feed surface gestly sloping to the mask for transferring electronic pedestals onto the mask. Moreover, the method is solely in context to electrode pedestals and silicon wafers; thereby limiting the use of such method to these structures.
Still another approach requires assembling integrated circuits onto a substrate through electrostatic forces as described in US Patent No. 5,355,577 issued on October 18, 1994 by Cohn.
The electrostatic forces vibrate particles such that the particles are arranged at a state of minimum potential energy. A limitation with such method includes providing an apparatus capable of vibrating particles with electrostatic forces. Moreover, the method of Cohn creates damaqe to a portion of the inteqrated circuits by mechanically vibrating them against each other and is also generally ineffective. Accordinqly the method typically becomes incompatible with a state-of-art microstructure.
rrom the above it is seen that a method of assembling a microstructure onto a substrate that is compact, low cost, efficient, reliable, and requires little maintenance is desired.
SQldtARY oa THE INVlNTION
The present invention pertains to a method and resulting structure for assembling a microstructure onto a substrate. In particular, the method includes transferring shaped blocks or generally structures via a fluid onto a top surface of a substrate having recessed reqions or generally binding sites or receptors.
Upon transferring, the blocks self-aliqn through their shape into the recoassd regions, and integrate thereon. The resultinq structure may include a variety of useful electronic integrated circuits containing silicon based electronic devices integrated with a gallium arsenide based microstructures such as a light emitting diodes (LED), lasers, tunnelinq transistors, Gunn oscillator$, integrated circuits, solar collectors, and others.
Accordingly, the present invention provides a method of assembling a microstructure on a substrate, said substrate comprising a top surface with at least one recessed region thereon, comprising the steps of: providing a plurality of shaped blocks, said shaped block comprising an integrated circuit thereon; transferring said shaped blocks into a fluid to form a slurry; and dispensing said slurry over said substrate at a rate where at least one of said shaped blocks is disposed into a recessed region.
In one specific embodiment, the method provides assembling a microstructure such as a micron sized block onto a substrate.
The substrate includes a top surface with at least one recessed region thereon and may be either a silicon wafer, gallium arsenide wafer, glass substrate, ceramic substrate, or others.
The substrate may also be a plastic sheet fabricated form a technique such as stamping, injection molding, among others. The slurry is dispensed evenly over the substrate at a rate where at least one of the shaped blocks is disposed into a recessed region. Dispensing occurs at substantially a laminar flow and allows a portion of the shaped blocks to self-align into the recessed region.
The present invention also provides a method of fabricating shaped blocks comprising an integrated circuit, comprising the steps of: providing a substrate having a top surface and a backside; growing a sacrificial layer overlying said top surface;
forming a block layer overlying said top surface; masking and etching said block layer up to said sacrificial layer forming a plurality of shaped blocks on and in contact with said sacrificial layer; depositing a filler layer onto a top surface of said shaped blocks and exposed portions of said sacrificial layer; attaching a top surface of an intermediate substrate onto said top surface of said shaped blocks; removing said substrate from said shaped blocks; processing portions of said shaped blocks, said processing step forming integrated circuits on said 4a blocks; and removing said filler layer and said shaped blocks from said intermediate substrate.
In one embodiment, the method provides, for example, shaped blocks having a trapezoidal profile from an improved fabrication process. Fabrication includes providing a second substrate having a top surface, and growing a sacrificial layer overlying the top surface. A step of forming a block layer overlying the top surface is then performed. Masking and etching the block layer up to the sacrificial layer creates trapezoidal shaped blocks thereon. A step of preferential etching the sacrificial layer lifts off each trapezoidal shaped block. Such blocks are then rinsed and transferred into a solution forming the slurry.
In a further aspect, the present invention provides a microstructure integral with a substrate comprising: a substrate having a plurality of recessed regions thereon; and a plurality of shaped blocks integral with said recessed regions, said shaped blocks comprising an integrated circuit thereon; wherein said shaped blocks each include a trapezoidal profile comprising a truncated pyramid shape including a top surface with four sides protruding therefrom to a base, said base having a length between about 10 pm and about 50 pm, and a width between 10 pm and about 50 pm, and each of said four sides having a height between about 5 pm and about 15 um, and each of said recessed regions in said substrate is shaped substantially trapezoidal to complement each of said shaped blocks.
Still a further embodiment, the shaped block comprises a truncated pyramid shaped gallium arsenide structure. The truncated pyramid shaped structure includes a base with four sides protruding therefrom to a top surface. Each side creates an angle between about 500 and about 700 from the base to a side.
Each side may also have a height between about 5 pm and about 15 pm. The base may have a length between about 10 pm and about 50 pm, and a width between 10 pm and about 50 pm.
The improved method and resulting structure are in context to a trapezoidal shaped block made of gallium arsenide assembled 4b onto a silicon substrate merely for illustrative purposes only.
The shaped blocks may also include a cylindrical shape, pyramid shape, rectangular shape, square shape, T-shape, kidney shape, or the like (symmetrical or asymmetrical), and combinations thereof.
Generally, the shape of the block allows the block to closely insert into a similarly shaped recessed region or receptor on =WO 95117005 2 1 7 7 2 7 6 PCT/US94/14152 a substrate. The shaped blocks also comprise a material such as gallium aluminum arsenide, silicon, diamond, germanium, other group Ill-V and II-VI compounds, multilayered structures, among others.
Such multilayered structure may include metals, insulators such as 5 silicon dioxide, silicon nitride, and the like, and combinations thereof.
A further understanding of the nature and advantages of the invention will become apparent by reference to the remaining portions of the specification and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a gallium arsenide wafer having a molecular beam epitaxy (MBE) grown gallium arsenide layer for the improved method of fabrication;
Fig. 2 is an illustration of trapezoidal shaped gallium arsenide blocks etched from an MBE grown gallium arsenide layer;
Fig. 3 is an illustration for a lift-off step of gallium arsenide blocks;
Fig. 4 is an illustration of a portion of an alternative lift-off step using a intermediate substrate;
Fig. 5 is an illustration of another portion of the alternative lift-off step of Fig. 4;
Fig. 6 is an illustration of each gallium arsenide block self-aligning onto a silicon substrate;
Fig. 7 is an embodiment of a microstructure assembled onto the silicon substrate according to the improved method depicted by Figs. 1-3 and 6;
Fig. 8 is an alternative embodiment of a microstructure assembled onto a substrate;
Fig. 9 is an embodiment of a microstructure assembled onto a substrate forming a gallium arsenide diode;
Fig. 10 is an alternative embodiment of a microstructure assembled onto a substrate forming a gallium arsenide diode;
Fig. 11 is a further alternative embodiment of a microstructure assembled onto a substrate forming a gallium arsenide diode;
Fig. 12 is an illustration of examples of shaped blocks;
Fig. 13 is a photograph of an assembled microstructure according to the experiment; and Fig. 14 is a photograph of an operational photo diode according to the experiment.
Fig. 15 is a photograph of a metallized ring layer overlying a gallium arsenide block;
Fig. 16 is a current-voltage representation for a gallium arsenide diode according to the experiment; and WO 95/17005 217 7 2 7 6 PCT/US94/14152 =
In one specific embodiment, the method provides assembling a microstructure such as a micron sized block onto a substrate.
The substrate includes a top surface with at least one recessed region thereon and may be either a silicon wafer, gallium arsenide wafer, glass substrate, ceramic substrate, or others.
The substrate may also be a plastic sheet fabricated form a technique such as stamping, injection molding, among others. The slurry is dispensed evenly over the substrate at a rate where at least one of the shaped blocks is disposed into a recessed region. Dispensing occurs at substantially a laminar flow and allows a portion of the shaped blocks to self-align into the recessed region.
The present invention also provides a method of fabricating shaped blocks comprising an integrated circuit, comprising the steps of: providing a substrate having a top surface and a backside; growing a sacrificial layer overlying said top surface;
forming a block layer overlying said top surface; masking and etching said block layer up to said sacrificial layer forming a plurality of shaped blocks on and in contact with said sacrificial layer; depositing a filler layer onto a top surface of said shaped blocks and exposed portions of said sacrificial layer; attaching a top surface of an intermediate substrate onto said top surface of said shaped blocks; removing said substrate from said shaped blocks; processing portions of said shaped blocks, said processing step forming integrated circuits on said 4a blocks; and removing said filler layer and said shaped blocks from said intermediate substrate.
In one embodiment, the method provides, for example, shaped blocks having a trapezoidal profile from an improved fabrication process. Fabrication includes providing a second substrate having a top surface, and growing a sacrificial layer overlying the top surface. A step of forming a block layer overlying the top surface is then performed. Masking and etching the block layer up to the sacrificial layer creates trapezoidal shaped blocks thereon. A step of preferential etching the sacrificial layer lifts off each trapezoidal shaped block. Such blocks are then rinsed and transferred into a solution forming the slurry.
In a further aspect, the present invention provides a microstructure integral with a substrate comprising: a substrate having a plurality of recessed regions thereon; and a plurality of shaped blocks integral with said recessed regions, said shaped blocks comprising an integrated circuit thereon; wherein said shaped blocks each include a trapezoidal profile comprising a truncated pyramid shape including a top surface with four sides protruding therefrom to a base, said base having a length between about 10 pm and about 50 pm, and a width between 10 pm and about 50 pm, and each of said four sides having a height between about 5 pm and about 15 um, and each of said recessed regions in said substrate is shaped substantially trapezoidal to complement each of said shaped blocks.
Still a further embodiment, the shaped block comprises a truncated pyramid shaped gallium arsenide structure. The truncated pyramid shaped structure includes a base with four sides protruding therefrom to a top surface. Each side creates an angle between about 500 and about 700 from the base to a side.
Each side may also have a height between about 5 pm and about 15 pm. The base may have a length between about 10 pm and about 50 pm, and a width between 10 pm and about 50 pm.
The improved method and resulting structure are in context to a trapezoidal shaped block made of gallium arsenide assembled 4b onto a silicon substrate merely for illustrative purposes only.
The shaped blocks may also include a cylindrical shape, pyramid shape, rectangular shape, square shape, T-shape, kidney shape, or the like (symmetrical or asymmetrical), and combinations thereof.
Generally, the shape of the block allows the block to closely insert into a similarly shaped recessed region or receptor on =WO 95117005 2 1 7 7 2 7 6 PCT/US94/14152 a substrate. The shaped blocks also comprise a material such as gallium aluminum arsenide, silicon, diamond, germanium, other group Ill-V and II-VI compounds, multilayered structures, among others.
Such multilayered structure may include metals, insulators such as 5 silicon dioxide, silicon nitride, and the like, and combinations thereof.
A further understanding of the nature and advantages of the invention will become apparent by reference to the remaining portions of the specification and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a gallium arsenide wafer having a molecular beam epitaxy (MBE) grown gallium arsenide layer for the improved method of fabrication;
Fig. 2 is an illustration of trapezoidal shaped gallium arsenide blocks etched from an MBE grown gallium arsenide layer;
Fig. 3 is an illustration for a lift-off step of gallium arsenide blocks;
Fig. 4 is an illustration of a portion of an alternative lift-off step using a intermediate substrate;
Fig. 5 is an illustration of another portion of the alternative lift-off step of Fig. 4;
Fig. 6 is an illustration of each gallium arsenide block self-aligning onto a silicon substrate;
Fig. 7 is an embodiment of a microstructure assembled onto the silicon substrate according to the improved method depicted by Figs. 1-3 and 6;
Fig. 8 is an alternative embodiment of a microstructure assembled onto a substrate;
Fig. 9 is an embodiment of a microstructure assembled onto a substrate forming a gallium arsenide diode;
Fig. 10 is an alternative embodiment of a microstructure assembled onto a substrate forming a gallium arsenide diode;
Fig. 11 is a further alternative embodiment of a microstructure assembled onto a substrate forming a gallium arsenide diode;
Fig. 12 is an illustration of examples of shaped blocks;
Fig. 13 is a photograph of an assembled microstructure according to the experiment; and Fig. 14 is a photograph of an operational photo diode according to the experiment.
Fig. 15 is a photograph of a metallized ring layer overlying a gallium arsenide block;
Fig. 16 is a current-voltage representation for a gallium arsenide diode according to the experiment; and WO 95/17005 217 7 2 7 6 PCT/US94/14152 =
Fig. 17 is a current-voltage representation for a gallium arsenide/aluminum arsenide resonant-tunneling diode according to the experiment.
DESCRIPTION OF SPECIFIC EMBODIMENTS
With reference to Figs. 1-17, the present invention provides an improved method of fabricating a microstructure onto a substrate, and an improved resulting structure. Figs. 1-17 are, for example, in context to fabricating and assembling a shaped gallium arsenide block onto a silicon substrate for illustrative purposes only.
In the assembly of a gallium arsenide block onto a silicon wafer, trapezoidal shaped blocks self-align into inverted trapezoidal shaped recessed regions located on the top surface of the ailicon wafer. Steps for such method include forming the gallium arsenide blocks, transferring the blocks into a solution forming a slurry, and spreading the slurry evenly over the top surface of a silicon substrate having recessed regions. During the spreading steps, the blocks self-align and settle into the recessed regions while being transported with the fluid across the top surface. The details of fabricating the silicon substrate having recessed regions will be discussed in detail below after a brief discussion of forming the gallium arsenide blocks.
In a specific embodiment, the method provides as an example a step of forming trapezoidal shaped blocks from a gallium arsenide wafer. Such stap includes providing a gallium arsenide wafer 10 as illustrated in Fig. 1. The method also provides forming sacrificial layer 13by chemical vapor deposition, sputtering, or the like overlying top surface 15 of gallium arsenide wafer 10. Such sacrificial layer 13 includes, for example, aluminum arsenide. other sacrificial layers may include indium phosphate, silicon dioxide, photoresist, among other materials capable of being selectively etched. Of course, the sacrificial layer used depends upon the particular application. For an aluminum arsenide eacrificial layer, thickness for such layer is between about 0.1 pm and about 5.0 um, and preferably at about 1gm. Before forming sacrificial layer 13, a step of etching top surface 15 by methods such as wet etching, plasma etching, or reactive ion etching clears off any native oxide.
Alternatively, a step of desorption in the presence of arsenic removes the native oxide layer. A subsequent step of preferential etching (to be discussed in detail later) removes sacrificial layer 13 to facilitate the lift-off of each gallium arsenide block (also called a mesa shaped or trapezoidal shaped or truncated pyramid shaped structure) formed overlying sacrificial layer 13.
OWO 95/17005 2 1 7 7 2 7 6 pCTfUS94/14152 in Fig. 1, gallium arsenide layer 17 forms overlying sacrificial layer 13. Such gallium arsenide layer may be fabricated by methods including molecular beam epitaxy, chemical vapor deposition, and others. The thickness (T) of the gallium arsenide layer is at least about 10 nm and greater, and preferably at about 10 um and greater, depending upon the particular application.
To produce the desired dimensions for the block, the improved method provides the steps of masking and etching gallium arsenide layer 17. Fig. 2 illustrates gallium arsenide substrate 10 after such masking and etching steps and includes gallium arsenide blocks 19 and a photoresist layer 21 overlying gallium arsenide layer 17 (not shown). Generally, unexposed portions of gallium arsenide layer 17 are etched up to sacrificial layer 13 as illustrated in Fig.
2. Such etching step provides a plurality of shaped gallium arsenide blocks 19. For the present example, the shaped blocks include a trapezoidal profile or truncated pyramid shape. Such trapezoidal profile may be fabricated by methods of wet etching, plasma etching, ion milling, reactive ion etching, among others, depending on the application.
Generally, a wet etch produces a aloping profile along the sides or edges of each gallium arsenide block. For mask edges parallel to the [110] direction, a wet etch produces an outward sloping profile as illustrated in Fig 2. Alternatively, mask edges parallel to the [110] direction, produces an inward sloping (or reverse mesa) profile. The outward sloping profile provides a desired shape which integrates into a silicon substrate having recessed regions shaped in a complementary manner.
Ion milling produces gallium arsenide blocks with outward sloping profiles, depending upon the beam angle. Beam angle is adjusted between about 00 to about 300 from a normal to top surface 15 on gallium arsenide substrate 10. To create the outward sloping (or truncated pyramid shape) profile for each block, the entire structure is typically rotated during such etching step.
Reactive ion etching (RIE) also produces gallium arsenide blocks having a shaped profile. Generally, such etching method creates blocks having undercut sides or a reverse mesa profile.
Depending upon variables such as the etchant, pressure, equipment, and others, such etching method may create blocks having substantially consistent shapes and/or profiles.
After etching the MEE grown layer, trapezoidal shaped blocks are removed through a lift-off technique from gallium arsenide substrate 10 by preferential etching sacrificial layer 13 as illustrated in Fig. 3. Such lift-off technique occurs by, for example, a preferential wet etch of the aluminum arsenide sacrificial layer. In the gallium araenide example, such wet etching step ia typically performed by a chemical such as a hydrofluoric acid solution or the like. The etchant used substantially etches the sacrificial layer but does not aggressively attack gallium arsenide blocks and/or substrates.
After separatinq the gallium arsenide blocks from substrate 10, methods of diluting and decantinq the wet etchant solution remove the blocks from the solution. In the qallium arsenide example, the wet etchant is diluted and decanted usinq purified water, methanol, ethanol, or the like. Optionally, a rinsing step occurs after the dilutinq and decantinq step. The rinsinq step relies on solutions such as acetone, methanol, ethanol, or any other inert solution having low corrosive properties. Such solution also provides a medium (or fluid) for creatinq a mixture havinq blocks suspended therein or qenerally a slurry.
Instead of the lift-off technique illustrated in Fiq. 3, an alternative lift-off method creates intermediate structure 250 of Fiq. 4 from the qallium arsenide structure of Fig. 2. Such alternative lift-off method also promotes lift-off of the shaped blocksin applications where the devices are formed onto the backside of the blocks. As shown, the mlthod includes spreadinq a filler or wax layer 253 preferably high temperature wax overlyinq the top surface of exposed portions of sacrificial layer 13 and gaps 255 between each block 19. One such wax includes a product by the aas~e of TLCH WAX#made by TRANSENE Co., Inc. The method then includes inverting the gallium arsenide structure of Fig. 2 and attaching top surface 21 onto intermadiate substrate M. Such intermediate substrate is, for example, a silicon wafer or the like. However, prior to the attachinq step, intermadiate substrate surface 261 undergoes steps of etchinq off any native oxide preferably with a wet etchant such as hydrofluoric acid, and treating the cleaned surface with an adhesion promotor such as hexamethyldisilazane also called MtDS. In removing gallium arsenide substrate 10, backside 263 is lapped about 50 lim remains on substrate 10. The remaining thickness of substrate 10 is then etched up to aluminum arsenide layer 13. An etchant such as amsionium hydroxide and hydrogen peroxide (6:200' NH30H:A2O2) preferentially etches the gallium arsenide substrate up to aluminum arsenide layer 13. Accordingly, the aluminum arsenide layer acts aa an etch stop protecting qallium arsenide blocks 19.
Removinq aluminum arsenide layer 13 requires a step of wet etching using an etchant such as hydrofluaric acid. Such etchant typically removes aluminum arsenide layer 13 after a short dip in such solution. After the aluminum arsenide layer is completely removed, steps including masking, sputtering, and etchinq form metallized ring contacts 265 as illustrated in Fiq. S. Such metallized ring contacts were made by patterns formed from photoresist layer 267. The #Trade-mark ~WO95/17005 _ 217' 2' 6 PCT/US94/14152 metallization for such contacts include materials such as gold, aluminum, among others. Alternatively, other processing stepa such as etching, masking, implantation, diffusion, and the like may be performed on the blocks to create other profiles as well as active devicee thereon. A solution such as trichloroethane (TCA) dissolves the filler or wax disposed between each block 19 and photoresist layer 21, and lifts off the gallium arsenide blocks 19 from intermediate substrate 257. To decrease corrosion, the gallium arsenide blocks are transferred to an inert solution such as acetone, methanol, ethanol, or any other solution having low corrosive characteristics. Such inert solution and blocks are often called a mixture or generally a slurry.
The slurry comprises an inert solution (of fluid) and shaped blocks. Enough eolution exists in the slurry to allow the blocks to slide across the top surface of the substrate. Preferably, the amount of solution in the mixture is at least the same order as the amount of blocks. of course, the amount of solution necessary depends upon characteristics such as block size, block material, substrate size, substrate material, and solution. After preparation, the slurry is transferred or spread over top surface 53 of silicon substrate 50 as illustrated in Fig. 6. The details of the transferring technique are discussed below after a brief discussion in fabricating silicon substrate 50.
As shown in Fig. 6, siLicon substrate 50 comprises etched recessed regions 55. A variety of techniques including wet etching, plasma etching, reactive ion etching, ion milling, among others provide recessed regions 50, or generally trenches, receptors, or binding sites. Such techniques etch recessed regions 50 with a geometric profile which is complementary to block 19. In the silicon substrate, for example, each recessed region includes a trapezoidal profile or inverted truncated pyramid shape. The trapezoidal profile allows block 19 to self-align and fit closely into recessed region 50 via the improved transferring technique.
The transferring technique includes a step of evenly spreading or pouring the slurry over top surface 53. The transferring technique may be accomplished by pouring a vessel of slurry evenly over top surface 53. Alternatively, the slurry may also be transferred from a pipet, flask, beaker, or any other type of vessel and/or apparatus capable of evenly transferring the slurry over top surface 53. Generally, the slurry is poured over top surface 50 at a rate which allows substantial coverage of the top surface, but prevents blocks already disposed into the recessed regions from floating or popping out. Slurry flow is typically laminar but can be non-laminar, depending upon the particular application. In the gallium arsenide block example, the fluid flux over top surface 53 occurs at a velocity between about 0.01 mm/sec.
and about 100 mm/sec. Preferably, fluid flux occurs at about 1 mm/sec. At such flux rates, the blocks flow evenly with the fluid, tumble onto top surface 53, self-align, and settle into recessed 5 regions 55. Optionally, to prevent the blocks already disposed in the recessed regions from floating out, the transferring step may take place in a centrifuge or the like. A centrifuge, for example, places a force on the blocks already disposed in the recessed regions and thereby prevents such blocks from floating out with solution.
DESCRIPTION OF SPECIFIC EMBODIMENTS
With reference to Figs. 1-17, the present invention provides an improved method of fabricating a microstructure onto a substrate, and an improved resulting structure. Figs. 1-17 are, for example, in context to fabricating and assembling a shaped gallium arsenide block onto a silicon substrate for illustrative purposes only.
In the assembly of a gallium arsenide block onto a silicon wafer, trapezoidal shaped blocks self-align into inverted trapezoidal shaped recessed regions located on the top surface of the ailicon wafer. Steps for such method include forming the gallium arsenide blocks, transferring the blocks into a solution forming a slurry, and spreading the slurry evenly over the top surface of a silicon substrate having recessed regions. During the spreading steps, the blocks self-align and settle into the recessed regions while being transported with the fluid across the top surface. The details of fabricating the silicon substrate having recessed regions will be discussed in detail below after a brief discussion of forming the gallium arsenide blocks.
In a specific embodiment, the method provides as an example a step of forming trapezoidal shaped blocks from a gallium arsenide wafer. Such stap includes providing a gallium arsenide wafer 10 as illustrated in Fig. 1. The method also provides forming sacrificial layer 13by chemical vapor deposition, sputtering, or the like overlying top surface 15 of gallium arsenide wafer 10. Such sacrificial layer 13 includes, for example, aluminum arsenide. other sacrificial layers may include indium phosphate, silicon dioxide, photoresist, among other materials capable of being selectively etched. Of course, the sacrificial layer used depends upon the particular application. For an aluminum arsenide eacrificial layer, thickness for such layer is between about 0.1 pm and about 5.0 um, and preferably at about 1gm. Before forming sacrificial layer 13, a step of etching top surface 15 by methods such as wet etching, plasma etching, or reactive ion etching clears off any native oxide.
Alternatively, a step of desorption in the presence of arsenic removes the native oxide layer. A subsequent step of preferential etching (to be discussed in detail later) removes sacrificial layer 13 to facilitate the lift-off of each gallium arsenide block (also called a mesa shaped or trapezoidal shaped or truncated pyramid shaped structure) formed overlying sacrificial layer 13.
OWO 95/17005 2 1 7 7 2 7 6 pCTfUS94/14152 in Fig. 1, gallium arsenide layer 17 forms overlying sacrificial layer 13. Such gallium arsenide layer may be fabricated by methods including molecular beam epitaxy, chemical vapor deposition, and others. The thickness (T) of the gallium arsenide layer is at least about 10 nm and greater, and preferably at about 10 um and greater, depending upon the particular application.
To produce the desired dimensions for the block, the improved method provides the steps of masking and etching gallium arsenide layer 17. Fig. 2 illustrates gallium arsenide substrate 10 after such masking and etching steps and includes gallium arsenide blocks 19 and a photoresist layer 21 overlying gallium arsenide layer 17 (not shown). Generally, unexposed portions of gallium arsenide layer 17 are etched up to sacrificial layer 13 as illustrated in Fig.
2. Such etching step provides a plurality of shaped gallium arsenide blocks 19. For the present example, the shaped blocks include a trapezoidal profile or truncated pyramid shape. Such trapezoidal profile may be fabricated by methods of wet etching, plasma etching, ion milling, reactive ion etching, among others, depending on the application.
Generally, a wet etch produces a aloping profile along the sides or edges of each gallium arsenide block. For mask edges parallel to the [110] direction, a wet etch produces an outward sloping profile as illustrated in Fig 2. Alternatively, mask edges parallel to the [110] direction, produces an inward sloping (or reverse mesa) profile. The outward sloping profile provides a desired shape which integrates into a silicon substrate having recessed regions shaped in a complementary manner.
Ion milling produces gallium arsenide blocks with outward sloping profiles, depending upon the beam angle. Beam angle is adjusted between about 00 to about 300 from a normal to top surface 15 on gallium arsenide substrate 10. To create the outward sloping (or truncated pyramid shape) profile for each block, the entire structure is typically rotated during such etching step.
Reactive ion etching (RIE) also produces gallium arsenide blocks having a shaped profile. Generally, such etching method creates blocks having undercut sides or a reverse mesa profile.
Depending upon variables such as the etchant, pressure, equipment, and others, such etching method may create blocks having substantially consistent shapes and/or profiles.
After etching the MEE grown layer, trapezoidal shaped blocks are removed through a lift-off technique from gallium arsenide substrate 10 by preferential etching sacrificial layer 13 as illustrated in Fig. 3. Such lift-off technique occurs by, for example, a preferential wet etch of the aluminum arsenide sacrificial layer. In the gallium araenide example, such wet etching step ia typically performed by a chemical such as a hydrofluoric acid solution or the like. The etchant used substantially etches the sacrificial layer but does not aggressively attack gallium arsenide blocks and/or substrates.
After separatinq the gallium arsenide blocks from substrate 10, methods of diluting and decantinq the wet etchant solution remove the blocks from the solution. In the qallium arsenide example, the wet etchant is diluted and decanted usinq purified water, methanol, ethanol, or the like. Optionally, a rinsing step occurs after the dilutinq and decantinq step. The rinsinq step relies on solutions such as acetone, methanol, ethanol, or any other inert solution having low corrosive properties. Such solution also provides a medium (or fluid) for creatinq a mixture havinq blocks suspended therein or qenerally a slurry.
Instead of the lift-off technique illustrated in Fiq. 3, an alternative lift-off method creates intermediate structure 250 of Fiq. 4 from the qallium arsenide structure of Fig. 2. Such alternative lift-off method also promotes lift-off of the shaped blocksin applications where the devices are formed onto the backside of the blocks. As shown, the mlthod includes spreadinq a filler or wax layer 253 preferably high temperature wax overlyinq the top surface of exposed portions of sacrificial layer 13 and gaps 255 between each block 19. One such wax includes a product by the aas~e of TLCH WAX#made by TRANSENE Co., Inc. The method then includes inverting the gallium arsenide structure of Fig. 2 and attaching top surface 21 onto intermadiate substrate M. Such intermediate substrate is, for example, a silicon wafer or the like. However, prior to the attachinq step, intermadiate substrate surface 261 undergoes steps of etchinq off any native oxide preferably with a wet etchant such as hydrofluoric acid, and treating the cleaned surface with an adhesion promotor such as hexamethyldisilazane also called MtDS. In removing gallium arsenide substrate 10, backside 263 is lapped about 50 lim remains on substrate 10. The remaining thickness of substrate 10 is then etched up to aluminum arsenide layer 13. An etchant such as amsionium hydroxide and hydrogen peroxide (6:200' NH30H:A2O2) preferentially etches the gallium arsenide substrate up to aluminum arsenide layer 13. Accordingly, the aluminum arsenide layer acts aa an etch stop protecting qallium arsenide blocks 19.
Removinq aluminum arsenide layer 13 requires a step of wet etching using an etchant such as hydrofluaric acid. Such etchant typically removes aluminum arsenide layer 13 after a short dip in such solution. After the aluminum arsenide layer is completely removed, steps including masking, sputtering, and etchinq form metallized ring contacts 265 as illustrated in Fiq. S. Such metallized ring contacts were made by patterns formed from photoresist layer 267. The #Trade-mark ~WO95/17005 _ 217' 2' 6 PCT/US94/14152 metallization for such contacts include materials such as gold, aluminum, among others. Alternatively, other processing stepa such as etching, masking, implantation, diffusion, and the like may be performed on the blocks to create other profiles as well as active devicee thereon. A solution such as trichloroethane (TCA) dissolves the filler or wax disposed between each block 19 and photoresist layer 21, and lifts off the gallium arsenide blocks 19 from intermediate substrate 257. To decrease corrosion, the gallium arsenide blocks are transferred to an inert solution such as acetone, methanol, ethanol, or any other solution having low corrosive characteristics. Such inert solution and blocks are often called a mixture or generally a slurry.
The slurry comprises an inert solution (of fluid) and shaped blocks. Enough eolution exists in the slurry to allow the blocks to slide across the top surface of the substrate. Preferably, the amount of solution in the mixture is at least the same order as the amount of blocks. of course, the amount of solution necessary depends upon characteristics such as block size, block material, substrate size, substrate material, and solution. After preparation, the slurry is transferred or spread over top surface 53 of silicon substrate 50 as illustrated in Fig. 6. The details of the transferring technique are discussed below after a brief discussion in fabricating silicon substrate 50.
As shown in Fig. 6, siLicon substrate 50 comprises etched recessed regions 55. A variety of techniques including wet etching, plasma etching, reactive ion etching, ion milling, among others provide recessed regions 50, or generally trenches, receptors, or binding sites. Such techniques etch recessed regions 50 with a geometric profile which is complementary to block 19. In the silicon substrate, for example, each recessed region includes a trapezoidal profile or inverted truncated pyramid shape. The trapezoidal profile allows block 19 to self-align and fit closely into recessed region 50 via the improved transferring technique.
The transferring technique includes a step of evenly spreading or pouring the slurry over top surface 53. The transferring technique may be accomplished by pouring a vessel of slurry evenly over top surface 53. Alternatively, the slurry may also be transferred from a pipet, flask, beaker, or any other type of vessel and/or apparatus capable of evenly transferring the slurry over top surface 53. Generally, the slurry is poured over top surface 50 at a rate which allows substantial coverage of the top surface, but prevents blocks already disposed into the recessed regions from floating or popping out. Slurry flow is typically laminar but can be non-laminar, depending upon the particular application. In the gallium arsenide block example, the fluid flux over top surface 53 occurs at a velocity between about 0.01 mm/sec.
and about 100 mm/sec. Preferably, fluid flux occurs at about 1 mm/sec. At such flux rates, the blocks flow evenly with the fluid, tumble onto top surface 53, self-align, and settle into recessed 5 regions 55. Optionally, to prevent the blocks already disposed in the recessed regions from floating out, the transferring step may take place in a centrifuge or the like. A centrifuge, for example, places a force on the blocks already disposed in the recessed regions and thereby prevents such blocks from floating out with solution.
10 In a specific embodiment, the resulting structure 20 of the method described by Figs. 1-3 and 6 is illustrated in Fig. 7.
The assembled microatructure includes silicon substrate 10, gallium arsenide blocks 19, and recessed regions 55. The trapezoidal shape of the blocks and recessed regions allows a block to self-align and fit closely into a recessed region during the transferring step. An angle (A) formed between one side of the block and the corresponding side of the recessed region is between about substantially 0 to about 20 . Preferably, such angle is less than about 5 but greater than substantially 0 . such angle facilitates the self-alignment process of each block. The improved method allows for the fabrication of multiple blocks or microstructures onto a substrate by various shaped blocks and recessed region geometries and the fluid transferring stop.
In a modification to the preceding specific embodiment, the blocks 19 are attached into recessed regions 55 through eutectic layer 75 as represented in etructure 70 of Fig. S. Prior to the lift-off step, a metallized layer such as gold, silver, solder, or the like is formed onto surface 73. Alternatively, the layer attaching the block with each recessed region may be a synthetic adhesive or the like instead of a eutectic layer. Process steps comprising masking, etching, and sputtering typically form such metallized layer. Subsequent to the transferring step, heating structure 70 forms eutectic layer 75 between metallization layer 73 and silicon substrate 10. The eutectic layer provides both mechanical and electrical contact between substrate 10 and block 19.
The method of attaching the blocks onto the substrate provides an efficient, cost effective, and easy technique.
In an alternative specific embodiment, the portions of the improved method of Figs. 1, 2, 4, 5, and 6 provides the reeulting gallium arsenide light emitting diodes (LED) 200 as illustrated in Fig. 9. As shown, the gallium arsenide LED includes silicon substrate 203 and gallium arsenide block 205. Each gallium arsenide block includes at least metallized ring contacts 207, p-type gallium arsenide layer 209, n-type gallium arsenide layer 211, and eutectic layer 213. To illuminate the device, voltage is applied to ~WO 95117005 2 1 7 7 2 7 6 pCT/j7S94114152 metallized ring contact 207 or metallization layer. Photons (hv) are illuminated from a center region within each metallized ring contact 207 of gallium arsenide block 205 as shown.
In a further alternative specific embodiment, the improved structure forms gallium arsenide light emitting diodes (LED) 90 as depicted in Fig. 10. Like the previous embodiment, the gallium arsenide LED includes silicon substrate 93 and gallium arsenide block 95. Each gallium arsenide block also includes at least metallized surface 97, p-type gallium arsenide layer 101, n-type gallium arsenide layer 103, and eutectic layer 105, similar to the preceding embodiment. To illuminate the device, voltage is applied to metallization layer 97 by, for example, a probe. Photons (hv) are illuminated from an edge region instead of a center region of gallium arsenide block 95 as shown.
is Still in another specific embodiment, the improved structure forms gallium arsenide structure 120 having tapered aperture opening 123 as illustrated in Fig. 11 (not to scale). A
process step such as wet etching, ion milling, reactive ion etching, and others forms the tapered aperture opening 123. The gallium arsenide structure may be an LED, laser, or the like. Similar to the previous embodiment, gallium arsenide structure 120 includea substrate 125 and gallium arsenide block 127. Structure 120 also includes a top metallization layer 131 such as aluminum overlying gallium arsenide block 127 and an insulating layer 133. A ring contact layer 135 provides mechanical and electrical contact between substrate 125 and gallium arsenide block 127. Mechanical support and electrical contact for the gallium arsenide block comes from ledge 137. Also shown is a light emitting (or lasing) aperture 139 having a dimension between about 5 Nm and about 40 pm. To turn-on the device, voltage is applied to metallization layer 131. Photons (hv) illuminate from gallium arsenide block 127, through light emitting aperture 139, and through tapered aperture opening 123 as shown.
Fiber optic cable 141 receives the photons. Such fiber optic cable includes a tapered receiver end with a diameter between about 50 Nm and about 200 pm.
The improved method and resulting structure are in context to a trapezoidal shaped block made of gallium arsenide merely for illustrative purposes only. Alternatively, the improved method and structure can be in context to almost any block having shaped = 40 features. Shaped features allow such blocks to move over the surface of the substrate via fluid transport, align with a corresponding recessed region, and insert into such recessed region. Fig. 12 illustrates further examples of the shaped blocks. As shown, the blocks may, for example, include a rectangular shape 300, octagonal shape 303, or circular ahape 305. The rectangular shaped block wo 95117005 2 17 7 2 7( PCT/US94/14152 includes up to four orientations for insertion into a substrate having a corresponding recessed region. Alternatively, the octagonal shaped block includee up to eight orientations and the circular shaped block includes continuous orientations as long as the narrow 5 end inserts first into the recessed region. Such blocks may also comprise a material such as silicon, gallium arsenide, aluminum gallium arsenide, diamond, germanium, other group III-V and II-VI
compounds, multilayered structures, among others. Such multilayered structures may include metals, insulators such as silicon dioxide, silicon nitride and the like, and combinations thereof. Generally, the block can be made of almost any type of material capable of forming shaped features. Typically, such blocks are fabricated by methods including ion milling, reactive ion etching, and the like.
In facilitating alignment of each block onto a recessed region, an angle between a side of the block and the corresponding side of the recessed region for a disposed block is between about substantially 00 to about 20 . Preferably, such angle is less than about 50 but greater than substantially 00.
The shaped block assembles with a substrate such as a silicon wafer, plastic sheet, gallium arsenide wafer, glaes substrate, ceramic substrate, or the like. The substrate includes almost any type of material capable of forming ehaped recessed regions or generally binding sites or receptors thereon which complement the shaped blocks.
Examiples To prove the principle and demonatrate the operation of the method and structure, a gallium arsenide block in the form of a diode was assembled onto a silicon substrate and operated.
In a gallium arsenide example, a slurry including gallium arsenide blocks were transferred such that the blocks self-aligned into recessed regions located on a top surface of a silicon substrate. The steps for such method included forming the gallium arsenide blocks, transferring the blocks into a solution forming a slurry, and transporting the slurry evenly over a top surface of a silicon substrate having recessed regions. The shaped blocks generally tumble onto the top surface of the substrate, self-align and engage with a recessed region having a complementary shape.
In creating the silicon substrate, a solution of ethylenediamine pyrocatechol pyrazine (EDP) or potassium hydroxide (ftOH) produced recessed regions having a trapezoidal profile or inverted truncated pyramid shape. Each solution created trapezoidal shaped profiles having an outward slope of about 55 from an angle normal to the top surface of the substrate. Trapezoidal profiles occurred due to the selectivity (1:100) between the {111) plane and IDWO 95/17005 2 1 7 7 2 7 6 pCFIUS94/14152 the {100} or {110} plane. Specifically, the {111} plane etched slower than the (100} or {110} plane by a ratio of 1:100.
In the present example, an EDP solution etched recessed regions into a silicon substrate. EDP includes ethylenediamine ~ 5 (about 500 ml.), pyrocatechol (about 160 gms.), water (about 160 gms.), pyrazine (about 1 gm.). The EDP bath was also at a temperature of about 115 C. Prior to the etching step, a thermal oxide (S102) layer having a thickness of about 200 nm was first formed on a top surface of such substrate. Masking and etching such oxide layer formed rectangular shaped regions. Such regions were then etched vertically about 10 km forming square openings on the top surface about 23 pm in length. Sides protrude down symmetrically from each opening to a square base having a length of about 9Enn.
In fabricating trapezoidal shaped blocks, an epi-ready two inch n-type gallium arsenide wafer provided a substrate for the formation of the self-aligning blocks. Native oxide on the top surface of such block was first cleared off by a desorption process.
The desorption process included exposing the wafer to a temperature of about 700 C and elements including arsenic. After the-desorption step, a sacrificial layer comprising 1 pm of doped or undoped aluminum arsenide was grown on and in contact with the top surface.
A thickness of about 10.7 pm of silicon doped gallium arsenide was then grown through an MBE process overlying the aluminum arsenide layer. Silicon dopants were at a concentration of about 1018 atoms/cm3. The top surface of the MBE grown layer was then patterned with photoresist.
Patterning the top surface of the MBE grown layer included spreading a phatoresist layer having a thickness of about 1.6 km over the top surface of the MBE grown gallium arsenide layer.
The photoresiet used is a product made by Shipley under the name of AZ1400-31. Patterning steps also included at least exposing, developing, and baking the photoresist. Such baking step occurred at a temperature of about 120 C for about 1 hour to hard-bake the photoresist layer. The patterning steps formed a plurality of rectangles each having a dimension of about 35 {tm by 24 pm (exposed portions of the photoresiat) on the top surface.
After patterning, unexposed regions were etched forming trapezoidal shaped blocks attached to the aluminum arsenide sacrificial layer. Proper fit between the block and the recessed region requires each block to have substantially the same shape.
Accordingly, various concentrations and techniques of wet etching were tested in this particular example.
Generally, wet etching the unexposed regions produced results which depended upon the orientation of the mask edges. If the maek edges were parallel to the [110) direction, wet etching the unexposed regions created outward sloping profiles from the top surface of each block. Alternatively, wet etching unexposed regions where mask edges were parallel to the [110] direction created inward sloping (or reverse mesa) profiles.
Wet etching produced such different profiles (mesa and reverse mesa) because gallium arsenide includes two distinct sets of {111} planes. In a{111} A or {111} gallium plane, each gallium atom on the surface has three arsenide atoms bonded below. For a(111} B
or {ill} arsenic plane, each arsenide atom on the surface includes three gallium atoms bonded below. Each arsenide atom in the {111} B
layer includes a pair-of dangling electrons and is therefore exposed.
Such dangling electrons are not present in the structure of the {111}
A plane. Accordingly, {111} B planes tend to etch faster than {111}
A planes, thereby forming blocks having a reverse mesa shape which is generally incompatible with the recessed regions etched on the silicon substrate.
Mask edges parallel to the (110] plane produced more undercutting than the cases where mask edges were parallel to the [110] plane. In the present example, mask edges parallel to the [110] direction produced about 1.1 pm of horizontal etching per micron of vertical etching near the tops of the blocks. Regions near the base of the blocks produced etches of about 0.4 pm of horizontal etching per micron of vertical etching. Alternatively, mask edges parallel to the (110) plane produced etches of about 0.8 km of horizontal etching per micron of vertical etching for regiona near the top of the blocks, and 0.1 pm of horizontal etching per micron of vertical etch near the bottom of the blocks. The formation of a square region at the base required a longer mask in the [110]
direction.
In addition to mask alignment, etchant concentration also affected the shape of each gallium arsenide block. A solution of phosphoric acid, hydrogen peroxide, and water (H2PO3:H202:H20) provided a promising etchant for the MBE grown gallium arsenide layer in the present example. Such etchant created three distinct profiles, depending upon the amount of hydrogen peroxide and water added to phosphoric acid. Dilute concentrations of phosphoric acid (1:1:40 H2PO3:H202:H20) created a trapezoidal or mesa shaped profile having a 30 angle between the top surface of the block and a corresponding side. Etchant solutions which were less concentrated produced shallower trapezoidal or mesa shaped profiles at angles from about 10 to 20 . Such shallower profilea were probably a result of etching reactions being- transport limited in the {111} B planes.
Higher concentrations of phosphoric acid (1:1:20 H2PO3:H202:H20 and above) created inward sloping (or reverse mesa) profiles limited by the reaction of the {111} B planes. Preferably, is a phosphoric acid concentration (1:1:30 H2PO4:H202:H20) between the dilute and concentrated solutions provides better profiles for assembly with recessed regions etched on the silicon substrate. Such etchant produced blocks having angles of 55 parallel to the [110]
plane and 49 parallel to the [110] plane, and typically etched the MBE grown layer at a rate of about 0.133 um/minute (or about 133 nm/min). In producing the results described, etchant solution was typically replenished when depleted.
Increasing the ratio of phosphoric acid to hydrogen peroxide by 3:1 produced similar profiles to the experiments described, but generally caused rough surfaces on the sides. Such rough surfaces were desirable for the present application.
In a modification to this example, a similar wet etchant (1:1:30 H2PO3aH202:H20) facilitated the formation of aluminum gallium arsenide blocks from an aluminum gallium arsenide MBE grown layer.
Such etchant provided an inward sloping profile parallel to the (110) direction for an aluminum gallium arsenide (x=0.1, AlxGal_xAS) grown MBE layer. Vertical etch rates were about the same as the gallium arsenide MBE grown layer. However, the presence of aluminum arsenide increased etching of the {111} B plane into the reaction-rate limited regime. such etchant produced an inward sloping profile because etching x=0.1, A1xGa1_xAs was more reactive in the {111} B plane than gallium arsenide.
In addition to wet etching, ion milling was also used to create the gallium arsenide trapezoidal shaped blocks. Ion milling the MBE grown gallium arsenide layer provided outward sloping profiles ranging at angles of about 68 to 90 between the top surface and a corresponding side. To produce such angles, the ion beam angles ranged from about 0 to 25 in reference to a normal from the top surface of the MBE grown layer. steeper beam angles (closer to 90 ) generally created vertical or substantially vertical profiles. Ion milling also required the substrate to be rotated about a center axia during such processing step. Other processing variables included an argon gas etchant, pressure of about 50 millitorr, ion energy of about 1000 v, and an ion milling rate of 1 Nm every seven minutes. As the photoresist mask eroded laterally about 5 pm every 70 minutes during milling, sidewalls having angles at about 68 were produced. Selectivity between the gallium arsenide and photoresist was about 3:1. Ion milling produced substantially consistent gallium arsenide blocks and was therefore more effective than wet etching in this particular example.
A final bath having a concentration of 1:1:30 H2PO3:H2O2:H2O was used to clear off remaining oxides of either gallium arsenide and aluminum arsenide. Such oxides were typically formed when aluminum arsenide was exposed to etching baths or ion WO 95/17005 2 1 7 7 2 1 6 pCTIIJS94/14152 milling. Hydrofluoric acid may then be used to clear off the oxide layers (typically rough looking and brown in appearance). Generally, such oxide layers reduce the effectiveness of hydrofluoric acid (HF) etching on the sacrificial aluminum arsenide layer.
After clearing off any oxide layers, a HF solution preferentially etched the sacrificial layer of aluminum arsenide to lift-off the gallium arsenide blocks. In particular, a HF solution having a concentration of about 5:1 H20:HF was used to etch the sacrificial layer and lift off the blocks. Any blocks still remaining on the substrate possibly through surface tenaion can be mechanically removed from the substrate into a solution. Removed blocks include a base dimension of about 22 pm by 23 pm, compared to a designed dimension of 24 pm by 24 Nm.
After removing the blocks from the substrate, a teflon pipet was used to remove a substantial portion of the HF solution from the gallium arsenide blocks. Any remaining HF was rinsed off with water. Such rinsing step created a mixture including blocks and water. An inert solution such as acetone then replaced the water to decrease any oxide formation on the blocks. Once in the inert solution, the blocks may cluster together and either float to the surface or settle to the bottom of the solution. Such clusters, often visible to the naked eye, decreased the effectiveness of a subsequent transferring step, and were therefore separated by mechanically agitating t{:e solution with ultrasonic vibration.
The inert solution including gallium arsenide blocks were then transferred (or poured) evenly over the top surface of the silicon substrate. In particular, a pipet was used to transfer such solution over the top eurface of the substrate. The solution is transferred at a rate creating substantially a laminar flow. Such laminar flow allowed the blocks to tumble and/or slide onto the top surface of the substrate and then self-align into the recessed regions via the trapezoidal profile. Generally, the transfer rate should provide an even flow of solution including blocks over the substrate surface but should not free or remove any blocks already disposed into the recessed regions.
Blocks fabricated by ion milling produced higher yields than wet etched blocks. Ion milled blocks having substantially consistent profiles self aligned and inserted into more than 90% of the recessed regions located on the substrate surface before the solution substantially evaporated. As the solution evaporates, surface tension often pulled a portion of the blocks out of the recessed regions. About 30% to 70% of the recessed regions remained filled after evaporation. The decrease in yield can be addressed by using liquids having lower surface tension during evaporation or by super critical drying methods which substantially eliminates surface ~WO95117005 2 1 7 7 2 7 6 PC"r/QS94114152 tension. Alternatively, blocka may be bonded into the recessed regions prior to evaporation of the solution, thereby fixing the yield. Wet etched blocka having less consistent block profiles inserted correctly into about 1% to 5% of available recessed regions.
Accordingly, ion milled blocks provided higher yields relative to the blocks fabricated by wet etching.
Photographs shown in Fig. 13 illustrate gallium arsenide blocks disposed into recessed regions of the silicon substrate 150 according to the present example. A top portion 153 of each recessed region is square and measures about 23 gm at length. As shown, the photograph includes recessed regions 155, silicon substrate 157, and trapezoidal shaped block 159.
To further illustrate the operation of the present example, an illuminated diode 170 is shown in the photograph of Fig.
14. The photograph includes silicon substrate 173 and illuminated gallium arsenide LED 175. The gallium arsenide LED emitted infrared radiation while under electrical bias. Each gallium arsenide LED
which was grown on an MBE layer included an N+ gallium arsenide cap layer (about 100 nm thickness), an N+ Al0.1GaO.gAs transport layer (about 1 km thickness), a P- active region (about 1pm thickness), and a P+ buffer layer (about 1 pm thickness). The gallium arsenide LED also required a ring metallized contact 400 for applying voltage and an opening 403 for light output at a top portion of each block as illustrated in Fig. 15. , A current-voltage (I-V) curve 500 illustrated in Fig. 16 exhibits typical p-n junction characteristics for the gallium arsenide structure of Fig. 14.
Gallium arsenide/aluminum arsenide resonant-tunneling diodes (RTD's) were also integrated onto ailicon. RTD's grown on an MBE layer include gallium arsenide wells (depth at about 5.0 nm) between two aluminum arsenide barriers (depth at about 2.5 nm).
Current-voltage characteristics 600 for the RTD's integrated with silicon exhibited proper differential negative resistance (NDR) at VPEAK = 2.0 v. as illustrated in Fig. 17. At such voltage, peak-to-valley ratio was about 2.5. Oscillations (rf) observed after biasing the RTD's in the NDR region were limited to about 100 MHz. External capacitances and inductances of the biasing circuit caused such limitations in frequency.
The description above is in terms of assembling a gallium arsenide block onto a silicon substrate for illustrative purposes only. As shown, the invention may be applied to forming gallium arsenide diodes onto silicon substrates. Another commercial application includes gallium arsenide lasers assembled with silicon integrated circuits. The silicon chips can communicate with other chips with integrated optical detectors on extremely high bit-rate optical channels. Other applications may also include integration of R'O 95/17005 2 i 7 7 2 7 6 PCTIUS94/14152 18 microwave gallium arsenide devices onto silicon integrated circuits for the purpose of microwave electronics. Still a further application includes microstructures integral with a plastic sheet forming active liquid crystal displays (ALCD) and the like. In such application, the plastic sheet may be fabricated by a technique including stamping, injection molding, among others. The concept of the invention can be used with almost any type of microstructure which assembles onto a larger eubstrate.
Also described in general terms is the unique profiles for creating self-assembling devices. Such unique profiles, for example, are terms of a single block structure having a corresponding recessed region structure on a substrate for illustrative purposes only. The block structure may also include a variety of shapes such as a cylindrical shape, rectangular shape, square shape, hexagonal shape, pyramid shape, T-shape, kidney shape, and others. The block structure includes widths, lengths, and heights to promote self-assembly for a desired orientation. In addition, more than one type of structure may be present in the mixture (solution and blocks) as long as each structure includes a specific binding site on the substrate.
Although the foregoing invention has been described in some detail by way of illustration and example, for purposes of clarity of understanding, it will be obvious that certain changes and modifications may be practiced within the scope of the appended claims.
The above description is illustrative and not restrictive. Many variations of the invention will become apparent to those of skill in the art upon review of this disclosure. Merely by way of example the invention may used to assemble gallium arsenide devices onto a silicon substrate as well as other applications. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.
The assembled microatructure includes silicon substrate 10, gallium arsenide blocks 19, and recessed regions 55. The trapezoidal shape of the blocks and recessed regions allows a block to self-align and fit closely into a recessed region during the transferring step. An angle (A) formed between one side of the block and the corresponding side of the recessed region is between about substantially 0 to about 20 . Preferably, such angle is less than about 5 but greater than substantially 0 . such angle facilitates the self-alignment process of each block. The improved method allows for the fabrication of multiple blocks or microstructures onto a substrate by various shaped blocks and recessed region geometries and the fluid transferring stop.
In a modification to the preceding specific embodiment, the blocks 19 are attached into recessed regions 55 through eutectic layer 75 as represented in etructure 70 of Fig. S. Prior to the lift-off step, a metallized layer such as gold, silver, solder, or the like is formed onto surface 73. Alternatively, the layer attaching the block with each recessed region may be a synthetic adhesive or the like instead of a eutectic layer. Process steps comprising masking, etching, and sputtering typically form such metallized layer. Subsequent to the transferring step, heating structure 70 forms eutectic layer 75 between metallization layer 73 and silicon substrate 10. The eutectic layer provides both mechanical and electrical contact between substrate 10 and block 19.
The method of attaching the blocks onto the substrate provides an efficient, cost effective, and easy technique.
In an alternative specific embodiment, the portions of the improved method of Figs. 1, 2, 4, 5, and 6 provides the reeulting gallium arsenide light emitting diodes (LED) 200 as illustrated in Fig. 9. As shown, the gallium arsenide LED includes silicon substrate 203 and gallium arsenide block 205. Each gallium arsenide block includes at least metallized ring contacts 207, p-type gallium arsenide layer 209, n-type gallium arsenide layer 211, and eutectic layer 213. To illuminate the device, voltage is applied to ~WO 95117005 2 1 7 7 2 7 6 pCT/j7S94114152 metallized ring contact 207 or metallization layer. Photons (hv) are illuminated from a center region within each metallized ring contact 207 of gallium arsenide block 205 as shown.
In a further alternative specific embodiment, the improved structure forms gallium arsenide light emitting diodes (LED) 90 as depicted in Fig. 10. Like the previous embodiment, the gallium arsenide LED includes silicon substrate 93 and gallium arsenide block 95. Each gallium arsenide block also includes at least metallized surface 97, p-type gallium arsenide layer 101, n-type gallium arsenide layer 103, and eutectic layer 105, similar to the preceding embodiment. To illuminate the device, voltage is applied to metallization layer 97 by, for example, a probe. Photons (hv) are illuminated from an edge region instead of a center region of gallium arsenide block 95 as shown.
is Still in another specific embodiment, the improved structure forms gallium arsenide structure 120 having tapered aperture opening 123 as illustrated in Fig. 11 (not to scale). A
process step such as wet etching, ion milling, reactive ion etching, and others forms the tapered aperture opening 123. The gallium arsenide structure may be an LED, laser, or the like. Similar to the previous embodiment, gallium arsenide structure 120 includea substrate 125 and gallium arsenide block 127. Structure 120 also includes a top metallization layer 131 such as aluminum overlying gallium arsenide block 127 and an insulating layer 133. A ring contact layer 135 provides mechanical and electrical contact between substrate 125 and gallium arsenide block 127. Mechanical support and electrical contact for the gallium arsenide block comes from ledge 137. Also shown is a light emitting (or lasing) aperture 139 having a dimension between about 5 Nm and about 40 pm. To turn-on the device, voltage is applied to metallization layer 131. Photons (hv) illuminate from gallium arsenide block 127, through light emitting aperture 139, and through tapered aperture opening 123 as shown.
Fiber optic cable 141 receives the photons. Such fiber optic cable includes a tapered receiver end with a diameter between about 50 Nm and about 200 pm.
The improved method and resulting structure are in context to a trapezoidal shaped block made of gallium arsenide merely for illustrative purposes only. Alternatively, the improved method and structure can be in context to almost any block having shaped = 40 features. Shaped features allow such blocks to move over the surface of the substrate via fluid transport, align with a corresponding recessed region, and insert into such recessed region. Fig. 12 illustrates further examples of the shaped blocks. As shown, the blocks may, for example, include a rectangular shape 300, octagonal shape 303, or circular ahape 305. The rectangular shaped block wo 95117005 2 17 7 2 7( PCT/US94/14152 includes up to four orientations for insertion into a substrate having a corresponding recessed region. Alternatively, the octagonal shaped block includee up to eight orientations and the circular shaped block includes continuous orientations as long as the narrow 5 end inserts first into the recessed region. Such blocks may also comprise a material such as silicon, gallium arsenide, aluminum gallium arsenide, diamond, germanium, other group III-V and II-VI
compounds, multilayered structures, among others. Such multilayered structures may include metals, insulators such as silicon dioxide, silicon nitride and the like, and combinations thereof. Generally, the block can be made of almost any type of material capable of forming shaped features. Typically, such blocks are fabricated by methods including ion milling, reactive ion etching, and the like.
In facilitating alignment of each block onto a recessed region, an angle between a side of the block and the corresponding side of the recessed region for a disposed block is between about substantially 00 to about 20 . Preferably, such angle is less than about 50 but greater than substantially 00.
The shaped block assembles with a substrate such as a silicon wafer, plastic sheet, gallium arsenide wafer, glaes substrate, ceramic substrate, or the like. The substrate includes almost any type of material capable of forming ehaped recessed regions or generally binding sites or receptors thereon which complement the shaped blocks.
Examiples To prove the principle and demonatrate the operation of the method and structure, a gallium arsenide block in the form of a diode was assembled onto a silicon substrate and operated.
In a gallium arsenide example, a slurry including gallium arsenide blocks were transferred such that the blocks self-aligned into recessed regions located on a top surface of a silicon substrate. The steps for such method included forming the gallium arsenide blocks, transferring the blocks into a solution forming a slurry, and transporting the slurry evenly over a top surface of a silicon substrate having recessed regions. The shaped blocks generally tumble onto the top surface of the substrate, self-align and engage with a recessed region having a complementary shape.
In creating the silicon substrate, a solution of ethylenediamine pyrocatechol pyrazine (EDP) or potassium hydroxide (ftOH) produced recessed regions having a trapezoidal profile or inverted truncated pyramid shape. Each solution created trapezoidal shaped profiles having an outward slope of about 55 from an angle normal to the top surface of the substrate. Trapezoidal profiles occurred due to the selectivity (1:100) between the {111) plane and IDWO 95/17005 2 1 7 7 2 7 6 pCFIUS94/14152 the {100} or {110} plane. Specifically, the {111} plane etched slower than the (100} or {110} plane by a ratio of 1:100.
In the present example, an EDP solution etched recessed regions into a silicon substrate. EDP includes ethylenediamine ~ 5 (about 500 ml.), pyrocatechol (about 160 gms.), water (about 160 gms.), pyrazine (about 1 gm.). The EDP bath was also at a temperature of about 115 C. Prior to the etching step, a thermal oxide (S102) layer having a thickness of about 200 nm was first formed on a top surface of such substrate. Masking and etching such oxide layer formed rectangular shaped regions. Such regions were then etched vertically about 10 km forming square openings on the top surface about 23 pm in length. Sides protrude down symmetrically from each opening to a square base having a length of about 9Enn.
In fabricating trapezoidal shaped blocks, an epi-ready two inch n-type gallium arsenide wafer provided a substrate for the formation of the self-aligning blocks. Native oxide on the top surface of such block was first cleared off by a desorption process.
The desorption process included exposing the wafer to a temperature of about 700 C and elements including arsenic. After the-desorption step, a sacrificial layer comprising 1 pm of doped or undoped aluminum arsenide was grown on and in contact with the top surface.
A thickness of about 10.7 pm of silicon doped gallium arsenide was then grown through an MBE process overlying the aluminum arsenide layer. Silicon dopants were at a concentration of about 1018 atoms/cm3. The top surface of the MBE grown layer was then patterned with photoresist.
Patterning the top surface of the MBE grown layer included spreading a phatoresist layer having a thickness of about 1.6 km over the top surface of the MBE grown gallium arsenide layer.
The photoresiet used is a product made by Shipley under the name of AZ1400-31. Patterning steps also included at least exposing, developing, and baking the photoresist. Such baking step occurred at a temperature of about 120 C for about 1 hour to hard-bake the photoresist layer. The patterning steps formed a plurality of rectangles each having a dimension of about 35 {tm by 24 pm (exposed portions of the photoresiat) on the top surface.
After patterning, unexposed regions were etched forming trapezoidal shaped blocks attached to the aluminum arsenide sacrificial layer. Proper fit between the block and the recessed region requires each block to have substantially the same shape.
Accordingly, various concentrations and techniques of wet etching were tested in this particular example.
Generally, wet etching the unexposed regions produced results which depended upon the orientation of the mask edges. If the maek edges were parallel to the [110) direction, wet etching the unexposed regions created outward sloping profiles from the top surface of each block. Alternatively, wet etching unexposed regions where mask edges were parallel to the [110] direction created inward sloping (or reverse mesa) profiles.
Wet etching produced such different profiles (mesa and reverse mesa) because gallium arsenide includes two distinct sets of {111} planes. In a{111} A or {111} gallium plane, each gallium atom on the surface has three arsenide atoms bonded below. For a(111} B
or {ill} arsenic plane, each arsenide atom on the surface includes three gallium atoms bonded below. Each arsenide atom in the {111} B
layer includes a pair-of dangling electrons and is therefore exposed.
Such dangling electrons are not present in the structure of the {111}
A plane. Accordingly, {111} B planes tend to etch faster than {111}
A planes, thereby forming blocks having a reverse mesa shape which is generally incompatible with the recessed regions etched on the silicon substrate.
Mask edges parallel to the (110] plane produced more undercutting than the cases where mask edges were parallel to the [110] plane. In the present example, mask edges parallel to the [110] direction produced about 1.1 pm of horizontal etching per micron of vertical etching near the tops of the blocks. Regions near the base of the blocks produced etches of about 0.4 pm of horizontal etching per micron of vertical etching. Alternatively, mask edges parallel to the (110) plane produced etches of about 0.8 km of horizontal etching per micron of vertical etching for regiona near the top of the blocks, and 0.1 pm of horizontal etching per micron of vertical etch near the bottom of the blocks. The formation of a square region at the base required a longer mask in the [110]
direction.
In addition to mask alignment, etchant concentration also affected the shape of each gallium arsenide block. A solution of phosphoric acid, hydrogen peroxide, and water (H2PO3:H202:H20) provided a promising etchant for the MBE grown gallium arsenide layer in the present example. Such etchant created three distinct profiles, depending upon the amount of hydrogen peroxide and water added to phosphoric acid. Dilute concentrations of phosphoric acid (1:1:40 H2PO3:H202:H20) created a trapezoidal or mesa shaped profile having a 30 angle between the top surface of the block and a corresponding side. Etchant solutions which were less concentrated produced shallower trapezoidal or mesa shaped profiles at angles from about 10 to 20 . Such shallower profilea were probably a result of etching reactions being- transport limited in the {111} B planes.
Higher concentrations of phosphoric acid (1:1:20 H2PO3:H202:H20 and above) created inward sloping (or reverse mesa) profiles limited by the reaction of the {111} B planes. Preferably, is a phosphoric acid concentration (1:1:30 H2PO4:H202:H20) between the dilute and concentrated solutions provides better profiles for assembly with recessed regions etched on the silicon substrate. Such etchant produced blocks having angles of 55 parallel to the [110]
plane and 49 parallel to the [110] plane, and typically etched the MBE grown layer at a rate of about 0.133 um/minute (or about 133 nm/min). In producing the results described, etchant solution was typically replenished when depleted.
Increasing the ratio of phosphoric acid to hydrogen peroxide by 3:1 produced similar profiles to the experiments described, but generally caused rough surfaces on the sides. Such rough surfaces were desirable for the present application.
In a modification to this example, a similar wet etchant (1:1:30 H2PO3aH202:H20) facilitated the formation of aluminum gallium arsenide blocks from an aluminum gallium arsenide MBE grown layer.
Such etchant provided an inward sloping profile parallel to the (110) direction for an aluminum gallium arsenide (x=0.1, AlxGal_xAS) grown MBE layer. Vertical etch rates were about the same as the gallium arsenide MBE grown layer. However, the presence of aluminum arsenide increased etching of the {111} B plane into the reaction-rate limited regime. such etchant produced an inward sloping profile because etching x=0.1, A1xGa1_xAs was more reactive in the {111} B plane than gallium arsenide.
In addition to wet etching, ion milling was also used to create the gallium arsenide trapezoidal shaped blocks. Ion milling the MBE grown gallium arsenide layer provided outward sloping profiles ranging at angles of about 68 to 90 between the top surface and a corresponding side. To produce such angles, the ion beam angles ranged from about 0 to 25 in reference to a normal from the top surface of the MBE grown layer. steeper beam angles (closer to 90 ) generally created vertical or substantially vertical profiles. Ion milling also required the substrate to be rotated about a center axia during such processing step. Other processing variables included an argon gas etchant, pressure of about 50 millitorr, ion energy of about 1000 v, and an ion milling rate of 1 Nm every seven minutes. As the photoresist mask eroded laterally about 5 pm every 70 minutes during milling, sidewalls having angles at about 68 were produced. Selectivity between the gallium arsenide and photoresist was about 3:1. Ion milling produced substantially consistent gallium arsenide blocks and was therefore more effective than wet etching in this particular example.
A final bath having a concentration of 1:1:30 H2PO3:H2O2:H2O was used to clear off remaining oxides of either gallium arsenide and aluminum arsenide. Such oxides were typically formed when aluminum arsenide was exposed to etching baths or ion WO 95/17005 2 1 7 7 2 1 6 pCTIIJS94/14152 milling. Hydrofluoric acid may then be used to clear off the oxide layers (typically rough looking and brown in appearance). Generally, such oxide layers reduce the effectiveness of hydrofluoric acid (HF) etching on the sacrificial aluminum arsenide layer.
After clearing off any oxide layers, a HF solution preferentially etched the sacrificial layer of aluminum arsenide to lift-off the gallium arsenide blocks. In particular, a HF solution having a concentration of about 5:1 H20:HF was used to etch the sacrificial layer and lift off the blocks. Any blocks still remaining on the substrate possibly through surface tenaion can be mechanically removed from the substrate into a solution. Removed blocks include a base dimension of about 22 pm by 23 pm, compared to a designed dimension of 24 pm by 24 Nm.
After removing the blocks from the substrate, a teflon pipet was used to remove a substantial portion of the HF solution from the gallium arsenide blocks. Any remaining HF was rinsed off with water. Such rinsing step created a mixture including blocks and water. An inert solution such as acetone then replaced the water to decrease any oxide formation on the blocks. Once in the inert solution, the blocks may cluster together and either float to the surface or settle to the bottom of the solution. Such clusters, often visible to the naked eye, decreased the effectiveness of a subsequent transferring step, and were therefore separated by mechanically agitating t{:e solution with ultrasonic vibration.
The inert solution including gallium arsenide blocks were then transferred (or poured) evenly over the top surface of the silicon substrate. In particular, a pipet was used to transfer such solution over the top eurface of the substrate. The solution is transferred at a rate creating substantially a laminar flow. Such laminar flow allowed the blocks to tumble and/or slide onto the top surface of the substrate and then self-align into the recessed regions via the trapezoidal profile. Generally, the transfer rate should provide an even flow of solution including blocks over the substrate surface but should not free or remove any blocks already disposed into the recessed regions.
Blocks fabricated by ion milling produced higher yields than wet etched blocks. Ion milled blocks having substantially consistent profiles self aligned and inserted into more than 90% of the recessed regions located on the substrate surface before the solution substantially evaporated. As the solution evaporates, surface tension often pulled a portion of the blocks out of the recessed regions. About 30% to 70% of the recessed regions remained filled after evaporation. The decrease in yield can be addressed by using liquids having lower surface tension during evaporation or by super critical drying methods which substantially eliminates surface ~WO95117005 2 1 7 7 2 7 6 PC"r/QS94114152 tension. Alternatively, blocka may be bonded into the recessed regions prior to evaporation of the solution, thereby fixing the yield. Wet etched blocka having less consistent block profiles inserted correctly into about 1% to 5% of available recessed regions.
Accordingly, ion milled blocks provided higher yields relative to the blocks fabricated by wet etching.
Photographs shown in Fig. 13 illustrate gallium arsenide blocks disposed into recessed regions of the silicon substrate 150 according to the present example. A top portion 153 of each recessed region is square and measures about 23 gm at length. As shown, the photograph includes recessed regions 155, silicon substrate 157, and trapezoidal shaped block 159.
To further illustrate the operation of the present example, an illuminated diode 170 is shown in the photograph of Fig.
14. The photograph includes silicon substrate 173 and illuminated gallium arsenide LED 175. The gallium arsenide LED emitted infrared radiation while under electrical bias. Each gallium arsenide LED
which was grown on an MBE layer included an N+ gallium arsenide cap layer (about 100 nm thickness), an N+ Al0.1GaO.gAs transport layer (about 1 km thickness), a P- active region (about 1pm thickness), and a P+ buffer layer (about 1 pm thickness). The gallium arsenide LED also required a ring metallized contact 400 for applying voltage and an opening 403 for light output at a top portion of each block as illustrated in Fig. 15. , A current-voltage (I-V) curve 500 illustrated in Fig. 16 exhibits typical p-n junction characteristics for the gallium arsenide structure of Fig. 14.
Gallium arsenide/aluminum arsenide resonant-tunneling diodes (RTD's) were also integrated onto ailicon. RTD's grown on an MBE layer include gallium arsenide wells (depth at about 5.0 nm) between two aluminum arsenide barriers (depth at about 2.5 nm).
Current-voltage characteristics 600 for the RTD's integrated with silicon exhibited proper differential negative resistance (NDR) at VPEAK = 2.0 v. as illustrated in Fig. 17. At such voltage, peak-to-valley ratio was about 2.5. Oscillations (rf) observed after biasing the RTD's in the NDR region were limited to about 100 MHz. External capacitances and inductances of the biasing circuit caused such limitations in frequency.
The description above is in terms of assembling a gallium arsenide block onto a silicon substrate for illustrative purposes only. As shown, the invention may be applied to forming gallium arsenide diodes onto silicon substrates. Another commercial application includes gallium arsenide lasers assembled with silicon integrated circuits. The silicon chips can communicate with other chips with integrated optical detectors on extremely high bit-rate optical channels. Other applications may also include integration of R'O 95/17005 2 i 7 7 2 7 6 PCTIUS94/14152 18 microwave gallium arsenide devices onto silicon integrated circuits for the purpose of microwave electronics. Still a further application includes microstructures integral with a plastic sheet forming active liquid crystal displays (ALCD) and the like. In such application, the plastic sheet may be fabricated by a technique including stamping, injection molding, among others. The concept of the invention can be used with almost any type of microstructure which assembles onto a larger eubstrate.
Also described in general terms is the unique profiles for creating self-assembling devices. Such unique profiles, for example, are terms of a single block structure having a corresponding recessed region structure on a substrate for illustrative purposes only. The block structure may also include a variety of shapes such as a cylindrical shape, rectangular shape, square shape, hexagonal shape, pyramid shape, T-shape, kidney shape, and others. The block structure includes widths, lengths, and heights to promote self-assembly for a desired orientation. In addition, more than one type of structure may be present in the mixture (solution and blocks) as long as each structure includes a specific binding site on the substrate.
Although the foregoing invention has been described in some detail by way of illustration and example, for purposes of clarity of understanding, it will be obvious that certain changes and modifications may be practiced within the scope of the appended claims.
The above description is illustrative and not restrictive. Many variations of the invention will become apparent to those of skill in the art upon review of this disclosure. Merely by way of example the invention may used to assemble gallium arsenide devices onto a silicon substrate as well as other applications. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.
Claims (18)
1. A method of assembling a microstructure on a substrate, said substrate comprising a top surface with at least one recessed region thereon, comprising the steps of:
providing a plurality of shaped blocks, said shaped block comprising an integrated circuit thereon;
transferring said shaped blocks into a fluid to form a slurry; and dispensing said slurry over said substrate at a rate where at least one of said shaped blocks is disposed into a recessed region.
providing a plurality of shaped blocks, said shaped block comprising an integrated circuit thereon;
transferring said shaped blocks into a fluid to form a slurry; and dispensing said slurry over said substrate at a rate where at least one of said shaped blocks is disposed into a recessed region.
2. The method of claim 1 wherein said substrate is selected from a group consisting of a silicon wafer, plastic sheet, gallium arsenide wafer, glass substrate, and ceramic substrate.
3. The method of claim 1 wherein said rate is substantially a laminar flow and allows each of said shaped blocks to self-align into said recessed region.
4. The method of claim 1 wherein said shaped blocks include a trapezoidal profile.
5. The method of claim 4 wherein each of said recessed regions in said substrate is shaped substantially trapezoidal to complement each of said shaped blocks.
6. The method of claim 4 wherein said trapezoidal shaped blocks include a length at about 10 µm and greater.
7. The method of claim 1 wherein said fluid is an inert fluid selected from a group consisting of water, acetone, and alcohol.
8. The method of claim 1 wherein said slurry includes enough fluid to allow said shaped blocks to slide across said substrate.
9. The method of claim 4 wherein said trapezoidal blocks are fabricated by a method comprising the steps of:
providing a second substrate having a top surface;
growing a sacrificial layer overlying said top surface;
forming a block layer overlying said top surface;
masking and etching said block layer up to said sacrificial layer forming a plurality of trapezoidal shaped blocks on and in contact with said sacrificial layer;
preferential etching said sacrificial layer lifting off each of said trapezoidal shaped blocks; and transferring said trapezoidal shaped blocks into a solution to form said slurry.
providing a second substrate having a top surface;
growing a sacrificial layer overlying said top surface;
forming a block layer overlying said top surface;
masking and etching said block layer up to said sacrificial layer forming a plurality of trapezoidal shaped blocks on and in contact with said sacrificial layer;
preferential etching said sacrificial layer lifting off each of said trapezoidal shaped blocks; and transferring said trapezoidal shaped blocks into a solution to form said slurry.
10. The method of claim 9 further comprising a step of rinsing said blocks subsequent to said preferential etching step.
11. The method of claim 9 wherein said preferential etching step is a step of wet etching.
12. The method of claim 9 wherein said wet etching step includes a hydrogen fluoride etchant.
13. The method of claim 9 wherein said second substrate is selected from the group consisting of gallium arsenide, gallium aluminum arsenide, silicon, and diamond.
14. The method of claim 4 wherein said trapezoidal shaped block further comprising a truncated pyramid shape including a top surface with four sides protruding therefrom to a base.
15. The method of claim 14 wherein said base has a length between about 10 µm and about 50 µm, and a width between 10 µm and about 50 µm, and each of said four sides has a height between about 5 µm and about 15 µm.
16. A microstructure integral with a substrate comprising:
a substrate having a plurality of recessed regions thereon; and a plurality of shaped blocks integral with said recessed regions, said shaped blocks comprising an integrated circuit thereon;
wherein said shaped blocks each include a trapezoidal profile comprising a truncated pyramid shape including a top surface with four sides protruding therefrom to a base, said base having a length between about 10 µm and about 50 µm, and a width between 10 µm and about 50 µm, and each of said four sides having a height between about 5 µm and about 15 µm, and each of said recessed regions in said substrate is shaped substantially trapezoidal to complement each of said shaped blocks.
a substrate having a plurality of recessed regions thereon; and a plurality of shaped blocks integral with said recessed regions, said shaped blocks comprising an integrated circuit thereon;
wherein said shaped blocks each include a trapezoidal profile comprising a truncated pyramid shape including a top surface with four sides protruding therefrom to a base, said base having a length between about 10 µm and about 50 µm, and a width between 10 µm and about 50 µm, and each of said four sides having a height between about 5 µm and about 15 µm, and each of said recessed regions in said substrate is shaped substantially trapezoidal to complement each of said shaped blocks.
17. A method of fabricating shaped blocks comprising an integrated circuit, comprising the steps of:
providing a substrate having a top surface and a backside;
growing a sacrificial layer overlying said top surface;
forming a block layer overlying said top surface;
masking and etching said block layer up to said sacrificial layer forming a plurality of shaped blocks on and in contact with said sacrificial layer;
depositing a filler layer onto a top surface of said shaped blocks and exposed portions of said sacrificial layer;
attaching a top surface of an intermediate substrate onto said top surface of said shaped blocks;
removing said substrate from said shaped blocks;
processing portions of said shaped blocks, said processing step forming integrated circuits on said blocks; and removing said filler layer and said shaped blocks from said intermediate substrate.
providing a substrate having a top surface and a backside;
growing a sacrificial layer overlying said top surface;
forming a block layer overlying said top surface;
masking and etching said block layer up to said sacrificial layer forming a plurality of shaped blocks on and in contact with said sacrificial layer;
depositing a filler layer onto a top surface of said shaped blocks and exposed portions of said sacrificial layer;
attaching a top surface of an intermediate substrate onto said top surface of said shaped blocks;
removing said substrate from said shaped blocks;
processing portions of said shaped blocks, said processing step forming integrated circuits on said blocks; and removing said filler layer and said shaped blocks from said intermediate substrate.
18. The method of claim 17 further comprising a step of preferential etching said sacrificial layer lifting off each of said shaped blocks.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/169,298 | 1993-12-17 | ||
US08/169,298 US5545291A (en) | 1993-12-17 | 1993-12-17 | Method for fabricating self-assembling microstructures |
PCT/US1994/014152 WO1995017005A1 (en) | 1993-12-17 | 1994-12-07 | Method for fabricating self-assembling microstructures |
Publications (2)
Publication Number | Publication Date |
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CA2177276A1 CA2177276A1 (en) | 1995-06-22 |
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---|---|---|---|
CA002177276A Expired - Fee Related CA2177276C (en) | 1993-12-17 | 1994-12-07 | Method for fabricating self-assembling microstructures |
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---|---|
US (2) | US5545291A (en) |
EP (3) | EP0734586B1 (en) |
JP (3) | JP3535166B2 (en) |
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AU (1) | AU681928B2 (en) |
CA (1) | CA2177276C (en) |
DE (1) | DE69433361T2 (en) |
WO (1) | WO1995017005A1 (en) |
Families Citing this family (378)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6569382B1 (en) | 1991-11-07 | 2003-05-27 | Nanogen, Inc. | Methods apparatus for the electronic, homogeneous assembly and fabrication of devices |
US6864570B2 (en) * | 1993-12-17 | 2005-03-08 | The Regents Of The University Of California | Method and apparatus for fabricating self-assembling microstructures |
US5824186A (en) * | 1993-12-17 | 1998-10-20 | The Regents Of The University Of California | Method and apparatus for fabricating self-assembling microstructures |
US5904545A (en) * | 1993-12-17 | 1999-05-18 | The Regents Of The University Of California | Apparatus for fabricating self-assembling microstructures |
US5674785A (en) * | 1995-11-27 | 1997-10-07 | Micron Technology, Inc. | Method of producing a single piece package for semiconductor die |
US6861290B1 (en) | 1995-12-19 | 2005-03-01 | Micron Technology, Inc. | Flip-chip adaptor package for bare die |
JP3097557B2 (en) * | 1996-05-20 | 2000-10-10 | 日本電気株式会社 | Method for manufacturing semiconductor device |
GB9616540D0 (en) | 1996-08-06 | 1996-09-25 | Cavendish Kinetics Ltd | Integrated circuit device manufacture |
US6507989B1 (en) | 1997-03-13 | 2003-01-21 | President And Fellows Of Harvard College | Self-assembly of mesoscale objects |
US6445489B1 (en) | 1998-03-18 | 2002-09-03 | E Ink Corporation | Electrophoretic displays and systems for addressing such displays |
US6391005B1 (en) | 1998-03-30 | 2002-05-21 | Agilent Technologies, Inc. | Apparatus and method for penetration with shaft having a sensor for sensing penetration depth |
USRE43112E1 (en) | 1998-05-04 | 2012-01-17 | Round Rock Research, Llc | Stackable ball grid array package |
JP4651193B2 (en) | 1998-05-12 | 2011-03-16 | イー インク コーポレイション | Microencapsulated electrophoretic electrostatically addressed media for drawing device applications |
US6066513A (en) * | 1998-10-02 | 2000-05-23 | International Business Machines Corporation | Process for precise multichip integration and product thereof |
DE19856331B4 (en) * | 1998-12-07 | 2009-01-02 | Robert Bosch Gmbh | Method for encasing electronic components |
US6312304B1 (en) | 1998-12-15 | 2001-11-06 | E Ink Corporation | Assembly of microencapsulated electronic displays |
US6683663B1 (en) * | 1999-02-05 | 2004-01-27 | Alien Technology Corporation | Web fabrication of devices |
US6850312B2 (en) * | 1999-03-16 | 2005-02-01 | Alien Technology Corporation | Apparatuses and methods for flexible displays |
JP2002536695A (en) * | 1999-02-05 | 2002-10-29 | エイリアン・テクノロジイ・コーポレーション | Apparatus and method for forming an assembly |
US6291896B1 (en) | 1999-02-16 | 2001-09-18 | Alien Technology Corporation | Functionally symmetric integrated circuit die |
US6380729B1 (en) | 1999-02-16 | 2002-04-30 | Alien Technology Corporation | Testing integrated circuit dice |
US6606079B1 (en) | 1999-02-16 | 2003-08-12 | Alien Technology Corporation | Pixel integrated circuit |
US6468638B2 (en) * | 1999-03-16 | 2002-10-22 | Alien Technology Corporation | Web process interconnect in electronic assemblies |
US6316278B1 (en) * | 1999-03-16 | 2001-11-13 | Alien Technology Corporation | Methods for fabricating a multiple modular assembly |
US6531997B1 (en) | 1999-04-30 | 2003-03-11 | E Ink Corporation | Methods for addressing electrophoretic displays |
US6504524B1 (en) | 2000-03-08 | 2003-01-07 | E Ink Corporation | Addressing methods for displays having zero time-average field |
US7030412B1 (en) | 1999-05-05 | 2006-04-18 | E Ink Corporation | Minimally-patterned semiconductor devices for display applications |
AU6365900A (en) | 1999-07-21 | 2001-02-13 | E-Ink Corporation | Use of a storage capacitor to enhance the performance of an active matrix drivenelectronic display |
US6420266B1 (en) | 1999-11-02 | 2002-07-16 | Alien Technology Corporation | Methods for creating elements of predetermined shape and apparatuses using these elements |
US6623579B1 (en) * | 1999-11-02 | 2003-09-23 | Alien Technology Corporation | Methods and apparatus for fluidic self assembly |
US6479395B1 (en) * | 1999-11-02 | 2002-11-12 | Alien Technology Corporation | Methods for forming openings in a substrate and apparatuses with these openings and methods for creating assemblies with openings |
US6527964B1 (en) * | 1999-11-02 | 2003-03-04 | Alien Technology Corporation | Methods and apparatuses for improved flow in performing fluidic self assembly |
KR100726134B1 (en) * | 2000-02-21 | 2007-06-12 | 엘지.필립스 엘시디 주식회사 | Array substrate for a liquid crystal display device and Method for fabricating the same |
KR100658977B1 (en) * | 2000-02-21 | 2006-12-18 | 엘지.필립스 엘시디 주식회사 | LCD and method for fabricating the same |
KR100732648B1 (en) * | 2000-02-22 | 2007-06-28 | 도레이엔지니어링가부시키가이샤 | Noncontact id card or the like and method of manufacturing the same |
JP2001257218A (en) | 2000-03-10 | 2001-09-21 | Sony Corp | Method for mounting fine chip |
EP1280101B1 (en) * | 2000-04-04 | 2005-05-18 | Toray Engineering Co., Ltd. | Method of manufacturing cof package |
JP2003531487A (en) | 2000-04-18 | 2003-10-21 | イー−インク コーポレイション | Process for manufacturing thin film transistor |
US7893435B2 (en) | 2000-04-18 | 2011-02-22 | E Ink Corporation | Flexible electronic circuits and displays including a backplane comprising a patterned metal foil having a plurality of apertures extending therethrough |
EP1290827A2 (en) * | 2000-06-02 | 2003-03-12 | Teradyne, Inc. | Method for measuring internet router traffic |
US6687987B2 (en) | 2000-06-06 | 2004-02-10 | The Penn State Research Foundation | Electro-fluidic assembly process for integration of electronic devices onto a substrate |
US6908295B2 (en) * | 2000-06-16 | 2005-06-21 | Avery Dennison Corporation | Process and apparatus for embossing precise microstructures and embossing tool for making same |
US6723576B2 (en) * | 2000-06-30 | 2004-04-20 | Seiko Epson Corporation | Disposing method for semiconductor elements |
JP4120184B2 (en) | 2000-06-30 | 2008-07-16 | セイコーエプソン株式会社 | Mounting microstructure and optical transmission device |
JP3829594B2 (en) | 2000-06-30 | 2006-10-04 | セイコーエプソン株式会社 | Device mounting method and optical transmission device |
JP4239439B2 (en) | 2000-07-06 | 2009-03-18 | セイコーエプソン株式会社 | OPTICAL DEVICE, ITS MANUFACTURING METHOD, AND OPTICAL TRANSMISSION DEVICE |
JP3840926B2 (en) * | 2000-07-07 | 2006-11-01 | セイコーエプソン株式会社 | Organic EL display, method for manufacturing the same, and electronic device |
US6583580B2 (en) | 2000-07-07 | 2003-06-24 | Seiko Epson Corporation | EL element driving circuit and method, and electronic apparatus |
JP3815269B2 (en) | 2000-07-07 | 2006-08-30 | セイコーエプソン株式会社 | Organic EL display and manufacturing method thereof, perforated substrate, electro-optical device and manufacturing method thereof, and electronic apparatus |
US6605902B2 (en) | 2000-07-07 | 2003-08-12 | Seiko Epson Corporation | Display and electronic device |
JP3915868B2 (en) | 2000-07-07 | 2007-05-16 | セイコーエプソン株式会社 | Ferroelectric memory device and manufacturing method thereof |
US6683333B2 (en) | 2000-07-14 | 2004-01-27 | E Ink Corporation | Fabrication of electronic circuit elements using unpatterned semiconductor layers |
JP3963068B2 (en) * | 2000-07-19 | 2007-08-22 | 豊田合成株式会社 | Method for producing group III nitride compound semiconductor device |
EP1323190A2 (en) * | 2000-07-20 | 2003-07-02 | President And Fellows of Harvard College | Self-assembled electrical networks |
US6780696B1 (en) | 2000-09-12 | 2004-08-24 | Alien Technology Corporation | Method and apparatus for self-assembly of functional blocks on a substrate facilitated by electrode pairs |
US6980184B1 (en) | 2000-09-27 | 2005-12-27 | Alien Technology Corporation | Display devices and integrated circuits |
US6811714B1 (en) * | 2000-10-06 | 2004-11-02 | Freescale Semiconductor, Inc. | Micromachined component and method of manufacture |
JP4491948B2 (en) | 2000-10-06 | 2010-06-30 | ソニー株式会社 | Device mounting method and image display device manufacturing method |
DE10053334B4 (en) * | 2000-10-27 | 2018-08-02 | Robert Bosch Gmbh | Method and device for controlling an actuating element in a vehicle |
WO2002043032A2 (en) * | 2000-11-21 | 2002-05-30 | Avery Dennison Corporation | Display device and methods of manufacture and control |
US7199527B2 (en) * | 2000-11-21 | 2007-04-03 | Alien Technology Corporation | Display device and methods of manufacturing and control |
US8641644B2 (en) | 2000-11-21 | 2014-02-04 | Sanofi-Aventis Deutschland Gmbh | Blood testing apparatus having a rotatable cartridge with multiple lancing elements and testing means |
US20020149107A1 (en) * | 2001-02-02 | 2002-10-17 | Avery Dennison Corporation | Method of making a flexible substrate containing self-assembling microstructures |
US6794221B2 (en) * | 2000-11-29 | 2004-09-21 | Hrl Laboratories, Llc | Method of placing elements into receptors in a substrate |
US6291266B1 (en) * | 2000-11-29 | 2001-09-18 | Hrl Laboratories, Llc | Method for fabricating large area flexible electronics |
US6611237B2 (en) | 2000-11-30 | 2003-08-26 | The Regents Of The University Of California | Fluidic self-assembly of active antenna |
US6951596B2 (en) | 2002-01-18 | 2005-10-04 | Avery Dennison Corporation | RFID label technique |
BR0208128A (en) | 2001-03-19 | 2004-03-02 | Dow Global Technologies Inc | Addressable Electrochromic Array Display Device |
JP2002359358A (en) | 2001-03-26 | 2002-12-13 | Seiko Epson Corp | Ferroelectric substance storage device and electronic apparatus |
US6417025B1 (en) * | 2001-04-02 | 2002-07-09 | Alien Technology Corporation | Integrated circuit packages assembled utilizing fluidic self-assembly |
US6864435B2 (en) * | 2001-04-25 | 2005-03-08 | Alien Technology Corporation | Electrical contacts for flexible displays |
GB0112395D0 (en) * | 2001-05-22 | 2001-07-11 | Koninkl Philips Electronics Nv | Display devices and driving method therefor |
US6606247B2 (en) * | 2001-05-31 | 2003-08-12 | Alien Technology Corporation | Multi-feature-size electronic structures |
US6988667B2 (en) * | 2001-05-31 | 2006-01-24 | Alien Technology Corporation | Methods and apparatuses to identify devices |
JP3812368B2 (en) * | 2001-06-06 | 2006-08-23 | 豊田合成株式会社 | Group III nitride compound semiconductor device and method for manufacturing the same |
US6686642B2 (en) * | 2001-06-11 | 2004-02-03 | Hewlett-Packard Development Company, L.P. | Multi-level integrated circuit for wide-gap substrate bonding |
US9226699B2 (en) | 2002-04-19 | 2016-01-05 | Sanofi-Aventis Deutschland Gmbh | Body fluid sampling module with a continuous compression tissue interface surface |
WO2002100254A2 (en) | 2001-06-12 | 2002-12-19 | Pelikan Technologies, Inc. | Method and apparatus for lancet launching device integrated onto a blood-sampling cartridge |
US9795747B2 (en) | 2010-06-02 | 2017-10-24 | Sanofi-Aventis Deutschland Gmbh | Methods and apparatus for lancet actuation |
DE60238119D1 (en) | 2001-06-12 | 2010-12-09 | Pelikan Technologies Inc | ELECTRIC ACTUATOR ELEMENT FOR A LANZETTE |
US7025774B2 (en) | 2001-06-12 | 2006-04-11 | Pelikan Technologies, Inc. | Tissue penetration device |
ES2336081T3 (en) | 2001-06-12 | 2010-04-08 | Pelikan Technologies Inc. | SELF-OPTIMIZATION PUNCTURE DEVICE WITH MEANS OF ADAPTATION TO TEMPORARY VARIATIONS IN CUTANEOUS PROPERTIES. |
US9427532B2 (en) | 2001-06-12 | 2016-08-30 | Sanofi-Aventis Deutschland Gmbh | Tissue penetration device |
US8337419B2 (en) | 2002-04-19 | 2012-12-25 | Sanofi-Aventis Deutschland Gmbh | Tissue penetration device |
US7981056B2 (en) | 2002-04-19 | 2011-07-19 | Pelikan Technologies, Inc. | Methods and apparatus for lancet actuation |
JP2003005212A (en) * | 2001-06-20 | 2003-01-08 | Seiko Instruments Inc | Liquid crystal display device having single crystal silicon transistor element, and its manufacturing method |
JP3696132B2 (en) | 2001-07-10 | 2005-09-14 | 株式会社東芝 | Active matrix substrate and manufacturing method thereof |
US6657289B1 (en) * | 2001-07-13 | 2003-12-02 | Alien Technology Corporation | Apparatus relating to block configurations and fluidic self-assembly processes |
US6590346B1 (en) * | 2001-07-16 | 2003-07-08 | Alien Technology Corporation | Double-metal background driven displays |
US6967640B2 (en) | 2001-07-27 | 2005-11-22 | E Ink Corporation | Microencapsulated electrophoretic display with integrated driver |
US6731353B1 (en) | 2001-08-17 | 2004-05-04 | Alien Technology Corporation | Method and apparatus for transferring blocks |
US7218527B1 (en) * | 2001-08-17 | 2007-05-15 | Alien Technology Corporation | Apparatuses and methods for forming smart labels |
US6863219B1 (en) * | 2001-08-17 | 2005-03-08 | Alien Technology Corporation | Apparatuses and methods for forming electronic assemblies |
US20030057544A1 (en) * | 2001-09-13 | 2003-03-27 | Nathan Richard J. | Integrated assembly protocol |
US20030059976A1 (en) * | 2001-09-24 | 2003-03-27 | Nathan Richard J. | Integrated package and methods for making same |
US6528351B1 (en) | 2001-09-24 | 2003-03-04 | Jigsaw Tek, Inc. | Integrated package and methods for making same |
US7018575B2 (en) * | 2001-09-28 | 2006-03-28 | Hrl Laboratories, Llc | Method for assembly of complementary-shaped receptacle site and device microstructures |
WO2003030254A2 (en) * | 2001-09-28 | 2003-04-10 | Hrl Laboratories, Llc | Process for assembling systems and structure thus obtained |
US7253091B2 (en) * | 2001-09-28 | 2007-08-07 | Hrl Laboratories, Llc | Process for assembling three-dimensional systems on a chip and structure thus obtained |
US6974604B2 (en) * | 2001-09-28 | 2005-12-13 | Hrl Laboratories, Llc | Method of self-latching for adhesion during self-assembly of electronic or optical components |
US7351660B2 (en) * | 2001-09-28 | 2008-04-01 | Hrl Laboratories, Llc | Process for producing high performance interconnects |
US7193504B2 (en) | 2001-10-09 | 2007-03-20 | Alien Technology Corporation | Methods and apparatuses for identification |
JP2003141761A (en) * | 2001-10-31 | 2003-05-16 | Sanyo Electric Co Ltd | Optical disk device and recording/reproducing method |
AU2002354445A1 (en) * | 2001-12-07 | 2003-06-17 | Sharp Kabushiki Kaisha | Display apparatus using bidirectional two-terminal element and display apparatus manufacturing method |
JP3844061B2 (en) * | 2002-01-16 | 2006-11-08 | ソニー株式会社 | Electronic component placement method and apparatus |
JP4082031B2 (en) * | 2002-01-17 | 2008-04-30 | ソニー株式会社 | Element arrangement method and display device |
AU2003235633A1 (en) * | 2002-01-18 | 2003-07-30 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Bonding device and method for production thereof |
US7214569B2 (en) * | 2002-01-23 | 2007-05-08 | Alien Technology Corporation | Apparatus incorporating small-feature-size and large-feature-size components and method for making same |
CN1606796A (en) * | 2002-01-23 | 2005-04-13 | 艾伦技术公司 | Apparatus incorporating small-feature-size and large-feature-size components and method for making same |
US6833277B2 (en) * | 2002-01-24 | 2004-12-21 | Massachusetts Institute Of Technology | Method and system for field assisted statistical assembly of wafers |
US6900851B2 (en) | 2002-02-08 | 2005-05-31 | E Ink Corporation | Electro-optic displays and optical systems for addressing such displays |
US20030153119A1 (en) * | 2002-02-14 | 2003-08-14 | Nathan Richard J. | Integrated circuit package and method for fabrication |
US7080444B1 (en) * | 2002-02-28 | 2006-07-25 | Alien Technology Corporation | Apparatus for forming an electronic assembly |
US6744549B2 (en) | 2002-03-19 | 2004-06-01 | Dow Global Technologies Inc. | Electrochromic display device |
US7976476B2 (en) | 2002-04-19 | 2011-07-12 | Pelikan Technologies, Inc. | Device and method for variable speed lancet |
US9314194B2 (en) | 2002-04-19 | 2016-04-19 | Sanofi-Aventis Deutschland Gmbh | Tissue penetration device |
US7909778B2 (en) | 2002-04-19 | 2011-03-22 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US8360992B2 (en) | 2002-04-19 | 2013-01-29 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for penetrating tissue |
US7901362B2 (en) | 2002-04-19 | 2011-03-08 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US7892183B2 (en) | 2002-04-19 | 2011-02-22 | Pelikan Technologies, Inc. | Method and apparatus for body fluid sampling and analyte sensing |
US7331931B2 (en) | 2002-04-19 | 2008-02-19 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US7175642B2 (en) | 2002-04-19 | 2007-02-13 | Pelikan Technologies, Inc. | Methods and apparatus for lancet actuation |
US8372016B2 (en) | 2002-04-19 | 2013-02-12 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for body fluid sampling and analyte sensing |
US7708701B2 (en) | 2002-04-19 | 2010-05-04 | Pelikan Technologies, Inc. | Method and apparatus for a multi-use body fluid sampling device |
US7297122B2 (en) | 2002-04-19 | 2007-11-20 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US7229458B2 (en) | 2002-04-19 | 2007-06-12 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US8784335B2 (en) | 2002-04-19 | 2014-07-22 | Sanofi-Aventis Deutschland Gmbh | Body fluid sampling device with a capacitive sensor |
US8267870B2 (en) | 2002-04-19 | 2012-09-18 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for body fluid sampling with hybrid actuation |
US7232451B2 (en) | 2002-04-19 | 2007-06-19 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US9248267B2 (en) | 2002-04-19 | 2016-02-02 | Sanofi-Aventis Deustchland Gmbh | Tissue penetration device |
US7491178B2 (en) | 2002-04-19 | 2009-02-17 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US8702624B2 (en) | 2006-09-29 | 2014-04-22 | Sanofi-Aventis Deutschland Gmbh | Analyte measurement device with a single shot actuator |
US9795334B2 (en) | 2002-04-19 | 2017-10-24 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for penetrating tissue |
US8221334B2 (en) | 2002-04-19 | 2012-07-17 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for penetrating tissue |
US7674232B2 (en) | 2002-04-19 | 2010-03-09 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US7547287B2 (en) | 2002-04-19 | 2009-06-16 | Pelikan Technologies, Inc. | Method and apparatus for penetrating tissue |
US8579831B2 (en) | 2002-04-19 | 2013-11-12 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for penetrating tissue |
US6927382B2 (en) * | 2002-05-22 | 2005-08-09 | Agilent Technologies | Optical excitation/detection device and method for making same using fluidic self-assembly techniques |
US6903458B1 (en) | 2002-06-20 | 2005-06-07 | Richard J. Nathan | Embedded carrier for an integrated circuit chip |
US20060014322A1 (en) * | 2002-07-11 | 2006-01-19 | Craig Gordon S | Methods and apparatuses relating to block configurations and fluidic self-assembly processes |
US6946322B2 (en) * | 2002-07-25 | 2005-09-20 | Hrl Laboratories, Llc | Large area printing method for integrating device and circuit components |
US6867983B2 (en) * | 2002-08-07 | 2005-03-15 | Avery Dennison Corporation | Radio frequency identification device and method |
JP4057861B2 (en) * | 2002-08-20 | 2008-03-05 | 松下電器産業株式会社 | Semiconductor laser device and manufacturing method thereof |
DE10238601A1 (en) * | 2002-08-22 | 2004-03-11 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Wafer for handling substrates in the semiconductor industry comprises a first surface on which an adhesive layer is applied to keep a substrate mechanically stable for subsequent processing, a second surface, and a feed line for solvent |
JP2004119620A (en) * | 2002-09-25 | 2004-04-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing same |
JP4197420B2 (en) | 2002-09-27 | 2008-12-17 | パナソニック株式会社 | Manufacturing method of semiconductor device |
US6710436B1 (en) * | 2002-12-12 | 2004-03-23 | Sun Microsystems, Inc. | Method and apparatus for electrostatically aligning integrated circuits |
US20060105549A1 (en) * | 2002-12-18 | 2006-05-18 | Duineveld Paulus C | Manipulation of micrometer-sized electronic objects with liquid droplets |
US8574895B2 (en) | 2002-12-30 | 2013-11-05 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus using optical techniques to measure analyte levels |
US7224280B2 (en) * | 2002-12-31 | 2007-05-29 | Avery Dennison Corporation | RFID device and method of forming |
US6940408B2 (en) * | 2002-12-31 | 2005-09-06 | Avery Dennison Corporation | RFID device and method of forming |
US7225992B2 (en) * | 2003-02-13 | 2007-06-05 | Avery Dennison Corporation | RFID device tester and method |
JP2004272014A (en) * | 2003-03-10 | 2004-09-30 | Seiko Epson Corp | Manufacturing method of optical communication module, optical communication module, and electronic apparatus |
US7253735B2 (en) | 2003-03-24 | 2007-08-07 | Alien Technology Corporation | RFID tags and processes for producing RFID tags |
US7059518B2 (en) * | 2003-04-03 | 2006-06-13 | Avery Dennison Corporation | RFID device detection system and method |
US7501984B2 (en) * | 2003-11-04 | 2009-03-10 | Avery Dennison Corporation | RFID tag using a surface insensitive antenna structure |
US7652636B2 (en) * | 2003-04-10 | 2010-01-26 | Avery Dennison Corporation | RFID devices having self-compensating antennas and conductive shields |
US20040200061A1 (en) * | 2003-04-11 | 2004-10-14 | Coleman James P. | Conductive pattern and method of making |
US7930815B2 (en) * | 2003-04-11 | 2011-04-26 | Avery Dennison Corporation | Conductive pattern and method of making |
JP3927919B2 (en) * | 2003-05-07 | 2007-06-13 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
US7244326B2 (en) | 2003-05-16 | 2007-07-17 | Alien Technology Corporation | Transfer assembly for manufacturing electronic devices |
US7324061B1 (en) | 2003-05-20 | 2008-01-29 | Alien Technology Corporation | Double inductor loop tag antenna |
ATE476137T1 (en) | 2003-05-30 | 2010-08-15 | Pelikan Technologies Inc | METHOD AND DEVICE FOR INJECTING LIQUID |
DK1633235T3 (en) | 2003-06-06 | 2014-08-18 | Sanofi Aventis Deutschland | Apparatus for sampling body fluid and detecting analyte |
WO2006001797A1 (en) | 2004-06-14 | 2006-01-05 | Pelikan Technologies, Inc. | Low pain penetrating |
US7223635B1 (en) | 2003-07-25 | 2007-05-29 | Hrl Laboratories, Llc | Oriented self-location of microstructures with alignment structures |
US7015479B2 (en) * | 2003-07-31 | 2006-03-21 | Eastman Kodak Company | Digital film grain |
US8102244B2 (en) | 2003-08-09 | 2012-01-24 | Alien Technology Corporation | Methods and apparatuses to identify devices |
US7265803B2 (en) * | 2003-08-27 | 2007-09-04 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Reconfigurable logic through deposition of organic pathways |
EP1671096A4 (en) | 2003-09-29 | 2009-09-16 | Pelikan Technologies Inc | Method and apparatus for an improved sample capture device |
EP1680014A4 (en) | 2003-10-14 | 2009-01-21 | Pelikan Technologies Inc | Method and apparatus for a variable user interface |
US7716160B2 (en) | 2003-11-07 | 2010-05-11 | Alien Technology Corporation | Methods and apparatuses to identify devices |
EP1706026B1 (en) | 2003-12-31 | 2017-03-01 | Sanofi-Aventis Deutschland GmbH | Method and apparatus for improving fluidic flow and sample capture |
US7822454B1 (en) | 2005-01-03 | 2010-10-26 | Pelikan Technologies, Inc. | Fluid sampling device with improved analyte detecting member configuration |
JP4534491B2 (en) * | 2004-01-09 | 2010-09-01 | ソニー株式会社 | Manufacturing method of electronic application apparatus and assembly method of microrod transistor |
JP4396285B2 (en) * | 2004-01-21 | 2010-01-13 | ソニー株式会社 | Element array substrate and element array method |
JP3978189B2 (en) * | 2004-01-23 | 2007-09-19 | 松下電器産業株式会社 | Semiconductor device manufacturing method and manufacturing apparatus thereof |
US20080055581A1 (en) * | 2004-04-27 | 2008-03-06 | Rogers John A | Devices and methods for pattern generation by ink lithography |
JP2008507114A (en) * | 2004-04-27 | 2008-03-06 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | Composite patterning device for soft lithography |
US8828203B2 (en) | 2004-05-20 | 2014-09-09 | Sanofi-Aventis Deutschland Gmbh | Printable hydrogels for biosensors |
US9775553B2 (en) | 2004-06-03 | 2017-10-03 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for a fluid sampling device |
WO2005120365A1 (en) | 2004-06-03 | 2005-12-22 | Pelikan Technologies, Inc. | Method and apparatus for a fluid sampling device |
US7943491B2 (en) | 2004-06-04 | 2011-05-17 | The Board Of Trustees Of The University Of Illinois | Pattern transfer printing by kinetic control of adhesion to an elastomeric stamp |
US7622367B1 (en) | 2004-06-04 | 2009-11-24 | The Board Of Trustees Of The University Of Illinois | Methods and devices for fabricating and assembling printable semiconductor elements |
US7799699B2 (en) * | 2004-06-04 | 2010-09-21 | The Board Of Trustees Of The University Of Illinois | Printable semiconductor structures and related methods of making and assembling |
US8217381B2 (en) | 2004-06-04 | 2012-07-10 | The Board Of Trustees Of The University Of Illinois | Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics |
US7521292B2 (en) | 2004-06-04 | 2009-04-21 | The Board Of Trustees Of The University Of Illinois | Stretchable form of single crystal silicon for high performance electronics on rubber substrates |
US20050281944A1 (en) * | 2004-06-17 | 2005-12-22 | Jang Bor Z | Fluid-assisted self-assembly of meso-scale particles |
CN102305896B (en) | 2004-06-21 | 2015-05-13 | 卡普雷斯股份有限公司 | A method for providing alignment of a probe |
EP2463668A2 (en) | 2004-06-21 | 2012-06-13 | Capres A/S | A method and an apparatus for testing electrical properties |
DE102004044179B4 (en) * | 2004-06-30 | 2010-04-22 | Osram Opto Semiconductors Gmbh | Method for mounting semiconductor chips |
US7307527B2 (en) * | 2004-07-01 | 2007-12-11 | Avery Dennison Corporation | RFID device preparation system and method |
US20070007637A1 (en) * | 2004-08-12 | 2007-01-11 | Marinov Valery R | Multi-layered substrate assembly with vialess electrical interconnect scheme |
US20060044769A1 (en) * | 2004-09-01 | 2006-03-02 | Forster Ian J | RFID device with magnetic coupling |
US20060051517A1 (en) * | 2004-09-03 | 2006-03-09 | Eastman Kodak Company | Thermally controlled fluidic self-assembly method and support |
US7251882B2 (en) | 2004-09-03 | 2007-08-07 | Eastman Kodak Company | Method for assembling micro-components to binding sites |
US7629026B2 (en) * | 2004-09-03 | 2009-12-08 | Eastman Kodak Company | Thermally controlled fluidic self-assembly |
US7501955B2 (en) * | 2004-09-13 | 2009-03-10 | Avery Dennison Corporation | RFID device with content insensitivity and position insensitivity |
US7500307B2 (en) * | 2004-09-22 | 2009-03-10 | Avery Dennison Corporation | High-speed RFID circuit placement method |
US7221277B2 (en) | 2004-10-05 | 2007-05-22 | Tracking Technologies, Inc. | Radio frequency identification tag and method of making the same |
US7452748B1 (en) | 2004-11-08 | 2008-11-18 | Alien Technology Corporation | Strap assembly comprising functional block deposited therein and method of making same |
US7353598B2 (en) | 2004-11-08 | 2008-04-08 | Alien Technology Corporation | Assembly comprising functional devices and method of making same |
US7551141B1 (en) | 2004-11-08 | 2009-06-23 | Alien Technology Corporation | RFID strap capacitively coupled and method of making same |
JP4548096B2 (en) * | 2004-11-11 | 2010-09-22 | ソニー株式会社 | Fitting structure between semiconductor chip and substrate, semiconductor chip mounting method and electronic device |
US20060109130A1 (en) * | 2004-11-22 | 2006-05-25 | Hattick John B | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
US7385284B2 (en) | 2004-11-22 | 2008-06-10 | Alien Technology Corporation | Transponder incorporated into an electronic device |
US7688206B2 (en) | 2004-11-22 | 2010-03-30 | Alien Technology Corporation | Radio frequency identification (RFID) tag for an item having a conductive layer included or attached |
US7342490B2 (en) * | 2004-11-23 | 2008-03-11 | Alien Technology Corporation | Radio frequency identification static discharge protection |
US7332361B2 (en) * | 2004-12-14 | 2008-02-19 | Palo Alto Research Center Incorporated | Xerographic micro-assembler |
US20060131505A1 (en) * | 2004-12-17 | 2006-06-22 | Eastman Kodak Company | Imaging element |
US7538756B2 (en) * | 2004-12-17 | 2009-05-26 | Eastman Kodak Company | Methods for making display |
US7515149B2 (en) * | 2004-12-17 | 2009-04-07 | Eastman Kodak Company | Display with wirelessly controlled illumination |
US7417550B2 (en) * | 2004-12-20 | 2008-08-26 | 3M Innovative Properties Company | Environmentally friendly radio frequency identification (RFID) labels and methods of using such labels |
US7687277B2 (en) * | 2004-12-22 | 2010-03-30 | Eastman Kodak Company | Thermally controlled fluidic self-assembly |
MX2007007939A (en) * | 2004-12-27 | 2007-11-07 | Quantum Paper Inc | Addressable and printable emissive display. |
US8652831B2 (en) | 2004-12-30 | 2014-02-18 | Sanofi-Aventis Deutschland Gmbh | Method and apparatus for analyte measurement test time |
TW200633037A (en) * | 2005-01-24 | 2006-09-16 | Matsushita Electric Ind Co Ltd | Manufacturing method for semiconductor chips, and semiconductor chip |
US8711063B2 (en) | 2005-03-11 | 2014-04-29 | The Invention Science Fund I, Llc | Self assembly of elements for displays |
US20060202944A1 (en) * | 2005-03-11 | 2006-09-14 | Searete Llc, A Limited Liability Corporation Of The State Of Delaware | Elements for self assembling displays |
US8860635B2 (en) * | 2005-04-04 | 2014-10-14 | The Invention Science Fund I, Llc | Self assembling display with substrate |
US8390537B2 (en) * | 2005-03-11 | 2013-03-05 | The Invention Science Fund I, Llc | Method of assembling displays on substrates |
US9153163B2 (en) * | 2005-03-11 | 2015-10-06 | The Invention Science Fund I, Llc | Self assembly of elements for displays |
US8300007B2 (en) * | 2005-03-11 | 2012-10-30 | The Invention Science Fund I, Llc | Self assembling display with substrate |
US7977130B2 (en) | 2006-08-03 | 2011-07-12 | The Invention Science Fund I, Llc | Method of assembling displays on substrates |
US7662008B2 (en) * | 2005-04-04 | 2010-02-16 | Searete Llc | Method of assembling displays on substrates |
US7990349B2 (en) * | 2005-04-22 | 2011-08-02 | The Invention Science Fund I, Llc | Superimposed displays |
US8334819B2 (en) * | 2005-03-11 | 2012-12-18 | The Invention Science Fund I, Llc | Superimposed displays |
US7625780B2 (en) * | 2005-03-15 | 2009-12-01 | Regents Of The University Of Minnesota | Fluidic heterogeneous microsystems assembly and packaging |
US7623034B2 (en) * | 2005-04-25 | 2009-11-24 | Avery Dennison Corporation | High-speed RFID circuit placement method and device |
US7542301B1 (en) | 2005-06-22 | 2009-06-02 | Alien Technology Corporation | Creating recessed regions in a substrate and assemblies having such recessed regions |
US7943052B2 (en) * | 2005-07-05 | 2011-05-17 | National Taiwan University | Method for self-assembling microstructures |
US20070031992A1 (en) * | 2005-08-05 | 2007-02-08 | Schatz Kenneth D | Apparatuses and methods facilitating functional block deposition |
US20070040688A1 (en) | 2005-08-16 | 2007-02-22 | X-Cyte, Inc., A California Corporation | RFID inlays and methods of their manufacture |
ES2609505T3 (en) * | 2005-08-22 | 2017-04-20 | Avery Dennison Retail Information Services, Llc | Method for performing RFID devices |
US20070082464A1 (en) * | 2005-10-11 | 2007-04-12 | Schatz Kenneth D | Apparatus for block assembly process |
US8022416B2 (en) * | 2005-10-19 | 2011-09-20 | General Electric Company | Functional blocks for assembly |
US7926176B2 (en) * | 2005-10-19 | 2011-04-19 | General Electric Company | Methods for magnetically directed self assembly |
US7555826B2 (en) | 2005-12-22 | 2009-07-07 | Avery Dennison Corporation | Method of manufacturing RFID devices |
US20070158804A1 (en) * | 2006-01-10 | 2007-07-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method of semiconductor device, and RFID tag |
US7154283B1 (en) | 2006-02-22 | 2006-12-26 | Avery Dennison Corporation | Method of determining performance of RFID devices |
JP2009528254A (en) | 2006-03-03 | 2009-08-06 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | Spatally arranged nanotubes and method of making nanotube arrays |
US7774929B2 (en) * | 2006-03-14 | 2010-08-17 | Regents Of The University Of Minnesota | Method of self-assembly on a surface |
KR100847598B1 (en) * | 2006-05-10 | 2008-07-21 | 주식회사 큐리어스 | Backlight unit and method for manufacturing the unit |
TWI294404B (en) * | 2006-07-18 | 2008-03-11 | Ind Tech Res Inst | Method and apparatus for microstructure assembly |
KR100755656B1 (en) * | 2006-08-11 | 2007-09-04 | 삼성전기주식회사 | Method of manufacturing nitride-based semiconductor light emitting device |
US7875952B1 (en) | 2006-09-19 | 2011-01-25 | Hrl Laboratories, Llc | Method of transistor level heterogeneous integration and system |
JP5171016B2 (en) * | 2006-10-27 | 2013-03-27 | キヤノン株式会社 | Semiconductor member, manufacturing method of semiconductor article, and LED array using the manufacturing method |
JP2008118024A (en) * | 2006-11-07 | 2008-05-22 | Sony Corp | Light-emitting device and its manufacturing method |
US20080135956A1 (en) * | 2006-12-12 | 2008-06-12 | General Electric Company | Articles and assembly for magnetically directed self assembly and methods of manufacture |
JP5700750B2 (en) | 2007-01-17 | 2015-04-15 | ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ | Optical system manufactured by printing base assembly |
US20080229574A1 (en) * | 2007-03-19 | 2008-09-25 | Advanced Chip Engineering Technology Inc. | Self chip redistribution apparatus and method for the same |
US8809126B2 (en) | 2007-05-31 | 2014-08-19 | Nthdegree Technologies Worldwide Inc | Printable composition of a liquid or gel suspension of diodes |
US9018833B2 (en) | 2007-05-31 | 2015-04-28 | Nthdegree Technologies Worldwide Inc | Apparatus with light emitting or absorbing diodes |
US8846457B2 (en) | 2007-05-31 | 2014-09-30 | Nthdegree Technologies Worldwide Inc | Printable composition of a liquid or gel suspension of diodes |
US8133768B2 (en) * | 2007-05-31 | 2012-03-13 | Nthdegree Technologies Worldwide Inc | Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system |
US9425357B2 (en) | 2007-05-31 | 2016-08-23 | Nthdegree Technologies Worldwide Inc. | Diode for a printable composition |
US9343593B2 (en) | 2007-05-31 | 2016-05-17 | Nthdegree Technologies Worldwide Inc | Printable composition of a liquid or gel suspension of diodes |
US8415879B2 (en) | 2007-05-31 | 2013-04-09 | Nthdegree Technologies Worldwide Inc | Diode for a printable composition |
US8674593B2 (en) | 2007-05-31 | 2014-03-18 | Nthdegree Technologies Worldwide Inc | Diode for a printable composition |
US8889216B2 (en) * | 2007-05-31 | 2014-11-18 | Nthdegree Technologies Worldwide Inc | Method of manufacturing addressable and static electronic displays |
US8456392B2 (en) | 2007-05-31 | 2013-06-04 | Nthdegree Technologies Worldwide Inc | Method of manufacturing a light emitting, photovoltaic or other electronic apparatus and system |
US8877101B2 (en) | 2007-05-31 | 2014-11-04 | Nthdegree Technologies Worldwide Inc | Method of manufacturing a light emitting, power generating or other electronic apparatus |
US8852467B2 (en) | 2007-05-31 | 2014-10-07 | Nthdegree Technologies Worldwide Inc | Method of manufacturing a printable composition of a liquid or gel suspension of diodes |
US9534772B2 (en) | 2007-05-31 | 2017-01-03 | Nthdegree Technologies Worldwide Inc | Apparatus with light emitting diodes |
US9419179B2 (en) | 2007-05-31 | 2016-08-16 | Nthdegree Technologies Worldwide Inc | Diode for a printable composition |
DE202007018520U1 (en) | 2007-08-17 | 2008-10-09 | Advanced Display Technology Ag | Pixel device and display with pixel device |
US8674212B2 (en) * | 2008-01-15 | 2014-03-18 | General Electric Company | Solar cell and magnetically self-assembled solar cell assembly |
US7861405B2 (en) | 2008-03-03 | 2011-01-04 | Palo Alto Research Center Incorporated | System for forming a micro-assembler |
US8552299B2 (en) | 2008-03-05 | 2013-10-08 | The Board Of Trustees Of The University Of Illinois | Stretchable and foldable electronic devices |
US8470701B2 (en) * | 2008-04-03 | 2013-06-25 | Advanced Diamond Technologies, Inc. | Printable, flexible and stretchable diamond for thermal management |
EP2277131A2 (en) | 2008-04-07 | 2011-01-26 | Alien Technology Corporation | Subset selection of rfid tags using light |
WO2009126900A1 (en) | 2008-04-11 | 2009-10-15 | Pelikan Technologies, Inc. | Method and apparatus for analyte detecting device |
US7992332B2 (en) | 2008-05-13 | 2011-08-09 | Nthdegree Technologies Worldwide Inc. | Apparatuses for providing power for illumination of a display object |
US8127477B2 (en) | 2008-05-13 | 2012-03-06 | Nthdegree Technologies Worldwide Inc | Illuminating display systems |
EP2286445A1 (en) * | 2008-06-02 | 2011-02-23 | Nxp B.V. | Method for manufacturing an electronic device |
WO2010005707A1 (en) * | 2008-06-16 | 2010-01-14 | The Board Of Trustees Of The University Of Illinois | Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates |
US8886334B2 (en) | 2008-10-07 | 2014-11-11 | Mc10, Inc. | Systems, methods, and devices using stretchable or flexible electronics for medical applications |
JP5646492B2 (en) | 2008-10-07 | 2014-12-24 | エムシー10 インコーポレイテッドMc10,Inc. | Stretchable integrated circuit and device with sensor array |
US8097926B2 (en) | 2008-10-07 | 2012-01-17 | Mc10, Inc. | Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy |
US8372726B2 (en) | 2008-10-07 | 2013-02-12 | Mc10, Inc. | Methods and applications of non-planar imaging arrays |
US8389862B2 (en) | 2008-10-07 | 2013-03-05 | Mc10, Inc. | Extremely stretchable electronics |
US8288877B1 (en) | 2008-10-25 | 2012-10-16 | Hrl Laboratories, Llc | Actuator enhanced alignment of self-assembled microstructures |
US8736082B1 (en) | 2008-10-25 | 2014-05-27 | Hrl Laboratories, Llc | Key structure and expansion enhanced alignment of self-assembled microstructures |
KR20100087932A (en) * | 2009-01-29 | 2010-08-06 | 삼성전기주식회사 | A method for die attach using self-assemble monolayer and a package substrate attached die using the self-assemble monolayer |
US9375169B2 (en) | 2009-01-30 | 2016-06-28 | Sanofi-Aventis Deutschland Gmbh | Cam drive for managing disposable penetrating member actions with a single motor and motor and control system |
US8748730B2 (en) * | 2009-03-13 | 2014-06-10 | California Institute Of Technology | Systems and methods for concentrating solar energy without tracking the sun |
KR101706915B1 (en) | 2009-05-12 | 2017-02-15 | 더 보드 오브 트러스티즈 오브 더 유니버시티 오브 일리노이 | Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays |
JP5256501B2 (en) * | 2009-06-16 | 2013-08-07 | コニカミノルタ株式会社 | Method for manufacturing flaky element array substrate and thermoelectric conversion module |
GB0914251D0 (en) * | 2009-08-14 | 2009-09-30 | Nat Univ Ireland Cork | A hybrid substrate |
US9723122B2 (en) | 2009-10-01 | 2017-08-01 | Mc10, Inc. | Protective cases with integrated electronics |
US9936574B2 (en) | 2009-12-16 | 2018-04-03 | The Board Of Trustees Of The University Of Illinois | Waterproof stretchable optoelectronics |
US10441185B2 (en) | 2009-12-16 | 2019-10-15 | The Board Of Trustees Of The University Of Illinois | Flexible and stretchable electronic systems for epidermal electronics |
EP2513953B1 (en) | 2009-12-16 | 2017-10-18 | The Board of Trustees of the University of Illionis | Electrophysiology using conformal electronics |
KR101837481B1 (en) | 2010-03-17 | 2018-03-13 | 더 보드 오브 트러스티즈 오브 더 유니버시티 오브 일리노이 | implantable biomedical devices on bioresorbable substrates |
WO2011114741A1 (en) * | 2010-03-19 | 2011-09-22 | Panasonic Corporation | Method for disposing a microstructure |
US8965476B2 (en) | 2010-04-16 | 2015-02-24 | Sanofi-Aventis Deutschland Gmbh | Tissue penetration device |
KR101058880B1 (en) | 2010-05-07 | 2011-08-25 | 서울대학교산학협력단 | Led display apparatus having active devices and fabrication method thereof |
US8349653B2 (en) | 2010-06-02 | 2013-01-08 | Maxim Integrated Products, Inc. | Use of device assembly for a generalization of three-dimensional metal interconnect technologies |
US10672748B1 (en) | 2010-06-02 | 2020-06-02 | Maxim Integrated Products, Inc. | Use of device assembly for a generalization of three-dimensional heterogeneous technologies integration |
US10329139B2 (en) | 2010-06-08 | 2019-06-25 | Northeastern University | Interfacial convective assembly for high aspect ratio structures without surface treatment |
US9181630B2 (en) * | 2010-07-14 | 2015-11-10 | Sharp Kabushiki Kaisha | Method for disposing fine objects, apparatus for arranging fine objects, illuminating apparatus and display apparatus |
KR20130117766A (en) * | 2010-09-01 | 2013-10-28 | 엔티에이치 디그리 테크놀로지스 월드와이드 인코포레이티드 | Diodes, printable compositions of a liquid or gel suspension of diodes or other two-terminal integrated circuits, and methods of making same |
KR102321916B1 (en) | 2010-09-01 | 2021-11-05 | 엔티에이치 디그리 테크놀로지스 월드와이드 인코포레이티드 | Light emitting, power generating or other electronic apparatus and method of manufacturing same |
US9442285B2 (en) | 2011-01-14 | 2016-09-13 | The Board Of Trustees Of The University Of Illinois | Optical component array having adjustable curvature |
US9765934B2 (en) | 2011-05-16 | 2017-09-19 | The Board Of Trustees Of The University Of Illinois | Thermally managed LED arrays assembled by printing |
EP2712491B1 (en) | 2011-05-27 | 2019-12-04 | Mc10, Inc. | Flexible electronic structure |
EP2713863B1 (en) | 2011-06-03 | 2020-01-15 | The Board of Trustees of the University of Illionis | Conformable actively multiplexed high-density surface electrode array for brain interfacing |
US20130175516A1 (en) * | 2011-09-02 | 2013-07-11 | The Procter & Gamble Company | Light emitting apparatus |
CN104472023B (en) | 2011-12-01 | 2018-03-27 | 伊利诺伊大学评议会 | It is designed to undergo the transient state device of programmable transformation |
US20130199831A1 (en) | 2012-02-06 | 2013-08-08 | Christopher Morris | Electromagnetic field assisted self-assembly with formation of electrical contacts |
TWI631697B (en) | 2012-02-17 | 2018-08-01 | 財團法人工業技術研究院 | Light emitting element and fabricating method thereof |
KR20150004819A (en) | 2012-03-30 | 2015-01-13 | 더 보오드 오브 트러스티스 오브 더 유니버시티 오브 일리노이즈 | Appendage mountable electronic devices conformable to surfaces |
WO2013158949A1 (en) * | 2012-04-20 | 2013-10-24 | Rensselaer Polytechnic Institute | Light emitting diodes and a method of packaging the same |
EP2790212B1 (en) | 2012-07-19 | 2015-09-16 | Technische Universität Ilmenau | Method of self-assembly of components on a substrate |
EP2690059A1 (en) * | 2012-07-24 | 2014-01-29 | Biocartis SA | Method for producing microcarriers |
WO2014040614A1 (en) * | 2012-09-11 | 2014-03-20 | Osram Opto Semiconductors Gmbh | Method for producing an optoelectronic device and optoelectronic device |
US9171794B2 (en) | 2012-10-09 | 2015-10-27 | Mc10, Inc. | Embedding thin chips in polymer |
CN103000780B (en) * | 2012-12-14 | 2015-08-05 | 京东方科技集团股份有限公司 | A kind of LED chip encapsulating structure and manufacture method, display unit |
JP6068165B2 (en) | 2013-01-29 | 2017-01-25 | スタンレー電気株式会社 | Semiconductor optical device and method of manufacturing semiconductor optical device |
US9548411B2 (en) * | 2013-03-15 | 2017-01-17 | Sandia Corporation | Photoelectrochemically driven self-assembly method |
JP2015038957A (en) * | 2013-07-16 | 2015-02-26 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
CN103531458A (en) * | 2013-09-09 | 2014-01-22 | 长春理工大学 | Method for carrying out wet etching on GaAs-based material by utilizing two-step method |
KR101534705B1 (en) * | 2013-12-30 | 2015-07-07 | 현대자동차 주식회사 | Method for junction of semiconductor substrate |
US9305807B2 (en) | 2014-02-27 | 2016-04-05 | Palo Alto Research Center Incorporated | Fabrication method for microelectronic components and microchip inks used in electrostatic assembly |
US10312731B2 (en) | 2014-04-24 | 2019-06-04 | Westrock Shared Services, Llc | Powered shelf system for inductively powering electrical components of consumer product packages |
WO2016057796A1 (en) * | 2014-10-08 | 2016-04-14 | The Arizona Board Of Regents On Behalf Of The University Of Arizona | Flowable electronics |
FR3028050B1 (en) * | 2014-10-29 | 2016-12-30 | Commissariat Energie Atomique | PRE-STRUCTURED SUBSTRATE FOR THE PRODUCTION OF PHOTONIC COMPONENTS, PHOTONIC CIRCUIT, AND METHOD OF MANUFACTURING THE SAME |
US10852492B1 (en) * | 2014-10-29 | 2020-12-01 | Acacia Communications, Inc. | Techniques to combine two integrated photonic substrates |
US9755110B1 (en) | 2016-07-27 | 2017-09-05 | Sharp Laboratories Of America, Inc. | Substrate with topological features for steering fluidic assembly LED disks |
US10446728B2 (en) * | 2014-10-31 | 2019-10-15 | eLux, Inc. | Pick-and remove system and method for emissive display repair |
US10520769B2 (en) | 2014-10-31 | 2019-12-31 | eLux, Inc. | Emissive display with printed light modification structures |
US10242977B2 (en) | 2014-10-31 | 2019-03-26 | eLux, Inc. | Fluid-suspended microcomponent harvest, distribution, and reclamation |
US9985190B2 (en) | 2016-05-18 | 2018-05-29 | eLux Inc. | Formation and structure of post enhanced diodes for orientation control |
US10319878B2 (en) | 2014-10-31 | 2019-06-11 | eLux, Inc. | Stratified quantum dot phosphor structure |
US10535640B2 (en) | 2014-10-31 | 2020-01-14 | eLux Inc. | System and method for the fluidic assembly of micro-LEDs utilizing negative pressure |
US10543486B2 (en) | 2014-10-31 | 2020-01-28 | eLux Inc. | Microperturbation assembly system and method |
US9722145B2 (en) * | 2015-06-24 | 2017-08-01 | Sharp Laboratories Of America, Inc. | Light emitting device and fluidic manufacture thereof |
US9825202B2 (en) | 2014-10-31 | 2017-11-21 | eLux, Inc. | Display with surface mount emissive elements |
US10236279B2 (en) | 2014-10-31 | 2019-03-19 | eLux, Inc. | Emissive display with light management system |
US10381332B2 (en) | 2014-10-31 | 2019-08-13 | eLux Inc. | Fabrication method for emissive display with light management system |
US10516084B2 (en) * | 2014-10-31 | 2019-12-24 | eLux, Inc. | Encapsulated fluid assembly emissive elements |
US9892944B2 (en) | 2016-06-23 | 2018-02-13 | Sharp Kabushiki Kaisha | Diodes offering asymmetric stability during fluidic assembly |
US10249599B2 (en) | 2016-06-29 | 2019-04-02 | eLux, Inc. | Laminated printed color conversion phosphor sheets |
US9917226B1 (en) * | 2016-09-15 | 2018-03-13 | Sharp Kabushiki Kaisha | Substrate features for enhanced fluidic assembly of electronic devices |
US10381335B2 (en) | 2014-10-31 | 2019-08-13 | ehux, Inc. | Hybrid display using inorganic micro light emitting diodes (uLEDs) and organic LEDs (OLEDs) |
US10418527B2 (en) * | 2014-10-31 | 2019-09-17 | eLux, Inc. | System and method for the fluidic assembly of emissive displays |
US10677647B2 (en) | 2015-06-01 | 2020-06-09 | The Board Of Trustees Of The University Of Illinois | Miniaturized electronic systems with wireless power and near-field communication capabilities |
EP3304130B1 (en) | 2015-06-01 | 2021-10-06 | The Board of Trustees of the University of Illinois | Alternative approach to uv sensing |
TWI665800B (en) * | 2015-06-16 | 2019-07-11 | 友達光電股份有限公司 | Light emitting diode display and manufacturing method thereof |
US10539433B2 (en) * | 2015-08-17 | 2020-01-21 | Pangolin Laser Systems, Inc. | Light detector employing trapezoidal chips and associated methods |
US10925543B2 (en) | 2015-11-11 | 2021-02-23 | The Board Of Trustees Of The University Of Illinois | Bioresorbable silicon electronics for transient implants |
US9627437B1 (en) | 2016-06-30 | 2017-04-18 | Sharp Laboratories Of America, Inc. | Patterned phosphors in through hole via (THV) glass |
CN107689410B (en) * | 2016-08-05 | 2020-01-17 | 群创光电股份有限公司 | Light emitting diode display device |
US10243097B2 (en) | 2016-09-09 | 2019-03-26 | eLux Inc. | Fluidic assembly using tunable suspension flow |
CN107833525B (en) * | 2016-09-15 | 2020-10-27 | 伊乐视有限公司 | System and method for fluid assembly of light emitting displays |
US9837390B1 (en) | 2016-11-07 | 2017-12-05 | Corning Incorporated | Systems and methods for creating fluidic assembly structures on a substrate |
EP3352211B1 (en) * | 2017-01-19 | 2020-08-05 | eLux Inc. | Method for the fluidic assembly of emissive displays |
CN110235231B (en) * | 2017-01-31 | 2023-07-25 | 株式会社新川 | Method and apparatus for manufacturing semiconductor device |
TWI785052B (en) * | 2017-06-01 | 2022-12-01 | 美商康寧公司 | Assembly substrates including through hole vias and methods for making such |
CN107681462B (en) * | 2017-09-12 | 2019-10-08 | 北京工业大学 | A kind of semiconductor chip autoregistration pendulum |
CN107651648B (en) * | 2017-10-20 | 2019-11-22 | 常州工学院 | One kind motivating micro element self-assembly device and method based on micro-vibration |
WO2019132050A1 (en) * | 2017-12-26 | 2019-07-04 | 박일우 | Led display device and method for manufacturing same |
CN110112075A (en) * | 2018-02-01 | 2019-08-09 | 上海瑞章物联网技术有限公司 | The packaging method of chip |
WO2019181045A1 (en) * | 2018-03-23 | 2019-09-26 | 株式会社 東芝 | Treatment solution and treatment method |
CN110349865A (en) * | 2018-04-04 | 2019-10-18 | 上海瑞章物联网技术有限公司 | The packaging method of chip |
CN110364470A (en) * | 2018-04-11 | 2019-10-22 | 上海瑞章物联网技术有限公司 | For the carrier of wafer package and the packaging method of chip |
WO2020029657A1 (en) * | 2018-08-10 | 2020-02-13 | 林宏诚 | Diode device, display panel, and flexible display |
CN110911435A (en) * | 2018-09-14 | 2020-03-24 | 英属开曼群岛商镎创科技股份有限公司 | Display device, manufacturing method of display device and substrate of display device |
CN111129245B (en) * | 2018-10-31 | 2022-09-06 | 成都辰显光电有限公司 | LED chip, display panel and display panel's equipment |
CN111162064B (en) * | 2018-11-08 | 2022-03-25 | 成都辰显光电有限公司 | LED unit, guide plate, LED display and manufacturing method thereof |
CN111816751B (en) * | 2019-04-12 | 2022-02-22 | 成都辰显光电有限公司 | Micro light-emitting diode display panel and preparation method thereof |
KR102323256B1 (en) * | 2019-09-19 | 2021-11-08 | 엘지전자 주식회사 | Self assembly device for semiconductor light emitting device |
CN113314446B (en) * | 2020-02-27 | 2023-06-02 | 上海微电子装备(集团)股份有限公司 | Chip transfer device and chip transfer method |
US11562984B1 (en) | 2020-10-14 | 2023-01-24 | Hrl Laboratories, Llc | Integrated mechanical aids for high accuracy alignable-electrical contacts |
KR102511685B1 (en) * | 2020-12-09 | 2023-03-21 | (주)포인트엔지니어링 | Micro device, alignment apparatus for the micro device and alignment method using it |
DE102021102332A1 (en) * | 2021-02-02 | 2022-08-04 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | METHOD OF MANUFACTURING AN ARRAY OF SEMICONDUCTOR CHIPS AND ARRANGEMENT OF SEMICONDUCTOR CHIPS |
WO2023016625A1 (en) | 2021-08-09 | 2023-02-16 | X-Celeprint Limited | Integrated-circuit module collection and deposition |
CN116705924A (en) * | 2023-08-04 | 2023-09-05 | 季华实验室 | Light-emitting unit transferring method and screen |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3439416A (en) * | 1966-02-03 | 1969-04-22 | Gen Telephone & Elect | Method and apparatus for fabricating an array of discrete elements |
GB1285708A (en) * | 1968-10-28 | 1972-08-16 | Lucas Industries Ltd | Semi-conductor devices |
GB1315479A (en) * | 1970-06-24 | 1973-05-02 | Licentia Gmbh | Method for manufacturing diodes |
US3725160A (en) * | 1970-12-30 | 1973-04-03 | Texas Instruments Inc | High density integrated circuits |
GB1581171A (en) * | 1976-04-08 | 1980-12-10 | Bison North America Inc | Alignment plate construction for electrostatic particle orientation |
DE2656019C3 (en) * | 1976-12-10 | 1980-07-17 | Brown, Boveri & Cie Ag, 6800 Mannheim | Device for aligning and soldering pedestals or discs with respect to or on the solderable ohmic contacts) of semiconductor components |
JPS6048104B2 (en) * | 1980-01-30 | 1985-10-25 | 三洋電機株式会社 | How to divide semiconductor wafers |
US4843035A (en) * | 1981-07-23 | 1989-06-27 | Clarion Co., Ltd. | Method for connecting elements of a circuit device |
GB2154365A (en) * | 1984-02-10 | 1985-09-04 | Philips Electronic Associated | Loading semiconductor wafers on an electrostatic chuck |
US4542397A (en) * | 1984-04-12 | 1985-09-17 | Xerox Corporation | Self aligning small scale integrated circuit semiconductor chips to form large area arrays |
JPS6281745A (en) * | 1985-10-05 | 1987-04-15 | Fujitsu Ltd | Lsi semiconductor device in wafer scale and manufacture thereof |
US4802951A (en) * | 1986-03-07 | 1989-02-07 | Trustees Of Boston University | Method for parallel fabrication of nanometer scale multi-device structures |
US5187547A (en) * | 1988-05-18 | 1993-02-16 | Sanyo Electric Co., Ltd. | Light emitting diode device and method for producing same |
US4949148A (en) * | 1989-01-11 | 1990-08-14 | Bartelink Dirk J | Self-aligning integrated circuit assembly |
JP2784537B2 (en) * | 1989-03-29 | 1998-08-06 | 新日本無線株式会社 | Light emitting diode manufacturing method |
US4962441A (en) * | 1989-04-10 | 1990-10-09 | Applied Materials, Inc. | Isolated electrostatic wafer blade clamp |
US4990462A (en) * | 1989-04-12 | 1991-02-05 | Advanced Micro Devices, Inc. | Method for coplanar integration of semiconductor ic devices |
US5075253A (en) * | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
GB2237143A (en) * | 1989-09-15 | 1991-04-24 | Philips Electronic Associated | Two-terminal non-linear devices and their fabrication |
US4975143A (en) * | 1989-11-22 | 1990-12-04 | Xerox Corporation | Keyway alignment substrates |
US5034802A (en) * | 1989-12-11 | 1991-07-23 | Hewlett-Packard Company | Mechanical simultaneous registration of multi-pin surface-mount components to sites on substrates |
US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
JPH04148999A (en) * | 1990-10-12 | 1992-05-21 | Dainippon Printing Co Ltd | Ic card |
JP2940138B2 (en) * | 1990-10-29 | 1999-08-25 | 日本電気株式会社 | Light emitting diode |
US5258325A (en) * | 1990-12-31 | 1993-11-02 | Kopin Corporation | Method for manufacturing a semiconductor device using a circuit transfer film |
US5355577A (en) * | 1992-06-23 | 1994-10-18 | Cohn Michael B | Method and apparatus for the assembly of microfabricated devices |
-
1993
- 1993-12-17 US US08/169,298 patent/US5545291A/en not_active Expired - Lifetime
-
1994
- 1994-12-07 CN CNB2006100819051A patent/CN100466250C/en not_active Expired - Lifetime
- 1994-12-07 EP EP95904304A patent/EP0734586B1/en not_active Expired - Lifetime
- 1994-12-07 WO PCT/US1994/014152 patent/WO1995017005A1/en active IP Right Grant
- 1994-12-07 CA CA002177276A patent/CA2177276C/en not_active Expired - Fee Related
- 1994-12-07 JP JP51684695A patent/JP3535166B2/en not_active Expired - Fee Related
- 1994-12-07 DE DE69433361T patent/DE69433361T2/en not_active Expired - Lifetime
- 1994-12-07 EP EP03020566A patent/EP1372194A1/en not_active Withdrawn
- 1994-12-07 CN CN94194495A patent/CN1103118C/en not_active Expired - Fee Related
- 1994-12-07 CN CNB021561044A patent/CN1263098C/en not_active Expired - Lifetime
- 1994-12-07 EP EP04014244A patent/EP1463116A3/en not_active Withdrawn
- 1994-12-07 AU AU13046/95A patent/AU681928B2/en not_active Ceased
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1995
- 1995-05-09 US US08/437,540 patent/US5783856A/en not_active Expired - Lifetime
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2003
- 2003-12-10 JP JP2003411714A patent/JP3884426B2/en not_active Expired - Fee Related
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DE69433361D1 (en) | 2004-01-08 |
JPH09506742A (en) | 1997-06-30 |
CN1263098C (en) | 2006-07-05 |
EP1372194A1 (en) | 2003-12-17 |
AU681928B2 (en) | 1997-09-11 |
JP2004165680A (en) | 2004-06-10 |
AU1304695A (en) | 1995-07-03 |
JP3828567B2 (en) | 2006-10-04 |
JP3535166B2 (en) | 2004-06-07 |
CN1103118C (en) | 2003-03-12 |
EP0734586A1 (en) | 1996-10-02 |
EP0734586B1 (en) | 2003-11-26 |
CN100466250C (en) | 2009-03-04 |
JP2006074062A (en) | 2006-03-16 |
US5783856A (en) | 1998-07-21 |
EP1463116A3 (en) | 2007-12-05 |
CN1137329A (en) | 1996-12-04 |
CN1492483A (en) | 2004-04-28 |
US5545291A (en) | 1996-08-13 |
DE69433361T2 (en) | 2004-09-16 |
EP1463116A2 (en) | 2004-09-29 |
CA2177276A1 (en) | 1995-06-22 |
JP3884426B2 (en) | 2007-02-21 |
WO1995017005A1 (en) | 1995-06-22 |
CN1893062A (en) | 2007-01-10 |
EP0734586A4 (en) | 1998-10-14 |
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