CA2179235A1 - Built-in test scheme for a jitter tolerance test of a clock and data recovery unit - Google Patents

Built-in test scheme for a jitter tolerance test of a clock and data recovery unit

Info

Publication number
CA2179235A1
CA2179235A1 CA2179235A CA2179235A CA2179235A1 CA 2179235 A1 CA2179235 A1 CA 2179235A1 CA 2179235 A CA2179235 A CA 2179235A CA 2179235 A CA2179235 A CA 2179235A CA 2179235 A1 CA2179235 A1 CA 2179235A1
Authority
CA
Canada
Prior art keywords
clock
test
recovery unit
built
data recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2179235A
Other languages
French (fr)
Other versions
CA2179235C (en
Inventor
Kamal Dalmia
Andre Ivanov
Brian Donald Gerson
Curtis Lapadat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Storage Solutions Ltd
Original Assignee
PMC Sierra Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PMC Sierra Inc filed Critical PMC Sierra Inc
Publication of CA2179235A1 publication Critical patent/CA2179235A1/en
Application granted granted Critical
Publication of CA2179235C publication Critical patent/CA2179235C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/3171—BER [Bit Error Rate] test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31709—Jitter measurements; Jitter generators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation

Abstract

A jitter test system for a clock and data recovery unit (CRU) is comprised of a data generating apparatus, apparatus for clocking the data generating apparatus with a jittered clock, apparatus for applying a stream of data generated by the data generating apparatus that has been jittered by the jittered clock to an input of the CRU, and apparatus for detecting a bit error rate of a data signal output from the CRU.
CA002179235A 1996-03-04 1996-06-17 Built-in test scheme for a jitter tolerance test of a clock and data recovery unit Expired - Fee Related CA2179235C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/607,990 1996-03-04
US08/607,990 US5835501A (en) 1996-03-04 1996-03-04 Built-in test scheme for a jitter tolerance test of a clock and data recovery unit

Publications (2)

Publication Number Publication Date
CA2179235A1 true CA2179235A1 (en) 1997-09-05
CA2179235C CA2179235C (en) 2000-03-28

Family

ID=24434574

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002179235A Expired - Fee Related CA2179235C (en) 1996-03-04 1996-06-17 Built-in test scheme for a jitter tolerance test of a clock and data recovery unit

Country Status (2)

Country Link
US (1) US5835501A (en)
CA (1) CA2179235C (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1050053A4 (en) * 1998-01-30 2004-10-20 Credence Systems Corp Event phase modulator for integrated circuit tester
CN111147071A (en) * 2019-12-31 2020-05-12 中国人民解放军空军工程大学 Proportional path gain regulator applied to clock data recovery circuit

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JP3156644B2 (en) * 1997-07-25 2001-04-16 日本電気株式会社 Semiconductor integrated circuit
US6834367B2 (en) * 1999-12-22 2004-12-21 International Business Machines Corporation Built-in self test system and method for high speed clock and data recovery circuit
US7206339B2 (en) * 1999-12-24 2007-04-17 Anritsu Corporation Wonder generator, digital line tester comprising the same, and phase noise transfer characteristic analyzer
US6754613B2 (en) * 2000-03-17 2004-06-22 Vector 12 Corporation High resolution time-to-digital converter
US20030076181A1 (en) * 2000-03-17 2003-04-24 Sassan Tabatabaei Tunable oscillators and signal generation methods
DE10048467B4 (en) * 2000-09-29 2004-11-25 Siemens Ag Jitter generation for measuring the remaining jitter tolerance during operation on a transmission link with a high data rate
US6856206B1 (en) 2001-06-25 2005-02-15 Silicon Laboratories, Inc. Method and apparatus for acquiring a frequency without a reference clock
US6988227B1 (en) * 2001-06-25 2006-01-17 Silicon Laboratories Inc. Method and apparatus for bit error rate detection
EP1408672B1 (en) * 2001-07-13 2010-11-17 Anritsu Corporation Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation
US6625560B1 (en) * 2001-07-13 2003-09-23 Silicon Image, Inc. Method of testing serial interface
EP1213870A1 (en) * 2001-08-22 2002-06-12 Agilent Technologies, Inc. (a Delaware corporation) Jitter generation with delay unit
WO2003073280A1 (en) * 2002-02-26 2003-09-04 Advantest Corporation Measuring apparatus and measuring method
US20030231707A1 (en) * 2002-06-05 2003-12-18 French John Sargent Method and apparatus for jitter creation and testing
US7558835B1 (en) 2002-08-19 2009-07-07 Juniper Networks, Inc. Application of a configuration patch to a network device
US7865578B1 (en) 2002-08-19 2011-01-04 Juniper Networks, Inc. Generation of a configuration patch for network devices
US7483965B1 (en) * 2002-08-19 2009-01-27 Juniper Networks, Inc. Generation of a configuration patch for network devices
US6985823B2 (en) * 2002-10-31 2006-01-10 Finisar Corporation System and method of testing a transceiver
US7080292B2 (en) * 2003-04-09 2006-07-18 Moore Charles E Method for testing jitter tolerance of high speed receivers
US7171601B2 (en) * 2003-08-21 2007-01-30 Credence Systems Corporation Programmable jitter generator
US7409617B2 (en) * 2004-09-30 2008-08-05 Credence Systems Corporation System for measuring characteristics of a digital signal
US7627790B2 (en) * 2003-08-21 2009-12-01 Credence Systems Corporation Apparatus for jitter testing an IC
US7363563B1 (en) 2003-12-05 2008-04-22 Pmc-Sierra, Inc. Systems and methods for a built in test circuit for asynchronous testing of high-speed transceivers
US7135904B1 (en) * 2004-01-12 2006-11-14 Marvell Semiconductor Israel Ltd. Jitter producing circuitry and methods
US7523097B1 (en) 2004-01-13 2009-04-21 Juniper Networks, Inc. Restoration of archived configurations for a network device
US7480358B2 (en) * 2004-02-25 2009-01-20 Infineon Technologies Ag CDR-based clock synthesis
US20050193290A1 (en) * 2004-02-25 2005-09-01 Cho James B. Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data buffer
US7315574B2 (en) * 2004-05-03 2008-01-01 Dft Microsystems, Inc. System and method for generating a jittered test signal
US7571360B1 (en) * 2004-10-26 2009-08-04 National Semiconductor Corporation System and method for providing a clock and data recovery circuit with a fast bit error rate self test capability
US7558357B1 (en) * 2004-10-26 2009-07-07 Pmc-Sierra, Inc. Systems and methods for reducing frequency-offset induced jitter
TWI277748B (en) * 2005-08-29 2007-04-01 Via Tech Inc Time jitter injection testing circuit and related testing method
US8327204B2 (en) * 2005-10-27 2012-12-04 Dft Microsystems, Inc. High-speed transceiver tester incorporating jitter injection
US7936809B2 (en) * 2006-07-11 2011-05-03 Altera Corporation Economical, scalable transceiver jitter test
US7681091B2 (en) * 2006-07-14 2010-03-16 Dft Microsystems, Inc. Signal integrity measurement systems and methods using a predominantly digital time-base generator
US7813297B2 (en) * 2006-07-14 2010-10-12 Dft Microsystems, Inc. High-speed signal testing system having oscilloscope functionality
US7809052B2 (en) * 2006-07-27 2010-10-05 Cypress Semiconductor Corporation Test circuit, system, and method for testing one or more circuit components arranged upon a common printed circuit board
US7375591B2 (en) * 2006-08-04 2008-05-20 Silicon Laboratories Inc. Robust false locking prevention in referenceless frequency acquisition
JP2010518760A (en) * 2007-02-09 2010-05-27 ディー・エフ・ティー・マイクロシステムズ・インコーポレーテッド System and method for physical layer testing of a high speed serial link in a high speed serial link mission environment
US8037371B1 (en) 2007-05-14 2011-10-11 National Semiconductor Corporation Apparatus and method for testing high-speed serial transmitters and other devices
US7809517B1 (en) 2007-09-07 2010-10-05 National Semiconductor Corporation Apparatus and method for measuring phase noise/jitter in devices under test
US7917319B2 (en) * 2008-02-06 2011-03-29 Dft Microsystems Inc. Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits
US8249137B2 (en) * 2008-06-16 2012-08-21 Intel Corporation In-situ jitter tolerance testing for serial input output
TWI444636B (en) 2011-02-18 2014-07-11 Realtek Semiconductor Corp Method and circuit of clock data recovery with built in jitter tolerance test
US9367298B1 (en) 2012-03-28 2016-06-14 Juniper Networks, Inc. Batch configuration mode for configuring network devices
JP2014174131A (en) * 2013-03-13 2014-09-22 Fujitsu Semiconductor Ltd Receiving circuit, semiconductor integrated circuit, and test method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0345390A1 (en) * 1988-06-08 1989-12-13 Hewlett-Packard Limited Improvement in or Relating to Jitter Circuits
US5239535A (en) * 1989-05-23 1993-08-24 Siemens Aktiengesellschaft Arrangement for testing the transmission properties of subscriber line modules or digital terminal equipment of a communication system connectible thereto
GB9313020D0 (en) * 1993-06-24 1993-08-11 Madge Networks Ltd Jitter monitoring

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1050053A4 (en) * 1998-01-30 2004-10-20 Credence Systems Corp Event phase modulator for integrated circuit tester
CN111147071A (en) * 2019-12-31 2020-05-12 中国人民解放军空军工程大学 Proportional path gain regulator applied to clock data recovery circuit
CN111147071B (en) * 2019-12-31 2022-10-11 中国人民解放军空军工程大学 Proportional path gain regulator applied to clock data recovery circuit

Also Published As

Publication number Publication date
CA2179235C (en) 2000-03-28
US5835501A (en) 1998-11-10

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20140617