CA2179613A1 - Look-up engine for packet-based network - Google Patents

Abstract

An arrangement is disclosed for parsing packets in a packet-based data transmission network. The packets include packet headers divided into fields having values representing information pertaining to the packet. The arrangement comprises input receiving fields from the packet headers of incoming packets, a memory for storing information related to possible values of said fields, and a device for retrieving said stored information appropriate to a received field value. The retrieving device comprises a look-up engine including at least one memory organized in a hierarchical tree structure, and a controller for controlling the operation of the memory. The arrangement is capable of performing fast look-up operations at a low cost of implementation.

Description

~ wo 95/18497 - 2 1 7 9 61 3 PCT/CA94/00695 ~OO~-UP ENGINE FOR PAC~ET-~3ASED NETWORK
This invention relates to the field of data communications, and more particularly to packet-based networks .
S There are two broad classes of-network: circuit-baaed and packet-based. ConvAnt;A,"A~ telephone networks are circuit based When a call is estAhl ;AhAd in a circuit-based network, a hard-wired connection is set up }:etween the ca_ling parties and remains in place for the rl~Ati~An of the call. Circuit-based networks are wastefu_ of available bandwidth and lack flexibility.
Packet-based n~L~.JL;ks UVt~I~ many o~ t~e disadvantagefi of circuit-based networks. In a packet-based network, the data are assembled into packets cnnt;~ining one or more address fields which dePine the contOEt of a packet, such as protocol type and relative r~AJr. i t; nn A of other ~ields : - ~Ar7 in the packet . LAN
bridges and routers use the inf~r~~t;An in the packet to forward it to the destin~t;~A~n~ 7 In a packet-based network, a packet must be parsed as it flows thr.;ugh the network. Parsing is the process of extracting and analyzing the inf ormation, such as source and destinAt;~Aln address and net layer protocol, ~AAnt;~;n_d in the packets.
In known networks, packet parsing is generally ~erformed with a miuLu~1LucdssoL, which provides fl ~ ih; l; ty in h~n~l7 ing difPerent packet types and can be upgraded to handle new packet types as they are defined.
Content ~ddressable Memory (CAM) is commonly used for ~ wo 95/18497 2 1 7 9 6 1 3 PCT~CA94/00695 hardware assistance to speed up searchefi through a li~;t of known addresses This is a tedious task C~Ms are also relatively expensive and limited in size and aV~ h; l i ty .
General purpose processor arrh;tect~lreS are not '~
spe~r;f;cA11y directed toward the types of operations required in packet parsing and so they tend to be inefficient. 'rO meet performance requirements, a fast but expensive processor based solution can be implemented. In the highest performance systems, hardware 5011.t;nn~ 2re implemented to increase speed, but at the cost of flp~;hil ity.
An object of the invention is to provide a fast, hut ; nG~ns~ive solutic~n to the problem of packet-parsing in packet-based networks.
According to the present invention there is provided an al~ for parsing packets in a packet-based data tr;qn~ 2gion network, said packets ;nrl1~ n~ packet headers divided into fields having values representing infnr~-t; nn pertaining to the packet, said aL., ,~ "
comprising input means for receiving fields from said packet headers of inrn~;n~ packets, means for storing infnrm~tinn related to possible values of said fields, and means for retrieving said stored infnr~-t;nn al.~Lu~liate to a received field value, characterized in that said retrieving means cnn~rr;~ a look-up engine including at least one memory organized in a hierarchical tree structure, and controller means for controlling the operation of said at least one memory.

c ' WO95/18497 ' 2 ~ 7 96 1 3 pCI~/C~94~00695 The memory and retrieving means constitute a look-up engine, which is the central resource rnnt~ining all information necessary for forwarding ~lPri~:inn1::
In a r~rkPt;7Prl data transmission rnnfnrminj to 5 IEEE802 standards, the packets have a MAC (medium access control) header ront~;n;ng information about the dest;n~t;nn and source addresses and the net layer protocol The invention permits packet switching to be achieved in a bridge-router, for example an Ethernët to ATM bridge-router, at a rate of about 178,000 packets per second using 64 byte minimum ~thP~Pt packets. This means that the MAC headers are interpreted once every 5 . 6 micro seconds .
The look-up engine preferably employs table look-ups 15 using nibble ;n~P~;nj on variable portions of the packet, such as MAC and network layer addresses, and bit pattern r-ocoJn;t;on on fixed portions for network layer protocol determination .
Each look-up table is organized into a hPl-~rlPrir^-l 20 search tree. Each search tree begins with a 16 word root table. The search key (e.g. MAC address) is divided into nibbles which are used as indices to subsequent tables.
The 16 bit entry in the table is cnn~tPn~tPcl with the next 4 bit nibble to form the 20 bit address of the next 25 16 word table. The final leaf entries point to the des ired inf n~; l t; nn Bit pattern recognition is achieved ~y a microcode instruction set. The microcode engine has the ability to compare fields in a packet to ~ JlU~L ' constants and -~

~ W095/18497 2 ~ 7 9 ~ 1 3 PCT/CA94100695 perform branches and index increments in a single instruction cycle typically. The microcode engine has complete control over the Rearch procedure, so it can be tailored to specific look-up functions. New microcode is 5 downloaded as new ~unctIons are re~uired.
The look-up engine can perform up to two tree searches in parallel with microcode P~Pr~lt; ~m . Look-up time is quick because the microcode determines the packet ' s network layer f ormat while the source and~-10 destination addresses are being searched in r~r~l 1 P1 . Theresults of the source and dest;n~tion look-ups and the protocol ~lPtPrm;n~t;nn arrive at roughly the same time, at which point the next level of ~Pr~; ~; nnR is made .
The look-up engine also performs protocol filtering 15 between areas The system allows devices to be grouped arbitrarily into areas on a per protocol basis and def ines f i l tering rules among these areas . The look-up engine keeps track of each station ' 8 area f or each of its protocols. The source and dest;n~t; nn areas are cross-20 indexed in a search tree, which is used to find thefiltering rule between the two areas. Separate filtering rules are defined for bridging and network layer forwarding; hr;fl~;n~ is normally allowed within an area while network layer forwarding is selectively allowed 25 between areas.
The parsing controller typically has a pointer to the current field in the packet being Pl-i-'~;nP~, The controller moves this pointer to the next field in the c W095/18497 2 1 7 9 6 1 3 PCT/C~94/1~695 packet after all decisions based on the current field are made .
. At each decision point on a tree, the current field is ~ d to a known value or range If the C~;lr; cnn 5 yields a true condition, the controller moves to the next r;f:;nn point by moving the current field pointer Otherwise the field pointer is left alone and controller hr~nrh~s: to new code to compare the current f ield to a different value or range. This process is repeated until 10 a final flf~ri c; nn iS made.
Moving to the next d~ri ~i on point reguires several discrete steps in a general purpose processor. Unlike a general purpose processor, which has the disadvantage that it only has a single memory bus f or both instruction 15 and data f etches, the Look-up engine controller has separate buses f or instruction and data and typically performs one ~l~r; f:; nn per step ~ast ~ r; cinn~ are made prF:~:;hle by a special set of instructions which both conditionally move the pointer and conditionally branch

2 '' to new code in a single step The comparisons and pointer v ~ can be ~yte or word wide, according to the current field' s size.
The look-up engine implements other optimized instructions which perform bit level logical comparisons 25 and conditional ~r:mrh~.c within the same cycle as well as other instructions tailored to retrieving data from nibble-indexed data structures The look-up engine is pref erably divided into the following sections: --~ WO 9~i/18497 PCI~/CA94/00695 a) one or more nibble tree address look-up engines (ALE) b) one microcode engine Bach ALE is used to search for addresses in a tree structure in its own large bank of memory. The result o~
5 a search is a pointer to pertinent inform~t; nn about the address. An ALE is assigned to dest;";lt;nn addresses (DALE) and source addresses (SALE). The ALEs operate in~Pr~n-lPntly o~ each other.
The microcode engine is used to ncnr~;~Ate the 10 search. It invokes the SAL~ and DALE to search fq;~ the source and dest;n~tinn addresses respectively and ~nnt;nllP~: on to parse the rPm~;nrl~r of the packet using an application-specific instruction set to rl~otP~n;~p the protocol The SALE, DAL~ and microcode engine can execute in parallel and arrive at their corresponding results at roughly the same time The rnicrocode engine then uses the SALE and DALE results along with its own to arrive at the forwarding ~1P~ ; nn The advantage o~ using RaM over a CAM is P~lnrl~3h; l; ty and cost . Increasing R~M is a trivial and inexpensive task compared to increasing CAM size.
The advantage of the microcode engine over a general purpose processor is that an ASIC; ~1 ~t;nn of the function is much less expensive and less complex than a processor-~ased design with all the overhead (RAM, ROM) associated with it.

2~796~3 _ j _ The invention also related to a method of parsing packets in a packet-~ased data tr~nr-ni r~ion network, said packets inrl~ ins packe_ leaders divided into fields having values representirg information pertaining to the packet, comprising fitoring information related to possible values of said fields, receiving fields from said packet headers of incoming packets, and retrieving said stored infnrr--tion appropriate to a received field value, characterized in that said infr~r~~~tir~n is stored in a memory organized in a hierarchical tree structure The invention will now be described in more detail, by way of example only, with reference to the _ ying drawings, in which:-Figure 1 is an example of a r~c layer header of a lS typical packet;
Figure 2 shows the data paths in a typical bridge-router between Ethernet LaN and ATM ne~h~.lhi;
Figure 3 is a block diagram of a first clrhorl;m~nt of a look-up engine in accordance with the invention;
Figure 4 is a block diagram of a look-up engine controller for the look-up engine shown in Figure 3;
Figure 5 is a block diagram of a second ~mhrrl;mf~nt of a look-up engine in accordance with the invention;
Figure 6 is a block diagram of a look-up engine controller for the look-up engine shown in Figure S;
Figure 7 is a map of look-up engine Address Look-up engine (AIE) r-~;
Figure 8 is a diagram illustrating search tree operation in an ALE;

i ~' W095/18497 , 2 1 7a 6 1 3 pCllC~94100695 Figure 9 shows one exa~nple o~ a MAC search tree;
Figure 10 shows the effect o~ the organizationally unique ;r~Gnt;f;~ of the MAC addresses on the size of the -~
search tree;
Figure 11 shows the source address look-up engine table;
Figure 12 shows the dest;n~t;nn address look-up table; .r Figure 13 illustrates the look-up engine addressiny modes;
Figure 14 shows a station information block;
Figure 15 shows a port inf nrr t i nr1 block;
Figure 16 shows an exa~ple of protocol liltering;
Figure 17 shows a look-up engine controller Instructlon State Machine;
Figure 18 shows a typical fast timing diag~am; and Figure 19 shows a typical SIB RAM access instruction timing diagram.
A typical look-up engine (LUE) in accordance with the invention is designed to be used in a twelve-port wire speed Ethernet to ATM bridge-router capable of switching about 178, 000 packets per second using 64 byte minimum Ethernet packets This packet rate corresponds to a look-up request occurring every 5 . 6 llsecs . The LUE is used each time a packet is received of f the Bthernet or the ATM network. The type of infnrr-t;nn that -he en~ine ~ W0 95118497 2 1 7 9 6, PCT/CA94J00695 _ g _ provides depends on the diroction of packet flow and the type of packet The look-up engine provides all the inf ormation needed to find the path to each known dest;n~t;on, as well as default information in the case of unknown dest;n~t;r,n~, Figure 1 shows a typical MAC layer header for~nat for a packet that can be parsed with the aid of the look-up engine in accordance with the invention. The header comprises dest;n~t;r~n and source address fields lD~, 101, a network layer protocol type field 102, and network layer destin~tirm and source address fields 103, 104.
Figure 1 also illustrates how the header is parsed in accordance with the invention. All fields except 102 are parsed using a tree search The Net Layer Protocol Type field 102 is parsed hy using microcode comparisons in the microcode engine to be ~Rrr; hPd On a bridge-router, eac}l port is represented by a corrP~pr,n-l;n~ bit in a PortSet (Ports 0-11), which is a 16 }~it value that has local significance only The Control Processor and A~M are each assigned a port The following definitions are special cases of a PortSet:
SinglePortSet a PortSet with a single bit set.
~ostPortSet a SinglePortSet uLLt a~uull~ling to the Control Processor MyPortSet 2L SinglePortSet ~uL~eD~ullding to the source port of this packet.
_ .

~ W095/18497 ' 2.1 7 9 ~ 1 3 PCT/C~94/006g5 -- lQ -NullPortSet a PortSet of no ports.
A t'r)nn~r~t;t~n ~ nt;~ ^ (CI), which is a 16 bit value with local signi~icance only, is used to map 5 connectiolls into VPI/VCI values.
The followiug definitions are special cases of CI:
Mesh_CI
a CI ~JLL~_~Jul~9ing to a path towards the ~lrcrin~tinn end3tation ' 8 Bridge-router . = ~
0 Null CI
a CI connected to nothing. It is returned when the destination is atrached to the local Bridge-router or if the rnnn~.rt~nn is not allowed RS CI
a CI ~uLL~b~ul~ling to a path to the ~oute Server.
ABS_CI ~ ~
a CI uLL~_~ullding to a path to the ~ddress~Broadcast Server.
MaC layer addresses are globally urli~aue 48 bit values, except in some protocols such as DECNet, where they may not be globally unique.
Unicast DA
a MAC layer rl~oct; n~t i nn address of an end-station .
Router DA
a MAC layer destination address of the Route Server. An end-station sends packets to the Route Server when it cannot send to the d~ctin~tinn directly at the MAC layer.
Broadcast DA
the broadcast MAC layer address (all ones~ which is recei~ed by all end--ctations~ It c~nnot be a source address.

~ WO 9S/18497 ' ' ~) 1 7 9~ 6 1 3 PCT/CA94/Oa695 ~ulticast_DA
~ multicast MAC ~ayer address lgroup bit set) which is received by end-stations that recoonize that multicast address.
Network layer (NL~ addresses are network protocol 5 dependent They are generally aivided into Network, Subnet, and Node portions, although not all protocols have all three present The Network Layer Address Field Sizes (in bits) are sulr~narized in the table below Protocol l`otal Size Network Subnet Node IP 32 8/16/24 variable variable IPX 80 n/a 32 48 (MAC address ) Apple~alk 24 n/a 16 8 DECNet 64 16 38 10 (reserved) (32 -31IOI~D ' ) (6 = subnet) The look-up engine ha~dles unicast network layer addresses .

nhen the look-up engine is used in a bridge - router providing an ;ntFrfAc~o between an ~th~rnot and ATM
15 network, packets coming from the Brh~orn~ot side are fed into the Look-up Bngine. The result of the look-up has the form: ~

Input -~ Command, CI, PortSet where Input is derived from the first few bytes of the 20 packet and Command is an opcode to the AXE (Transfer engine) The Quad M~C status word distinguishes between router MAC, broadcast and multicast MACs.

~ ` WO 95118497 ` ~ 2 1 7 9 6 ~ 3 PC~/CAg4Jo0695 Rri ~1~; ng occurs when the destination address is a unicast address othEr than the Route Server address.
Rr;~;n~ is allowed between two endstations in the same area f or a given protocol .
Both source and destination MAC addresses must be known before automatic hr;c;l~in~/filtering is performed;
otherwise, the packet is sent to the Route Server for:
SA (Source Address) v~ ;fl;it;nn if the SA has never been seen qrPAkin~ a ~iven protocol -~
DA (Dest;n~t;nn Address) resolutio~ if the DA was not f ound in the local MAC cache ~
The Bridge command instructs the AXE (Transfer Engine) to use RFC-1483 bridge encapsulation. BridgeProp command instructs the AXE to use bridge-router 1~ Pnm~rq~ t;on (include source PortSet in Pn~rlslll~tinn) l~nknown SA -~ BridgeProp, Null_CI, HostPortSet, MyPortSet Unknown SA - send to HP for Spanning ~rree processing !HP will decide whether to ~orward it to ABS for learning, depending on Spisnning ~ree state Unicast DA -> Bridge, Mesh_CI, NullPortSet DA in the same area on a different Bridge-router Unicast DA -~: Prldge, Nuli_CI, NullPortSet DA not in the same area (reject) Protocol not allowed to bridge-router 2S DA on the same port Unicast_DA -~ Bridge, Null_CI, SingIePortSet DA in the same area on the same Bridge-rollter l~ut on a di~erent port Unknown_D~ -~ ~ BridgeProp, ABS CI, NullPortSet, MyPortSet

3 0 DA not found in the ta`ole - send to ABS for 100d proce~sing WO 95/18497 ' ' PCT/CA94/00695 Broadcast DA -:. 3ridgePro~, A35_CI, I~lllPortSet, MyPortSet Broadcast D~ - ~end to Control Proces60r rOr ~roadcast processing Multicast_DA -~ 3ridgeProp, A3S CI, NullPortSet, MyPortSet Multicast DA - Send to ABS for multlcast processing Multicast_DA -> 3ridgeProp, Xull CI, HostPortSet, MyPortSet Multicast DA is of interest to HP (eg Spanning Tree~
HP will decide whether to forward it to ~3S for multicast processillg Routing occurs when the destin~t;on address is the unicast Route Server address. Filtering rules betw~een areas are ~l;r;tly defined per protocol. The per protocol source area is an attribute of the source MAC
address and the per protocol destination area is an 15 attribute of the desr;nilt;r~n ~L address.
Both source MAC and desr;n~tic~n NL addresses must be known before network layer forwarding can occur.
The packet will be bridged to the Route Server if any o~ the following are true:
2 0 IP options are present Protocol is unknown The packet will be dropped if any o~ the following are true:
Source area is not allowed to send to Dest;n~t;rn area 25 for this protocol Source NI- address is invalid (eg. any IP broadcast address ) rk~ lm~ is invalid Time -To-Live f ield expires ~' WO95/18497 ~ , 2 7~6 1 3 pCT/C~94/00695 Unicast~ > Route, ~5esh CI, ~lullPortSet I~L node on a di~l~erent bridge-router Vnicast_NLDA -> Route, Null CI, SinglePortSet ~ ~ node on the same bridge-router (could be same port~
5 Snknown NLDA -> Bridge, RS CI, NullPortSet unknown NL node - send to Route Server IJnknown Protocol -> Bridge, RS_CI, ~ullPortSet ~ protocol unknown, or packet with options Figure 2 shows the data paths in a typical brirdge-10 router. Control processor 16 has control over the formatting of packets it sends and receives. I~ t~re control processor 16 wants look-up engine 17 to per~orm a look-up, it formats the packet in the same way as Quad Mac 1~; otherwise it sends it as a raw packet, which does 15 not require a lengthy look-up. The control processor pro~to~r;n~C the des~;n~t;-~n by providing a CI
(Connection Td~nt; f; ~r) and an output Portset as part of the data stream. A bit in the Quad MAC status word indicates a raw packet and the look-up engine simply 20 retrieves the CI a~d Portset as part of the data stream.
A bit in the Quad MAC status word indicates a raw packet and the look-up engine simply retrieves the CI and Portset from the data stream and feeds it to the AXE
(Tr~n~fGr ~ngine) through the result FIF0. I'he Control 25 processor is responsible for correctly formatting the required ~n-~rS~ ricn As shown in Figure 2, packets coming from the ATM
side are fed into the look-up engine. The look-up engi~e accepts an RFC-1483 encapsulated packet and determines ~` wogs/18497 2 1 7~ 1 3 PCT/CA94/006ss whether to look ~t a MAC or ~ address. The result of the look-up will have the f orm:

Input -, PortSet Filtering is not performed in this direction. It is 5 assumed that the all filtering is done at the ingress side. It is also assumed that the dest;n~tinn endstation is known to be ~tt~rh~ to the recei~ing Bridge-router, so unicast packets with unknown destin~t;rJn addresses are dropped .

Flood and broadcast packets are ~nrArSl17 ~t-~ in a special f ormat which includes an e~eplicit output PortSet IJnicest_DA -, SinglePortSet DA on this Bridge-router ~nknown DA -3 NullPortSet DA not in the te~le (drop~ - this situation should not occur IJnic~st_r~DA -, SinslePortSet NLDA on thiq sridge-router ~nknown_~LDA -, NullPortSet NLDA not in the taole Idrop) - this situation should not 2 0 occur sroadcast DA,PortSet -~ PortSet Proprietary sroadcast reouest received ~rom RS

Multicast DA,PortSet -, PortSet Proprietary r~ulticast request received from RS

25 Unknown DA,PortSet -, PortSet Proprietary ~lood request received from RS

~ urning now to Figure 3, the look-up engine consists of three f~lnrtirln~l blocks, namely a dest;n~tirn address look-up engine (DAIE) 1, a source address look-up engine 30 (SALE) 2, and a look-up engine controller (~EC) 3, which wo 9~JI8497 2 1 7 ~ 6 1 3 PCTICA94100698 ;nrlll~lP5 a microcode ram 4. DALE 1 ;nrlllrlPc a destination address look-up controller 5 and DALE RAM 6. SALE 2 ; nrl ~ PP: a 50urce address look-up controller 7 and SALE
RaM 8. The input to the look-up engine is through a fast 5 16-bit wide I/F RAM 9 receiving input from the AXE
(Transfer Engine) and re-asfiembler. me output from the look-up engine is through word-wide FIFOs 11, 12.
One: ~ ' r^^nt of look-up engine controller ILEC~ 3 is shown in more detail in Figure 4. miS comprises 10 (Station Inf~rr~t;r,n Block~ SIB ram 20, interface ram 21, and microcode ram 22. The SIB ram 20 is connected to look-up pointers 23. TntPrf~rP ram 21 is connected to data register 25 and index pointers 26 connected to ALU
(Arithmetic Logic Unit) 27. Microcode ram 22 is c 15 to instruction register 28.
The look-up Engine controller 3 is a microcoded engine tailored for efficient bit pattern comparisons through a packet . It r ; ratPf: with the Source Address Look-up Engine 2~and the Dest;n~tirn Address Look-up 20 Engine 1, which both act as co-processors to the LEC 3.
The look-up engine snoops on the receive and transmit data buses and deposits the header portion of the packet into the I/F RAM 9. me look-up response is sent to the c~ uL,liate FIF0 11, 12 Figures 5 show an alternative embodiment of the loop-up engine ana controller. In Figure 5, the LEC 3 includes a 64 x 16 I/F (TntPrf~rP~ ram 41 connected to FIFO's 42, 43 (First-in, First-out memories~ respectively ~ wo 95/18497 ' l 7 9 6 1 3 PCT/CA94/00695 connected to latches 44, 45 receiving AXE (Transfer Engine) and reassembler input Referring now to Figure 6, the LEC 3 also contains several registers, which will now be described Register 5 select instructions are provided for the register banks ( XP0 - 7, LP0 - 7 ) .
Index Pointer register ~IP) 50 is a byte index into the I/F RAM 21 Under normal opPn~ti nn, the index pointer register 50 points to the current packet field 10 being nP~l in the I/F RAM 21 but it can be us d whenever random access to the I/F R~M 21 is required The IP 50 can be mn~;f;P~ in one of the following ways:
1) loaded by the LOADIP instruction (eg to point to the beginning of the packet ) 15 2) in-_L ~Pd by 1 (byte compare~ or 2 (word compare) if a branch condition is not met.
3) in~:L~ ed by 2 by a MOVE (IP) + type instruction.
Data Register 51 cnnt~;n~ the 16 bit value read from ~/F R~M 21 using the current IP The DR 51 acts like a 20 one word cache; the LEC keeps its rnnfPnt~ valid at all times Program Counter 52 points to the current microcode instruction It is incremented by one if a branch condition is true, otherwise the ~ r~ ~ t field is 25 added to it The Lookup Pointers (LP0-7) 23 are 16 bit registers which contain pointers to the SIB RAM 20. The LPs are used to store pointers whenever milestones are reached in , ~' WO9511849'7 ~ 1 7 9 6 1 3 PCT/CA94/00695 -- ~ 8 --a search, One LP will typically point to a source SIB
and another will point to a dest;nAtinn SIB, The LP
provides the upper 16 bits o the pointer; the lower 4 bits are provided by the microcode word for in~;n~ into 5 a given S IB, The LPs are also used to prime the SALE and DALE
with their respective root pointers, X,Y Registers 53, 54 are general purpose registers where logic ---n;rll At; nn~:: can be made (AND, OR, XOR), 10 They are used for setting and dearing bits in cer~ain words in the SIB RAM ~eg, Age bit) and to test for certain bits (eg. status bits), The X Register 53 can be selected as Operand A to the ~ogic Unit while the Y
Register can be selected as Operand B.
The BYZ and BYNZ instructions conditionally branch on Y=0 and Y~,O respectively, The Y Register 5g is the only register source for moves to the result FIFOs.
The X Register 53 can be saved to or restored f rom 20 X' Registers (X'0-X'7) 55. The mnemonic sy~bol for the currently selected X' register is XP.
The S Register 56 is a pipelining stage between SIB
RAM 20 and the Logic Unit. It ~i _l;f;.~q read access from SIB R~M 20 by relaxing prnra~At;~n delay 25 reSIuirements from SIB RAM 20 valid to register setup. It provides the added advantage of essentially caching the most recent SI33 RAM access for repeated use. It is loaded by the GET Index (LP) instruction.

~ WO 95/18497 ' 2 1 7 9 6 1 3 pcr/cAs4/oo6ss ~ s in Figure 3, the LEC 3 controls the operation of the look-up engire. ~11 look-up re~r~uests pass through the LEC 3, which in turn activates the SAIE 2 and the DALE 5 as required. The LEC 3 is microcode based, running from a 5 32-bit wide microcode RAM. The inst~ct;nn set consists mainly of compare-and-branch instructioIls, which can be used to find sp~c;f;r bit pAttGrnC or to check for valid ranges in packet fields. Special I/O instr~lct;nn~ give the LEC random read access to the interface RAM.
The LEC has access to 3 memory systems: the ;ntPrf~re RAM 9, the SIB Ra~ 20 and the Microcode RAM 22.
The ;nt~fArr RAM 9 is used to feed packet data into the LEC 3. The look-up eIlgine hosts dump packet headers into this RAM through snoop FIFOs 42, 43. This R~M is 15 only Acc~cihl e through the snooped buses The SIB RAM 20 is used to hold ;ncnrr~tic~n for each known end-station The LEC 3 can Arh;tra~ily retrieve data from this RA~I and transfer it to one of the response FIFOs ll, 12 or to ;nt~rnAl registers for ~~n;rllAt;r,n 20 and rh.ork;ng ~ligh speed RAM is also used to minimize the data retrieval time. The size of the SB 3W1 20 is dependent on the maximum nun~er of rr~rhAhl ~ end-stations. For a limit of 8,000 end-stations, the SB RAM
size is 256K bytes . This R~M is Acr~ ;hl e directly to 25 the Control Processor f or updates .
The Microcode RAM 22 is ~ ; rAt~ to the LEC 3 . It cnntA;n~ the 32 bit microcode instructions. The LE:C 3 has read-only access to this high speed RAM normally, but it ~ WO 9~/18497 ` 2 1 7 9 6 1 3 PCTIC~94100695 i8 mapped directly to the Control Processor' s memory space at startup f or microcode downloading .
Variahle fields of a packet, such as addresses, are searched in one of m. any search trees in the ALEs 1, 2, 5 ~Figure ~), which are nibble index m-~-h;n~. Each ALE 1, 2 has its own search tree RAM 6, 8 (Figure 7), which is typically high density but low speed. This MM is divided into 32 byte blocks which can either be Index Arrays or Information Blocks The searches in the AL13s 1, 2 are`based stritly on the root pointer, the search key and search key length it is given. A look at Lhe look-up engine memory map ~Figure 7) as viewed from the ALEs shows how the ch~ni ~m ~orks All search trees in a given ALE 6, B reside in the 15 upper haif of its memory. ~he 16-bit root pointer given to the ALE will have the most si~n; F; ~ nt bit set. The search key (eg. MAC address) is divided into nibbles The first nibble is c~n~t&n~te~l with the root pointer to get an index into the root pointer array. The word at this 20 location is retrieved. If the MSB (Most Significant Bit) (P Bit) is set, the ne~Lt nibble is c~n~-~t~n~t~d with the retrieved word to form the next pointer. If the P Bit is clear, the search is 1 ;n;~::h~d, The final result is given to the LEC, which uses it either as a pointer into the 25 SB RAM, or as data, depending on the context of the search A zero value is reserved as a null pointer value.
Figure 8 illustrates search tree operation.
The search key length limits the number of itor~ti-~n~ to a known m=~; The control processor .

~ WO 95118497 ' 2 1 7 '~ 6 1 3 PCT/CA94/00695 manipulating the search tree structure may choose to shorten the search by putting data with a zero P bit at any point in the tree ~Don't Care~ fields are also achievable by 5 ~s11r1;~?tin~ appropriate pointers within the same pointer array. Search trees are r~int~;rpd by the Control Processor, which has direct accesfi to the SALE and DAI,E
RAMS 6, 8.
Figure 9 is a diagram illustrating a MAC search tree 10 example. The main purpose o~ the ALE RaMs 6, 8 is_to hold MAC layer addresses. The size of the RAM required for a MAC addregs tree depends on the statistical distr;h~1ti~1n of the addresses. The absolute worst case is given by the following formula:
N=~ min(16~
where X is the number of addresses L is the number of nibbles in the address N is the number of pointer arrays The amount of memory re~uired, given 32-byte pointer 20 arrays, is 32N. The number obtained from this formula can be quite huge, PRpP~ 7 1y for MAC addresses, but some r~ t j rm ~ l i 7 ~ t i nn q can be made .
In the case of ~C addresses, the f irst 6 nibbles of the address is the Or~n;~t;nn~lly Unique TrlPntif;Pr 25 (OUI), which is common to ~tllPrnpt cards from the same r~nllf:~ctllrer It can be assumed that a particular system will only have a small nur~ber of dif ferent OUIs .

~ wo 95/18497 2 1 7 S 6 1 3 PCT/C~94~006g~

The formula for MACs then becomes:

N=~mm(16'~~,M~+~ ~min(16i~7,X~) ;~1 j=1 ~=7 where M is the num~er of different OlJIs X~ is the number of stations in OUI~
~ m; n~ that the addresses are distributed evenly over all OUIs, N=~min(16i~1,M)+M~min(16'~7,--) j 1 ,=7 M
The effect of OUI on Search Tree Size is shown in Figure l0.
Similar r~t;~n~l;7~t;-~n~ can be made with IP and other network layer protocol addresses. An IP network will not have very many subnets and even fewer network numbers .
Although the SAI,E 2 typically holds locally attached source MAC addresses and the DALE 1 typically holds dest;n~t;-7n MAC P~ S~, either AI,E l, 2 is capable of holding any arbitrary search tree Network layer addresses, intra-area filters, and user-defined ~ac protocol types can all be stored in search trees. The ~ r; ~ n to put a search tree in either SALE or DALE is implementation ~rPn~l.=nt; it relies on what searches can be done in parallel for maximum speed.
The principal function of the SALE 2 is to keep track of the M~C addresses of all stations that are locally ~tt~--h~ to the bridge-router. Typically one station will be attached to a ~ridge-router port, bu~ --~ ~ WO9~/18497 2 1 7 9 6 1 3 PCTIC~94/00695 connections to tr~it1~n~l hubs, repeaters and bridge-routers are allowed, so mor~ source addresses will be ~n ~o~7n t F~red IJsing the formula for R~M size above, typical RAM
5 cal~ t;~n~ for the source address trees are as follows:
er of O~IS Num~er of Total Bytes Stations 400 65, 440 2 500 65, 184 500 77, 984 800 116,284 1, 000 131,552 The number of source stations is limited to some fraction of the total allowable stations. The limit is imposed here because the SALE will most likely hold many 10 of the other search trees leg. per protocol NL address search trees, intra-area filters).
Whenever a new source address is ~nrollnt~ed, the SALE 1 will not find it in the r~AC source address search tree. The LEC 3 realizes the fact and sends it to the 15 Control Processor The new source address is inserted into the search tree once validation is received f rom the Route Server.
Whenever a previously learned address is re-encountered, the Age entry in the SIB 20 is refreshed by 20 the LEC 3. The control processor clears the Age entry of all source addresses every aging period. The entry is removed when the age limit is ~r~d~d~
The source aadress look-up engine table is shown in Pigure 11.

, ~ ' WO95118497 . 2 1 7 9 61 3 PCT/CA94/0o69!
- 2~ --The DALE 1 keeps track of all stations that are directly reachable from the ~ridge-router, including those that are locally attached The DA~E search trees are rnncjdf~hly larger because they contain ~C
5 addre8ses of up to 8, 000 stations Typical memDry si~es for MAC dest;n~t;nr address search trees would be:
Number of Number of Total Bytes OUIs Stations 8,000 856,992 8, 000 945, 824 8, 000 1, 034, 464 A station ' s MAC address will appear in the MAC
10 search tree if the station is reachable through MAC
hr; ~ls; n~ . A station ' s network layer address will appear in the corr~on~;n~ network layer search tree i~ it is reachable through routing.
The des~;n~t;nn address look-up engine MAC ta~le is 15 shown in Figure 12 IP masking may be re~uired if a particular port is known to have a router ~tt~hPd to it. Masking is achieved by ~nn~ r;n~ the IP network layer search tree in such a way that the node portion of the address is 20 treated as Don't Care bits and the corrl~cpnn~l;n~ pointers point to the same Next Index Array.
The SALE and DA~E RAMs 8, 6 are divided up intD 16 word blocks . These RAMs are acn~F~; hl ~ only to the corresponding AI,E and the Control Processor The8e R~s ' WO95118497 ' . 2 1 7 6 1 3 PCTICA94100695 contain mostly pointer arrays organized in several search trees The SIB RAM 20 is divided into 16 word blocks which can be treated as records with 16 f~ields Each block S typically r~ntA;n~ inf~ t;nn about an endstation This RaM is accessible only to the LEC and the CP.
The LEC 3 uses the lookup pointer (LP~ as a base pointer into a SIB 20 The .~nnt~nt~ o~ the LP is obtained either from the result of a SALE 2 or DALE 1 10 search to access end-station ;nfn~-t;nn, or from a constant loaded in by the microcode to access mis~ llAn~m-~ inf~lrr-t;~1n (eg. port inforr-t;on) ~rhe LP
provides the upper sixteen bits and the microcode word provides the lowest f our bits of the SIB R~M address .
The lookup Engine addressing scheme is shown in Figure 13.
The SIB RAM 20 (Figure 14) gf~n~rAl~y cnntA;n~
information about the location of an endstation and how to reach i~ For example, the PortSet f ield may keep 20 track of the port that the endstation is AttA~hl 51 to (if it is locally attached) and the cnnnF~ct; on index refers to a VPI/VCI pipe to the endstation (if it is remotely attached) Other fields are freely ~f;nAhle for otker things such as protocol filters, source and dest;nAt;nn 25 encapsulation types and quality-of-service parameters, as the need arises A variant of the SIB is the Port Infn~t; nn Block (PIB) (Figure 15) PIBs contain information about a particular port Certain protocols have attr;hut~ -_ _ _ _ _ _ _ _ _ _ , .. ....... .. . ... ..

. ~ wo 95/18497 2 1 7 9 6 1 3 pCT/CA94/006g5 ;~tt2~rhP~7 to the port itsel f, rather than the endstations An endstation ;nhpritq the characteristics assigned to the port to which it is attached The definition of the SI~3 is flexible; the only 5 require~m.ent is that the data be easily digestible by the LUE instruction set The field type can be a single bit, a nibble, a byte, or a whole word.
In Figure l~, the CI ~nnnPction T~lPnt;~;Pr) field is a reference to an ATM connection to the endstation if 10 it is remotely ~tt~rhP~l. This field is zero for a.
locally attached endstation.
The PortSet field is used both for ~iPrprm;n;ng the dest;n~t;on port of a locally attached endstation, and for determining whether a source Pn~1Rt~t; nn has moved.
15 In one Npwhr; ~e-router ~ Lhb system, a moved endstation must go through a rP~m; cc; on procedure to preserve the ;nte~r;ty of the network. This field is zero for a remotely ~tt~rhpcl endstation The MAC IndOE is a reference to the 6-byte MAC layer 20 address of the endstation This field is used for network layer forwarded packets, which have the ~AC layer PnrArc~ t;nn removed The MAC layer address is re-att~rhP-l when a packet is re-Pnr~rs~ tPd before retr~nFm; cc; nn out an ~thPrnPt port The encapsulation 25 flags determine the MaC re-encapsulation format The Proto Area and Proto Dest Area fields are used for filtering opPr~t;nnc. 13ecause the Newbridge-router system Pc,qPnt;~11y rem~oves the traditional physical constraints on a network topology, the area concept ~ WO 9~/18497 2 l 7 9 6 1 3 pCT~CA9~/00695 logically re-imposes the constraints to allow existing protocols to function properly. Fil~ering rules defined between areas ~'tP~mi nP whether two endstations are logically allowed to coTnmunicate with each other using a 5 specific protocol.
The Proto Area field is a pointer to a filtering rule tree, which is similar in structure to the address trees, The Dest Area field is a search key into the tree. The result of the search is a bitfield in which 10 each protocol is assigned one bit. Communications is allowed if the ~uLL~ "".fling bit is set.
Figure 16 shows a filteri~g rule tree The microcode for the LEC 3 will now be described, The LEC microcode is divided into four main fields as 15 shown in the table below . The usage of each f ield is florPnfl~nt on the instruction group.

Inct Ins~ruction r~; crl: Parameter Group The iLStruCtiOn group f ield consists of instructions grouped according to similarity of function. A maximum 20 of eight instruction groups can be defined.
The Instruction field definition is flFrGnfl~nt on Instruction Group.
In branch instructions, the D;~rl~c ' field is added to the PC if the branch condition is true. This 25 field is used by non-branch instructions for other purposes . - -. ~ WO 9S/18497 2 1 7 9 6 1 3 PCT/CA94~00695 The Parameter field is a 16 bit value used for comparison, as an operand, or as an index, dependent on the instruction. =
The fllnrf;smq of the groups are 8et out in the 5 following table.
Group O Index Poin~er/Bank Select Instructions These ~n~trllrtinnc ---nip~ t~ the IP and the register bank select register .
Group 1 F~st Move Instructions _ These instructions move data between I~F R~M and in~ernal registers .
Group 2 ~'nnrlit1nni~1 Branch Tnetrl1~tinne These instructions brzmch when a given condition is met. They can optionally increment the IP.
Group 3 X Register Branch Instructions These instructions branch on an X
Register logic comparison.
Group 4 Not lIsed Group 5 Slow Move Instructions These instructions generally involve the SIB RaM bus. The accesY time to the SIB RAM is longer because of address setup time ~nnc~ri~tinne and because the CP may be accessing it at the same time. Access to the Resul~
FIFOs are included here.
Group 6 Not U9ed Group 7 Misc Instructions These instructions invoke special funct ions .
The following table ~lPqrr;hP~ the use of each of the f ields .
,:

^ WO95/1~497 2 1 7 9 6 ~ 3 PCT/CA94/00695 Grp 31-29 23-26 ¦ 25-24 1 23-21 1 20-1 1 1 -16 15-0 0 0 D 0 0 0 0 Cper. 1 1 1 1 1 0 BSel Immediate Value (15-0) Register Select (15-4 0 0 1 Dest. Size LSel ASel BSel Immediate Value (15-0 llegister Select (15-4 or Index (3-: Cond. Size Disp. ~8~ Comparand Cond. 0 0 LSel Disp (5~ Comparand Dest. Size LSel ~Sel BSel Immediate Value (15-0 Register Select (15-4 or Index (3-Qi 7 1 1 1 0 0 0 Si~e 0 0 0 0 0 0 0 0 codes 'when LLgel . lC
Condition 000 - (IP~ ~ Comparand 001 - ~IP~ < Comparand 5 010 - (IP~ > Comparand 011 - 7'rue 100 - Extended Condition = 7`rue 101 - Extended f'nn~lir;nn ~ False 111 - Y <> O
Dest - D~t i n:~t 1 nn 000 - currently active FIFO
15 001 - X l~egister 010 - Lookup Engine Address RAM
Oll - Group 5: S ~egister otherwise: l~one 100 - Y Register 20 101 - Index(LP~ (SIB
110 - XP Register 111 - Lookup Pointer Operation - IP/Register Select operation 00 - ~egister Select 10 - Load Size - IP increment size 0 0 - no increment 01 - byte ~+1 10 - word (+2~
n;qrl~ (8 bits) WO95/18497 2179613 pCT/CA94/00695 0000000l - next in3truction 00000000 - 6ame instruc~ion DicrlA. (5 bits~
0000l - next i nctr~ tinn 00000 - same instruction LSel - Logic IJnit Select ..

00l - A OR B
0l0 - A A~ NOT B
0ll - A OR XOT B
15 lO0 - A XOR B
l0l - Reserved ll0 - B
lll - A
20 ASel - Operand A Select 000 - (IP), (IP) 1 Indirect I/F Data 00l - X X Register 0l0 - S S Register 0ll - XP X' Register 100 - XP X~ Reglster BSel - Operand B Select 00 - Y Y Reglster 0l - #Value Immediate Value ll - Special Function When LSel .- ll0:
0lO - DALE Lookup Result g0 ll0 - SALE Lookup Result Immediate Value Word values fill the whole ~ield 45 Byte values must ~e repeated twice to ~ill the ~ield When BSel - ll (Special Punctions ):
Value ~unction Mnemonic 50 $oooo x rotate left 4 L4 (X) ,Rl2 (X) $1000 X rotate 8 (}~yte swap) SWAP(X~,L8(X),R8(X) $2000 X rotate right 4 R4 (X) ,Ll2 (X) $3000 port3et(X) PSET(X) $4000 X rotate left l Ll (X) 55 $5000 X rotate right l Rl (X~

~ ~ WO 95/18497 . 2 1 7 9 6 l 3 PCT/CA94/0069~

S6000 flip X FLIP(X1 57000 LI~B Version nuTn~er VE~
When Value ~ S3000 ~Portset Funcl:ion3:
s X(11:8~ ~(15:03

4 0000000000010000 14 . 0100000000000000 25 FIFO Write Instructions 31-29 1 28-26 1 25-24 1 23-21 l20-18 1 17-16 1 15-0 Il o 1 1 1 o 11 1 o ¦Bxtra IBSel iIIonedi~te Value (15-0) Bxtra/8Sel 3 0 Oee 01 MOVBF #Value, Extra Move I~oediate Value to PIFO with 3~xtra oits Oee 00 MOVEF Y,Extra Move Y 33egister to FIPO with Extra bits lee 00 MOVEF Index (LP) ,Bxtra Nove I~Ldexe~ Lookup Data to FIFO with Bxtra bits The FIFO write instructions are used to write data into the currently active result FIFO The hxtra field 40 control bits 16 and 17 in the FIFO data bus.
The third instruction in the list is a direct memory access ~rom SIB RAM to the active FIFO. SIB RAM is enabled while the active FIFO is sent a write pulse.
Doing so avoids having SIB data propagate through the 217~613 LUE. Bit 20 differpnti~t~c between a DMA and a non-Dr~
instruction .

The X register cannot be used as a MOVE~ source because what would normally be the ASel field conflicts

5 with the E~tra f ield .

Usage:
MOVEF #IPSnap, 0 ; Paclcet is IP over SI~AP
Interface E~AM Data Read Instructions ¦ 31-29 ¦ 28-26 ¦ 25-24 ¦ 23-21 ¦ 20-lB ¦ 17-16 ¦ 15-0 ¦ o 0 1 ¦ Dest ¦ Size l l 1 1 l 0 ¦ o 0 1 Unused Dest/Size 001 00 MOVE (IP~ ,X
Move IP indirect to X Register 001 10 MOVE (IP~ +,X
Move IP indirect autoinc to X Register 100 00 ~OVE (IP~ ,Y
Move IP indirect to Y Register 100 10 MWE (IP~+,Y
2 0 Move IP indirect autoinc to Y Reglster 111 00 MOVE (IP~ ,LP
Move IP indirect to LP Register 111 10 MOVE (IP)+,LP
Move Tp indirect autoinc to LP Register TntF-rf~ e RAM Data Read instructions are used to read data from the Interface R~M 41 into the X, Y or LP
Register The LP used is preselected using the RSEL
instruction .

30 Lookup Pointer Instructions Group Dest 0 0 LSel ASel ESel Ililmediate Value (15-0) or Reg Sel ( 15 -4 ) Extra or Index (3-0) Group/Dest~Sel/ASeltBSel - Instruction Type ~ WO95/18497 2 1 7 9 6 1 3 PCT/CA94/00695 101 101 111 001 00 MOVE X,IndexlLP) Move X ~egis~er to Indexed Lookup Data 101 101 110 000 00 MOVE Y,~ndex(LP3 Move X ~egister to IndexeLI Lookup Data 5 101 011 000 000 00 GEI` Index(LP) Load S Register with Indexed Lookup Data 001 111 110 000 00 MOVE Y,LP
Move X 3~egi~ter to Lookup Poin~er 001 111 110 000 01 MOVE #Value,LP
Move Immediate Value to Lookup Pointer 001 111 111 001 00 MOVE X,LP
Move X l~egister to Lookup Pointer Lookup Pointer instruc~ions are used to load the 15 Lookup Pointers or to store and retrieve values in Lookup RAM. --17sage -MOVE Age(LP),X ; Get Age field 2 0 ., . ; check age ... ; reset age MOVE X,Age (LP) ; put it back in Logic Instructions 31-29 1 28-26 1 25-24 1 23-21 ~ 20-18 1 17-16 1 15-0 O O 1 Dest O O LSel ASel BSel Immediate Value (15-0 or Index ( 3 - 0 ~
Logic instructions are used to perf~orm logic r--n;rllAtit~n~ on the X and Y Registers. ~ ' inAtion~ Of the selections above yield the following (useful) 3 0 instructions:
Dest/LSel/ASel/BSel 001 110 000 00 MOVE Y,X
Y -~ X
100 111 001 00 MOVE X,Y
X -, Y
001 111 010 00 MOVE S,X
S --> X
100 111 010 00 MOVE S,Y

' WO 9S/18497 2 1 7 q 6 1 3 PCT/CA94la0695 S -, Y
001 110 000 01 ~qOVE #Value,X
Immediate Value -, X
100 110 000 01 MOVE #Value,Y
S Immedi~te Value -~ Y
001 000 001 00 A~D X,Y,X
X A~D Y -~ X
001 000 010 00 A~D S, Y,X
S A~;D Y - > X
10 001 000 001 01 ~D X,#Value,X
X AND Value -> X
001 000 010 01 A~D S,#Value,X
S A~D Value -> X
100 000 001 00 A~D X,Y,Y
X A~D Y -> Y
100 000 010 00 A~D S,Y,Y '' S AXD Y - > Y
100 000 001 01 ~D X,#Value,Y
X AI~D Value -> Y
20 100 000 010 01 AND S,#Value,Y
S ~ND Value -~ Y
OR, ~ND~, ORZ~ and XOR are s~milar to AII~D:
dst 001 aaa bb O~ aaa,bb,dst aaa OR bb -> dst5 dst 010 aaa bb A~DN aaa,bb,ds;
aaa O~ bb -> dst dst 011 aaa bb ORN aaa,bb,dst aaa Ol~ bb -> dst dst 100 aaa bb XO~ aaa,bb,dst aaa OR bb -> dst Conditional Branch Instructions 1 31-29 1 2~-26 1 2~-Z4 1 23-16 1 lS-0 ¦ O 1 0 ¦ Cond . i Size ¦ ni crl A~f~m~nr ¦ Comparand 3 5 Cond/Size 000 01 ESC!i~E.b #Comparand,Label Bscape if Byte Not Eo,ual O O O 10 ESCI~E . w #Comparand, Label Escape if Word llot Equal 001 01 ESCGE.b #Com.parand,Label Escape if Byte Greater or Equal 001 10 ESCGE.w #Comparand,Label Escape if Word Greater or Equal 010 01 ESCLE.b #Co~mp~rand,L~bel Escape if Byte Less or Equal 010 10 ESCLE.w #Comparand,Label Escape 1~ Word Less or Equal 110 00 BYZ La~el Branch if Y ~e~ister ~s zero _ _ _ _ _ _ . . _ .. . .. ...

~ WO 95/1849~ ' 2 1 7 9 6 1 3 PCT/Cl~94100695 - 3~ --111 00 BYNZ Labe~
Branch i~ Y 5Agiste~ 's not zero Tnl ' Branch instr~ctions are used to compare 5 the current packet ~ield with an i ~ tP value. If the condition is met, the branch is taken; otherwise IP is incremented by the Tnl Size ~Jsage:
Labell: ; check if SNAP header ESCNE . w #S~, .aoel2 ; compare to SNAP value ~-ESCNE.w #sooo3~r9thprllAl~pl . . . _ Label2: -1~
X Register Branch Instructions 1 31-29 1 28-26 1 25-Z~ I ~3-21 ~ 20-16 1 15-0 ¦ o 1 1 ¦ Co~d ¦ 0 0 ¦ LSel ~ Disp ¦ Value Cond/LSel 110 100 BXEQ #Value,Label Branch ~ f X is equal ~o value 111 100 BXNE #Value,I,a'oel Branch if X "5 not equal to value 110 000 ANDBZ #Value,La'oel Branch if X AND Value is equal to zero 111 000 ANDEINZ #Value,Label Branch ~f X AND Value is not equal to zero 110 010 ANDN~3Z #Value,Laoel Branch if X AND NOT Value is equal to zero 111 010 A~DNBNZ #Value,La'oel Branch i X AND NOT VAlue is not equal to zero X Register Branch instructions are derived from the 35 X Register Logic instructions with Operand A always set to the X Register a~d Operand B always set to the Immediate value l~e X Re~ister is Ilot a~ected by any , ~ WO 95/18497 2 1 7 9 6 1 3 PC'r/CA94/00695 of these instructions. ~e disrli~c~m~nt field is reduced to 5 bits (+/- 32 instructions) U5age:
See Destination Lookup Instruction example s~P.w ; ignore the next word iield Other Branch Instructions 31-29 28-26 25-24 23-16 l5-g 1 3-0 l o 1 0 ¦ Cond ¦ Si~e ¦ Disp ¦ ExtCond ¦ ExtDisp Cond/Si~e/Disp/ExtCond/BxtDisp 100 00 $00 S000 0 DWAIT
Wait for DALE
100 00 S00 S~00 0 SWAIT
Wait for SALE
15 101 oo S00 scoo o F~;AIT
Wait for Snoop FIFO done 101 00 ddd S400 0 BCSE~I ddd Branch on checksum error 011 01 Sol S000 0 S7~IP.b Skip Byte ~same as IBRA.b ~1 011 10 Sol SOOO O SRIP.w Skip Word (same as IBRA.w +13 011 01 ddd S000 d IBRA.b Label Increment Byte and Branch Always 011 lo ddd S000 d IBRA.w Label Increment Word and Branch Always Switch on X (add X to PC~
011 00 ddd S000 d ~RA.u Label Branch Always These instructions are derived from the conditional branch instructions. Wait instructions loop until the ~tF~n~lo~ condition is false. Skip instructions move to 35 the next instruction and increment the IP c.~Lu~liately.
3~Sore branch instructions can be defined easily by using Cond=100 or 101 and picking an unused ExtCond pattern ` ~ W095/18497 ~ l q 6 1 3 PCT/CA94/0069 When Cond = 0ll (True), the rlicrlA~ nt field is t~n~ to 12 bit8 .

The SWITC~I instruction adds the least signif icant nibble of X to the PC. If X(3:0~ = 0, 16 is added to the 5 PC.

Usage:

SKIP . w ; ignore the next word f ield Index Pointer/Register Select Instructions 31-29 28-26 2s-24 Z3-21 20-18 17-16 15-0 Group Dest Oper LSel ~Sel ~3Sel In~nediate Value (15-0) or Register Select 115-4) Group/Dest/Oper/LSel/ASel/P,Sel 001 110 00 111 000 00 ST Xt,XPn,LPn3 X -, XP, optionally switch to XPn,LPn 001 001 oo lll 100 00 LD Xt,XPn,LPn7 XP -, X, option~lly 3witch to XPn,LPn 001 011 oo lll ooo oo RSEL XPn,LPn switch to XPn,LPn o00 0ll 10 110 ooo 01 LOADIP #Value Load IP in~nedi~te 000 011 10 111 001 00 LOAI~IP X
Lo~d IP with x Index Pointer instructions are u8ed to perform manip~ t i ~n~ on the index pointer .
Transfers from the X regi8ter8 are not normally used in a lookup ~unction but may be useful for general purpose tran8fers from interface R~M
The Regi8ter Select instruction selects a register from each of the regi8ter banks. The format of the Ban3c Select Bits f ield is:

~ WO 95/~8497 2 1 7 ~ 6 1 3 PCT/CA94/00695 1 15-12 ~ 10-8 1 7 1 6-4 1 3-0 ¦ X X X X ¦ XEn ¦ XSel I LPEn ¦ LPS~l ¦ X X X X
The En bits ~ptpr~ nP whether the corresponding select bits are valid. If En is zero, the corrPqp-~n-ling register selection remains l1nrh_n~Pd. If En is one, the 5 corresponding select bits are used. This -h_n; r--allows register selections to be made i n~lPpPntlpnt of each other.
n~ctin~tif~n Lookup Tnctr-l~ti~nc 0 0 1 0 1 0 ¦ Size ¦ 1 1 1 ¦ ASel ¦ O O ¦ Con~nand~Address Size/ASel 00 001 DLQAD X,Address r,Command]
Load X lnto DALE
oo ooo DLOAD (IP~ ,Address [,Col;~and]
Load IP indirect into DALE / load Con~nd Reg 10 000 DLOAD ~IP)+,Address I,Command]
Load IP indirect autoinc into DALE / load Co~nnand Reg 31-29 ~ 28-Z6 25-Z~ 23-21 1 20-18 17-16 15-0 0 0 1 Dest l o 0 ~ l l 0 ¦ 0 ¦ 1 0 ¦not used . - Dest Move DALE result pointer into Lookup Pointer 2 5 o o 1 DMOVE X
Move DALE result pointer into X Register 10 0 L'MOVE Y
Move DALE result pointer into Y 3?egister The rlPqtin_t;on lookup iIlstructions set up the DAI.E
and read results from it. The currently selected lookup pointer is used as the root pointer.

~ ~ WO9S/18497 2 1 7 9 6 1 3 PCT/CA94/0069~

The DLOAD instruction loads words into the 16 by 16 bit DALI~ Nibble R~M and loads the Co~Lnand Register. The DMOVB instrn~inn returns the DALE result.
Con~nand Register lS I 14 13 -12 11-4 3- 0 Start 1 Nibble O O O O O O O O Address The Start bit Eignals the DALE to start the lookup.
The Nibble Offset field points to the first yalid nibble in the first word loaded into the Address RAM.
The Address field points to the word being written in Nibble R~M.
The DMOVE instruction gets the 16 bit DALE result pointer. D~OVB should be preceded by DWAIT, otherwise the result tlay be in~Talid.
15 Osage:
LOADIP #StartOfP~cket ; point to start of packet DLOAD ~IP~+,Wordl ; load D~ word 1 DLOAD (IP)t,Word2 ; load DA word 2 DLOAD (IP)+,Word3,Start; load DA word 3 and start lookup .,, ; do other stuff D~5OVE X ; get result SXNE #Null, DAFound ; address i~ound in ta~7le 25 Source Lookup Instructionfi 31-25 l28-26 1 25-24 1 23-21 1 20-1& 1 17-16 1 1~-0 1 o 1 1 1 o I Size ~ ASel ¦ 1 ¦ Command/Ad~iregs Size/ASel -' 00 001 SLOAD X,Address t,Command~
3 0 Lo~d X into SALE
00 000 SLOAD (Ip) ~Addresfi I, Co~nand3 Load IP ir,direct into SA~E / load Co~nand Word 10 000 SLOAD (IP~ +,Address I, Con~and]
. .

. ~ WO 9S/1849~ 2 1 7 9 6 1 3 PCT/CA94/0069~

Lo~d IP indirect autoinc into SALE / load l:~onunand Word 31-29 28-2~; 25-24 Z3-21 20-18 17-16 1 lS-0 l o o 1 ¦ Dest l o ¦ l 1 0 ¦ O O 1 ¦ 1 0 1 Ilmnediate Value ~15-0) ¦
Deqt Move SALE re~ult pointer into Lookup Pointer O 01 sMc~rE X
Move SALE result polnter into X Register Move SALE result pointer into Y Register The destin~tinn lookup instructions set up the SALE
and read results from it. The currently selected lookup 15 pointer is used as the root pointer The SLOAD instruction loads words into the 16 by 16 bit SALE Nibble BAM and loads the Comma~d Word. The SMOVE instruction returns the SALE result Con~nand Word 1~ 1 14 1 13-12 ~ 11-4 1 3-0 St~rt 1 I Nib~le ¦ I Address The Start bit signals the SALE to start the lookup.
The Nibble Offset ~ield points to the first valid nibble in the first word loaded into the Address RAM.
The Address field points to the word being written in Addres s R~M
The SMOVE instruction gets the 16 bit SALE result pointer The SMOVE instruction should be preceded by SWAIT, otherwise the result may be invalid -- ~ WO95~18497 _ 4l _ pCT~C~94/00695 Us age:
SLOAD rIP) +,Wordl ; load DA word 1 SLCW (IP~ +,Word2 - load DA word 2 SLOAD (IP)+,Word3,Start ; load DA word 3 ~nd start looku ... ; do other stuff SWAIT ; wait for SALE to fini3h SMC~ X ; get result EXNE #Null,SAFound ; address found in table l0 Checksum Engine Instructions ¦ 0 0 1 ¦ 0 1 0 ¦ Size 1 1 1 1 ¦ ASel ¦ 1 0 ¦ 58000 ,, ..
Size/ASel lS 00 001 CLOAD X
Load X lnto Checksum Engine and start 00 000 CLOAD (IP~
Load IP indirect into Checksum Engine 2nd start 10 000 CLOAD (IP) +
20 Load IP indirect autoinc into Checksum Engine and start The CLOAD instruction loads a word count into the mh~mkc:~lm engine, clears the mhPrkcllm and starts the engine The word currently illde~ced bv IP i8 sllhs~ ently 2~ added to the checksum each time the IP crosses a word boundary until the count is exhausted.
Misc~ n~ Instructions .

31-29 1 28-16 lS-0 1 1 1 0 0 0 0 0 0 0 0 ¦ Code ~2-0) These instructions invoke special functions Code 001 Sl'OP
Stop execution until next lookup request WO9~ 497 2 1 7 9 6 1 3 PCT/C~94/00695 The lookup engine operation will now be descri~ed in more detail The instruction State Machine ( ISM1 is shown in Figure 17.
A lookup engine microcode will typically take f our S clock cycles. ~t 50 MHz, the instruction cycle ta3~es 80 ns to execute. Instructions that re~uire access to SIB
RAM, which reSIuire ar~itration with the Control Processor, and any future P~tPn~ n~:: that recluire more time to execute will re~uire one or more additional l0 cycles to ~ ~1 ete.
Af ter reset, the 3 LEC is in the idle state . As soon as one of the snoop FIFOs 42, 43 is non-empty, the ISM enters the main instruction cycle loop.
A microcode instruction cycle is typically divided 15 into four main states. State 3 and State 0 allow the microcode .-~mtPnt~ to propagate through the LEC. The instruction group is ~lPtp~n;nGrl in State l. If a fast instruction is keing P~p~lltpcl ~Groups 0-3), State 2 is entered; ';::ltPly~ Otherwise the appropriate next 20 state is entered according to the Group field.
Figure 18 shows a typical fast instruction.
By the time State 2 is reached, all signals will have settled. New values for the PC and if necessary, the IP and/or the selected dest;n~ti~n~ are loaded at the 25 end of this state.
State 42 is a dummy state for currently l1n~l~f;nP~l groupS .

~ ' wo 95/18497 2 1 7 9 6 1 3 PCT/C~94/006ss State 52 is a wait state for P7 tPrn-l accesses to SIB RAM. The ISM exits this state when the SIB RAM has been granted to the LEC long e~ough for an access to complete Figure l9 shows a typical SIB RA~q access instruction .
States 72 and 73 are ~rutPrl duri~g the STOP
instruction. State 73 flushes the snoop FIFOs in case me LEC cycles through States 0 to 3 ;n~qPf;n;t~ly until a STOP instruction is Pn~ ntP~P~, which }:r~ngs the LEC l~ack to the idle state.
The lookup reguest ~ n; ~ for a MAC layer lookup is as follows:
The reyuestor (eg. the AXE~ places ;n~ t;on, generally a packet header, into the snoop FIFO.
me empty flag of the FIFO kickstarts the LEC.
The LEC instructs the DALE to look up the destinatio~
address .
The LEC instrucSs the SALE to look up the source 2 0 address .
The LEC looks i~to the packet to dPtP~; nP the network layer protocol in case it needs to 3~e f orwarded .
The LEC waits for the SALE and reads the Source Address SIB pointer.
The source port is co~pared against the previously stored portset to see if the source endstation has moved _~ ' WO9~/18497 2 1 796 ~ 3 pCI~/CA94l0069 The LEC waits for the DALE~ and reads the Des~in~ti~-n Address SIB pointer.
The destin~ti nn area is compared to the source area to see if the endstations are in the same area 5 The source port is " ~ against the destini~ti~n port to see i~ the endstations are on the same port Packets are discarded if they serve no other useful purpose (eg. SA and DA on the same port or in different areas, errored packets). Otherwise they are sent to the 10 Control Processor for further proc~:sir~
Sample Program ; File: BDG a 5 ; Unic~t Bridging C~se ; Relen~e 1 1 h~ctionality BDG Btart:
20 ;XO ~ P~cket Statu~l word ; IP _ Point~i to 2nd byte o~ P8W
;DR - Contain~l Packet Statu~ Word ;X0, LP0 are de~ault XP, LP
25 MvVE S8000,LP ;Look up n~.. r;n.r;.~.~ MAC
DLvAD (IP~f,0 ;Load D-~t Addr bits 0-lS
DLQ~D (IP)+,l ;Load Dst Addr ~its 16-31 ;Load D~t Addr bitl~ 32-47 DLOAD (IP~+ 2,S8000 ~nd st~rt lookup MvVE $8000 LP ;Look up Source MAG
BLOAD (IP)+,0 ;Load 8rc Addr bit~ 0-lS
8LOAD (IP)~,l ;Loaa Src Adar bits 16-31 ;Load Src ~ddr ~vitl~ 32-47 8LC~AD (IP)+,2,S8000 ;~md ~tart lookup 3 5 ; determine protocol her~
ESCGE.w lSOO,Cl.__kE~ Iyl~e ;check i Boi.3 form~t EB~E w SAAAA~ e ; check DSAP/g8AP
ES~E.w S0300,8~pr~ "= ;check ~L ~ield EB A~E . w S 0 0 0 O, sN~ plrAknown~ype 40 ES~E.w $0800,81JAPU.J~.,v.. V~ l ;ch~ck protocol type ~ield ; It'~i IP over 8NaP
Bdg8NAPIP:
A~LvAD 5 ;~lisume IP header length is S
ES~l;E.w $4500,Bd,8!~APIP_withvpts ;check IP header s~P.w ;~kip length -SXIP w ;~kip identiiic~tion ~ WO 95/18497 ' 2 1 7 9 6 ~1 3 PCT/C~94/0069S

SXIP w ;-kip o~set ESCLE b S0l,BdgSNAPIP T~LExpired :checR ~rL
SltIP b ; ~kip protocol S~IP w i skip checksum MOVE ~IP~ +,X ;read NLSA
NOVE Rl~ (X) ,X ;~hift ~ir3t nibble to bottom 8WITCi; jcheck IP Cla~s BRA u BdgSNAPIPClA--A ;0xxx _ Class A address BRA u BdgSNAPIPCl_D sA
0 BRA u BdgSNAPIPCl~--A
BRA u BdgSNAPIPCla-sA
BRA u BdgSNAPIPC1~-~
BRA u BdgSNAPIPCl---sA
BRA u BdgSNAPIPCl4s-A
5 BRA u BdgSNAPIPCl l--B ;l0xx = Clnss B Address BRA u BdgSNAPIPClAs-B
BRA u BdgSNAPIPCla~sB -' BRA u BdgSNAPIPCl4-fiB
BRA u BdgSNAPIPCl~s-C ; ~ox _ Cla~ C addre~
BRA u BdgSNAPIPCla~C -BRA u BdgSNAPIPCla~sD ; lllO - C1~J~; D ~ddrenS
PRA u BdgSNAPIPClasDE ;llll ~ Clna~ E addres~ (~uture) BRA u BdggNAPIPCl~ssA ; 0xxx .~ Cl~mi A ~ddres~
BdgSNAPIPCla- A
OR X,$FFOO,X ;check i~ broadca~t BXNE $PFFP,BdgSNAPIP_~TC~
MOVE tIP~ ~, X ; check lowcr ~ddres~ word BXEQ SF~cFF~BdgsNApIp - ~T5~Tnlr-l;diall one3 host Address BRA u Bd~7SNAPIP NLSAV~lid ;broJdc~st SA i- not ~llowed 3 0 BdgSNAPIp NT.'r'` 1 i~n SIUP . W
BRA u BdgSNAPIP_NLSAV,llid BdgSNAPIPCl~sB
MOVE (IPI+,X ;check low ~ddress word BXNE $PFFF,BdgSNAPIP NLsAV~lid BRA u BdgSNAPIP NLSAV~lid BdgSNAPIPCld~C:
MOVE ~IPI~,X ;check lower _ddre3~ byte OR X, SFF00, X ; check i~ bro_dc~st BXEQ $FFFF,BdgSNAPIP NLSAIn~lid BRA u BdgSNAPIP_NLsAV~lid BdgSNAPIPCla-~D
S~UP . w BRA u BdgSNAPIP_NLSAVAlid BdgSNAPIP_ NT.q~Tnv~
SWAIT ;cleAn up _fter SALB ~md DALE
DWAIT
OR XP,C~ID_DISCARD ¦ CMD_~NIC~S~,Y ;Load co~and Word MOV~F ~, FIRST ;Send Comm~Lnd Word MOVEF Nr3I~L_CI ;Send CI Indcx NOVEF PORT CP ;Dest Port is CP
MOVEF RSN FRC_MAC_SRC_INVALID ;Send Re~on STOP
Bdg5NAPIP_NLsAVAlid:
SXIP w ;-kip NL~A
S~P .w BCSERR PDG_SNAPIP_CSError RSEL LPl ;Store ~ourc~ SIB pointer in LPl SWAIT

~ ~ WO 95118497 2 1 7 9 6 1 3 PCTICA94100695 SMOVE Y Y contains SALE reault MOVE Y,LP,LP2 jLPl points to sourc~ Addr SIB
gtore dest SIB point~r in LP2 BYN'L' BDG SrcHit BDG SrcMisJ ;~ sour~e Cach~ Miss ~
OR XP,CMD FWDCP I CtlD ~NICi~ST,Y jLo~d =nd Word ;Default M~C Ethernet Type ;De~ault Low priori~y 0 MOVEF Y, FIRST ;Send Comnumd Word MOVEF NULL CI ;Send CI Index MOVEF PORT CP ;D~st Port is CP
MOVEF E~SN FEC MAC SRC MISS ;Send Rea~on STOP ;Done! ! !
PDG SNAPIP CSE ror~
OE~ XP,CMD DISC~2D I CMD UNICAST,Y ;Load command Word MOVEF Y, FIIIST ; Send Comm~d Word MOVEF ~LL CI ; send CI Index MOVEF PORT CP ;De_t Port i~ CP
MOVEF RS~ FRC MAC CSEiRR ;Send Re~son S~OP
EDG SrcHit DWAI~
DMOVE Y ;Get DALE result MOVE Y,LP,LPl ;point to source SIB
BYNZ BDG CL__h9L~EVL~ ;And check ~ource port BDG DestMiss ;.. n eti~r;r~ C~che Miss ~
OR XP,CMD F11DCP I CMD U~IICAST,Y ;Load comm5nd Word 3 0 ;Default MAC Ethern~t ~ype ;Default Low priority MOVEF Y, FIBST ;send Commlmd Word MOVEF HDI,L CI ;Send CI Index MOVEF PORT CP ;De-t Port is CP
MOVEF ESN FRC MAC DST MISS ;Send E~eason STOP ;Done! ! !
BDG CheckSrcPort GET SIB MAC PORTSE~(LP) ;Co~pare port~ets in LP 5~ Src SIB
AND S,PSET(X) ,Y ;Y = src addr hit A~ID sr~ port hit BYNZ BDG ~h~ rn~ r~ea source mQved i~ bits don't m~tch BDG SrcMove ; '~ Source Moved ~
OR XP,CMD FNDCP ~ CMD ~NICAST,Y ;Lo~ld con~nand Word ;Default MAC Ethernet Type ;Default Low priority MOVEF Y, FIRST iSend Command Word MOVEF DULL CI ; Send CI Index MOVEF PORT CP ;Deat Port i~ CP
MOVEF RSN_FRC SRC MOVED iSend R~elson STOP ; Done ! ! !
BDG_rh~r~n~r~
RSEL LP2 ;point to dest SIB
OET SIB_PROTO ~REA_l (LP1 ;get IP Dest Area }~ND S,MASl~ ARE~a,Y ;Mask o~f top ~ hits BYNZ EDG Cl.~SL~AL~ .
BDG DestAreaInv lid ;'~' De~tination Ar~ Inv~lid ~'~

~ WO 95118497 2 1 7 9 6 1 3 rcT~cAg4/00695 ID X
OR X,CMD_DISCaRD I Cr~D_UNIC.3ST,Y ;Load comm~nd Word ;Deault r5AC Ethe-net Type ;Deaul~ Low priority ;De~ult Multic~L~t MOVEF Y, FIRST :send Comm~nd Word MOVEF NVLL_CI ;S nd CI Inaex MOVEF PORT _ CP ;D st Port i9 CP
MOVEF RSN_DRC_DST_ARl;A INV ;Send Re son STOP ; Done 1 ! !
BDG_Ch_ JGi . .A~
RSEL LPl ;get ready for 90urce Addr check ¢ET SIB_PROTO_AREA_l (LP) OR S,SIB_AREA_P~OTO ACTIVE,X ;s t PA bit in SIB_IPAREA
MOVE X,SIP._PROTO_AREA_ltLP~ ;modiy AWD X,MASY AREA, X ;MaRk of top 4 bits XOR X,Y,Y,LP2 ;check against D st Area ;svitch to LP2 ~Dest SIB1 BY:i BDG_CheckDestPort BD¢_SrcAreaInvalid~ Source Ar~ea Inva~lid OR XP,CMD_DISCARD ¦ CID _ VNICaST,Y ;Lo~d commund Word ;Deault MAC Ethernet Type ;Def~ult Low priority ;Def~ult Multica t MOVEF Y, FIRST ;Serd Connsnd Word MOVEF NULL _ CI ;Send CI Index MOVEF PORT_CP ;Dest Port i~ CP
MOVEF RSN _ DRC_SRC AfiEA IWV ;s nd Reason 8TOP ; Done ! 1 J
BDG Chec3cDestPort:
;XO, LP2 ~re deault XP, LP
LD X ;re~tore PSW
GFT SIB_MAC PORTSET~LP~ ;S . deot addres3 portRet AWD S, PSET~X) ,Y ;comp~re ~a~inst source p~rt portset BY~ BDG_OX
BDG_SamePort: ; Src Port = Dest Port ~
OR XP,C~D DISCARD ¦ C!ID_VNICaST,Y ;Load command Word ;Def~ult MAC Ethernet Type ;Default Low priority MOVEF Y, FIRST ;Scnd Colr~nd Word MOVEF NVLL_CI ; Scnd CI Index MOVEF PO~T_WVLL ;DeRt Port is NULL
MOVEF RSN_DRC_DST_SAME ;send ~eADon STOP iDone! 3 !
BDG _ 0~: ; Bridge-router OR XP,CMD BRIDGE-ROVTER I CMD_UNICAST,Y ;LoAd command Word ;DeIault MAC Ethe~net Type ;De~aUlt Low priority MOVEF Y, EIR8T ;Send Comm~ud Word MOVEF SIB_MaC_CI ~LP) ;send CI Index from dst SIB
MpVEF SIB_MaC_PORTSET~LP~ ;Dest Port io determined from dst SIB
MOVEF SIB_MAC_Ma~INDEX~LP~ ;Get MaC Ind x from dst SIB
STOP ;Done! ! !

' wo s5tl8497 2 1 7 9 6 1 3 PCT/CA94~01)69s The described look-up engine is capable o~
per~orming bridge-router and most network layer look-ups -in less than 5.6 ~18 (1/178,000) with to minimum R~M
5 requirements and cost and ~-T~m;7~ flexibility for ~uture additions/corrections without hardware changes.
The ;nt~nfl-~rl application o~ the look-up engine is high per~ormance LaN systems and other packet-based devices .

~ ~ WO95118497 2 1 7 q 6 1 3 PCT/CA94100695 t~T ,t~,r~ ,r~ ~T~Y
BRIDGE-~O~TER A LAN bridging-routing device, with 12 ethernet portfi and 1 ArM port.
A~M Asy~ uuuu:, l~nsfer l~ode. A cell relay standard .
ABS Address/Broadcast Se~yer A component of a Route Server that handles address resolution and broadcafit trafic.
AXE A ~raDsfer EDgiDe - -DA I)~ctin~tirn Addres8. The MAC address of the intended destination of a MAC fr~me.
DAL~ ~,.ctin:ltirn Address Look-up EDgi~e. The T~E
component that generally searches through a table of MAC layer ~tinAt~nn addrefises. ~
CI ~ ~'rnn~rtirn Tfl~nt~f~l~r, A nu~ber internally used to indicate a particular rnnn~rt 1 rn IP IDternet Protocol A popular netwo~:lc layer protocol used by the Internet community.
IPX T"rer~et Packet Ex~haDge A Novell developed network layer protocol.
LEC Look-up ngiDe Controller. The L~E component that executes microcode.
L~E Look-up T'"giDe.
MAC ~rediuo Access CoDtrol. A term commonly encountered in IEEE 802 standards generally referring to how a particular medium (ie.
Ethernet~ is used. "MAC address" i9 commonly used to refer to the globally unique 48 bit address given to dll interface cards adhering somewhat to the IEEE 8 02 standards .
RS Route Ser~er.
SA Source Address. The MAC addresfi of the originator of a MAC frame.
SALT~ Source Address Loo~-up T~'ngiDe. The L~E component that generally fiearches through a table o~ MAC
layer source addressefi.
SIB statioD rnfrrm:~tlnn BlocJ~. The data fitrUcture in the LUE that holds relevant ~n~nrr-tirn about an f.ntlctAt i rn CAM Content Addrefifiable Memory.
VPI Virtual Path Ttlont i f i F~r VCI Virtual Channel Identif ier Control Procefifior The ~L~ a~ll in the Bridge-router that handle functions

Claims (28)

Claims:

1. An arrangement for parsing packets in a packet-based data transmission network, said packets including packet headers divided into fields having values representing information pertaining to the packet, said arrangement comprising input means for receiving fields from said packet headers of incoming packets, means for storing information related to possible values of said fields, and means for retrieving said stored information appropriate to a received field value, characterized in that said retrieving means comprises a look-up engine including at least one memory organized in a hierarchical tree structure, and controller means for controlling the operation of said at least one memory.

2. An arrangement as claimed in claim 1, characterized in that said controller means compares, at each decision point on the tree structure, the current field with a known value or range, and moves to the next decision point by moving the current field pointer and branching to new code if said comparison results in a first logical condition, and if said comparison results in a second logical condition, the current field is compared to a different value or range, and so on until a said comparison results in said first logical condition.

3. An arrangement as claimed in claim 1, characterized in that said tree structure is based on nibbles of said field values, and said controller means matches successive nibbles of a field in said memory to locate the related information.

4. An arrangement as claimed in claim 3, characterized in that said controller means concatenates a first nibble of an incoming field value with a root pointer to obtain an index to a root pointer array, retrieves a word at a location identified by said index, concatenates the next nibble with the next word to form the next pointer and so on until said related information is retrieved.

5. An arrangement as claimed in claim 1, characterized in that said memory is a random access memory (RAM).

6. An arrangement as claimed in claim 1, characterized in that one of said fields comprises a destination address and said related information comprises the path data associated with said respective destination addresses.

7. An arrangement as claimed in claim 1, characterized in that said look-up engine further comprises a plurality of said memories operating in parallel, said memories being associated with respective fields of said packet headers.

8. An arrangement as claimed in claim 1, characterized in that each said memory is a random access memory (RAM).

9. An arrangement as claimed in claim 6, characterized in that one of said fields comprises a destination address and said related information comprises the path data associated with said respective destination addresses, and another of said fields comprises a source address and said retrieving means also locates path data associated with the source address in the header of said packet in parallel with the location of the path data associated with the destination address.

10. An arrangement as claimed in claim 7, characterized in that said controller means comprises a main controller controlling overall operation of the look-up engine and memory controllers associated with each said memory.

11. An arrangement as claimed in claim 10, characterized in that said main controller is a microcode engine.

12. An arrangement as claimed in claim 10, characterized in that said microcode engine comprises an interface memory for receiving said incoming packets, a station information block memory for storing information pertaining to endstations, and a microcode memory storing microcode instructions.

13. An arrangement as claimed in claim 11, characterized in that the microcode engine parses the remainder of the packet header using a specific instruction set while said information is retrieved from said memories.

14. An arrangement as claimed in claim 13, characterized in that said microcode engine comprises separate buses for instructions and data.

15. An arrangement as claimed in claim 14, characterized in that said microcode engine further comprises means for implementing optimized instructions that perform bit level logical comparisons and conditional branches within the same cycle and other instructions tailored to retrieving data from nibble-indexed data structures.

16. An arrangement as claimed in claim 15, characterized in that said microcode engine is implemented as an ASIC
processor.

17. An arrangement for parsing packets in a packet-based data transmission network, said packets including packet headers including destination and source address fields, said arrangement comprising input means for receiving fields from said packet headers of incoming packets, means for storing information related to possible values of said source and address fields, and means for retrieving said stored information, characterized in that it further comprises respective source and destination address look-up engines, a processor controlling overall operation of said source and destination address look-up engines, each said address look-up engine comprising a memory and associated memory controller, and said address look-up engines and said processor operating in parallel.

18. An arrangement as claimed in claim 17, characterized in that each said memory is based on a hierarchical tree structure.

19. An arrangement as claimed in claim 18, characterized in that said memory controllers compare, at each decision point on the tree structure, the current field with a known value or range, and move to the next decision point by moving the current field pointer and branching to new code if said comparison results in a first logical condition, and if said comparison results in a second logical condition, the current field is compared to a different value or range, and so on until a said comparison results in said first logical condition.

20. An arrangement as claimed in claim 18 or 19, characterized in that said processor comprises a microcode engine that parses additional fields in said packet header while said address look-up engines retrieve said related information.

21. An arrangement as claimed in claim 18 or 19, characterized in that said microcode engine comprises an interface memory for receiving said incoming packets, a station information block memory for storing information pertaining to endstations, and a microcode memory storing microcode instructions.

22. A method of parsing packets in a packet-based data transmission network, said packets including packet headers divided into fields having values representing information pertaining to the packet, comprising storing information related to possible values of said fields, receiving fields from said packet headers of incoming packets, and retrieving said stored information appropriate to a received field value, characterized in that said information is stored in a memory organized in a hierarchical tree structure.

23. A method as claimed in claim 22, characterized in that at each decision point on the tree structure, in retrieving said information the current field is compared with a known value or range, the current field pointer is moved and branched to new code if said comparison results in a first logical condition, and if said comparison results in a second logical condition, the current field is compared to a different value or range, and so on until a said comparison results in said first logical condition.

24. A method as claimed in claim 22, characterized in that said tree structure is based on nibbles of said field values, and successive nibbles of a field are matched to locate the related information.

25. A method as claimed in claim 24, characterized in that a first nibble of an incoming field value is concatenated with a root pointer to obtain an index to a root pointer array, a word at a location identified by said index is retrieved, the next nibble is concatenated with the next word to form the next pointer and so on until said related information is retrieved.

26. A method as claimed in claim 22, characterized in that information related to a plurality of fields is retrieved in parallel.

27. A method as claimed in claim 26, characterized in that one of said fields comprises a destination address and said related information comprises the path data associated with said respective destination address, and another of said fields comprises a source address and said related information comprises the path data associated with said source address.

28. A method as claimed in claim 27, characterized in that the remainder of the packet header is parsed using a specific instruction set while said related information is retrieved.