CA2193207A1 - Apparatus and Method for Clock Alignment and Switching - Google Patents

Apparatus and Method for Clock Alignment and Switching

Info

Publication number
CA2193207A1
CA2193207A1 CA2193207A CA2193207A CA2193207A1 CA 2193207 A1 CA2193207 A1 CA 2193207A1 CA 2193207 A CA2193207 A CA 2193207A CA 2193207 A CA2193207 A CA 2193207A CA 2193207 A1 CA2193207 A1 CA 2193207A1
Authority
CA
Canada
Prior art keywords
timing
clock
switching
active
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2193207A
Other languages
French (fr)
Other versions
CA2193207C (en
Inventor
Keith A. Sloan
Mark A. Lovell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent Holdings Inc
Original Assignee
Keith A. Sloan
Mark A. Lovell
Dsc Communications Corporation
Alcatel Usa, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Keith A. Sloan, Mark A. Lovell, Dsc Communications Corporation, Alcatel Usa, Inc. filed Critical Keith A. Sloan
Publication of CA2193207A1 publication Critical patent/CA2193207A1/en
Application granted granted Critical
Publication of CA2193207C publication Critical patent/CA2193207C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1604—Error detection or correction of the data by redundancy in hardware where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Abstract

In a telecommunication system (figure 1) having multiple timing subsystems (14, 16 and 18) receiving and distributing redundant timing signals, there is provided a circuitry for aligning first and second redundant timing signals (CLOCK A and CLOCK B) and switching therebetween. The circuitry includes a selecting and switching circuitry for receiving the first and second redundant timing signals (CLOCK A and CLOCK B) and designating one of the redundant timing signals as ACTIVE and the other as INACTIVE, and providing the ACTIVE
timing signal as an output timing reference signal. The selecting and switching circuitry further switching the ACTIVE and INACTIVE timing signal designation and output timing reference signal in response to detecting fault or a clock switching command. The ACTIVE timing signal is provided to a first delay path (DELAY PATH A) having a programmable delay value, which delays it and produces a first output timing signal. A second delay path (DELAY PATH B) receives the INACTIVE redundant timing signal and produces a second output timing signal. The circuitry further includes a phase detector (50) which receives the ACTIVE and INACTIVE output timing signals and generates a status signal indicative of the phase relationship therebetween.
CA002193207A 1994-06-21 1995-06-05 Apparatus and method for clock alignment and switching Expired - Fee Related CA2193207C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US262,921 1994-06-21
US08/262,921 US5515403A (en) 1994-06-21 1994-06-21 Apparatus and method for clock alignment and switching
PCT/US1995/007107 WO1995035608A1 (en) 1994-06-21 1995-06-05 Apparatus and method for clock alignment and switching

Publications (2)

Publication Number Publication Date
CA2193207A1 true CA2193207A1 (en) 1995-12-28
CA2193207C CA2193207C (en) 2001-01-23

Family

ID=22999641

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002193207A Expired - Fee Related CA2193207C (en) 1994-06-21 1995-06-05 Apparatus and method for clock alignment and switching

Country Status (7)

Country Link
US (1) US5515403A (en)
EP (1) EP0766892A4 (en)
JP (1) JP3069916B2 (en)
CA (1) CA2193207C (en)
FI (1) FI965093A (en)
MX (1) MX9606694A (en)
WO (1) WO1995035608A1 (en)

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07326950A (en) * 1994-06-02 1995-12-12 Fujitsu Ltd Skewness adjusting device for timing signal and its method
GB2293062B (en) * 1994-09-09 1996-12-04 Toshiba Kk Master-slave multiplex communication system and PLL circuit applied to the system
US5727034A (en) * 1995-07-26 1998-03-10 Nokia Telecommunications Oy Apparatus and method for synchronizing base sites individually in a communication system
SE504920C2 (en) * 1995-09-29 1997-05-26 Ericsson Telefon Ab L M Method and system for redundant clock distribution to telecommunications equipment in which switching of selected clock signal among the incoming clock signals is constantly taking place
US5703905A (en) * 1996-02-16 1997-12-30 Globespan Technologies, Inc. Multi-channel timing recovery system
JP3531374B2 (en) * 1996-09-03 2004-05-31 ソニー・プレシジョン・テクノロジー株式会社 Displacement detector
US5930311A (en) * 1996-10-10 1999-07-27 Alcatel Usa Sourcing, L.P. Circuitry for retiming a received data signal
US5740211A (en) * 1996-11-12 1998-04-14 Lucent Technologies Inc. Method and apparatus for a hitless switch-over between redundant signals
US5748569A (en) * 1996-12-19 1998-05-05 Dsc Telecom L.P. Apparatus and method for clock alignment and switching
TW357521B (en) * 1996-12-26 1999-05-01 Dsc Telecom Lp Data transfer system and method for distributed digital cross-connect system
JP3690899B2 (en) * 1997-05-30 2005-08-31 富士通株式会社 Clock generation circuit and semiconductor device
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6052726A (en) 1997-06-30 2000-04-18 Mci Communications Corp. Delay calculation for a frame relay network
US6078595A (en) * 1997-08-28 2000-06-20 Ascend Communications, Inc. Timing synchronization and switchover in a network switch
US6101197A (en) * 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US5966417A (en) * 1997-10-02 1999-10-12 International Business Machines Corporation Cycle alignment circuit for multicycle time systems
US6426985B1 (en) * 1998-04-03 2002-07-30 Matsushita Electric Industrial Co., Ltd. Variable delay circuit and phase adjustment circuit
US6327318B1 (en) * 1998-06-30 2001-12-04 Mosaid Technologies Incorporated Process, voltage, temperature independent switched delay compensation scheme
US6349399B1 (en) * 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
JP2000134246A (en) * 1998-10-26 2000-05-12 Fujitsu Ltd Transmitter
US6516006B1 (en) * 1999-02-16 2003-02-04 Mitsubishi Electric And Electronics U.S.A., Inc. Self-adjusting clock phase controlled architecture
US6470060B1 (en) * 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
FI107202B (en) * 1999-04-01 2001-06-15 Nokia Networks Oy Method and apparatus for exchanging parallel signals of a digital data transmission propagation contrast signal
US6194969B1 (en) 1999-05-19 2001-02-27 Sun Microsystems, Inc. System and method for providing master and slave phase-aligned clocks
US7111053B1 (en) 2000-05-20 2006-09-19 Ciena Corporation Template-driven management of telecommunications network via utilization of operations support services clients
US7143153B1 (en) 2000-11-09 2006-11-28 Ciena Corporation Internal network device dynamic health monitoring
US7225244B2 (en) * 2000-05-20 2007-05-29 Ciena Corporation Common command interface
US7266595B1 (en) 2000-05-20 2007-09-04 Ciena Corporation Accessing network device data through user profiles
US6880086B2 (en) 2000-05-20 2005-04-12 Ciena Corporation Signatures for facilitating hot upgrades of modular software components
US20020001307A1 (en) * 2000-05-20 2002-01-03 Equipe Communications Corporation VPI/VCI availability index
US20020116485A1 (en) * 2001-02-21 2002-08-22 Equipe Communications Corporation Out-of-band network management channels
US7222147B1 (en) 2000-05-20 2007-05-22 Ciena Corporation Processing network management data in accordance with metadata files
US7240364B1 (en) 2000-05-20 2007-07-03 Ciena Corporation Network device identity authentication
US6715097B1 (en) 2000-05-20 2004-03-30 Equipe Communications Corporation Hierarchical fault management in computer systems
US7020696B1 (en) 2000-05-20 2006-03-28 Ciena Corp. Distributed user management information in telecommunications networks
US7225240B1 (en) 2000-05-20 2007-05-29 Ciena Corporation Decoupling processes from hardware with logical identifiers
US6658580B1 (en) 2000-05-20 2003-12-02 Equipe Communications Corporation Redundant, synchronous central timing systems with constant master voltage controls and variable slave voltage controls
US6658579B1 (en) 2000-05-20 2003-12-02 Equipe Communications Corporation Network device with local timing systems for automatic selection between redundant, synchronous central timing systems
US6332198B1 (en) 2000-05-20 2001-12-18 Equipe Communications Corporation Network device for supporting multiple redundancy schemes
US6868092B1 (en) 2000-05-20 2005-03-15 Ciena Corporation Network device with embedded timing synchronization
US6934749B1 (en) 2000-05-20 2005-08-23 Ciena Corporation Tracking distributed data retrieval in a network device
US7280529B1 (en) 2000-05-20 2007-10-09 Ciena Corporation Providing network management access through user profiles
US6654903B1 (en) 2000-05-20 2003-11-25 Equipe Communications Corporation Vertical fault isolation in a computer system
US6760339B1 (en) 2000-05-20 2004-07-06 Equipe Communications Corporation Multi-layer network device in one telecommunications rack
US7062642B1 (en) 2000-05-20 2006-06-13 Ciena Corporation Policy based provisioning of network device resources
US6601186B1 (en) 2000-05-20 2003-07-29 Equipe Communications Corporation Independent restoration of control plane and data plane functions
US7051097B1 (en) 2000-05-20 2006-05-23 Ciena Corporation Embedded database for computer system management
US7349960B1 (en) 2000-05-20 2008-03-25 Ciena Corporation Throttling distributed statistical data retrieval in a network device
US6876652B1 (en) 2000-05-20 2005-04-05 Ciena Corporation Network device with a distributed switch fabric timing system
US7039046B1 (en) 2000-05-20 2006-05-02 Ciena Corporation Network device including central and distributed switch fabric subsystems
US6671699B1 (en) 2000-05-20 2003-12-30 Equipe Communications Corporation Shared database usage in network devices
US7054272B1 (en) 2000-07-11 2006-05-30 Ciena Corporation Upper layer network device including a physical layer test port
US6742134B1 (en) 2000-05-20 2004-05-25 Equipe Communications Corporation Maintaining a local backup for data plane processes
US6639910B1 (en) 2000-05-20 2003-10-28 Equipe Communications Corporation Functional separation of internal and external controls in network devices
US6708291B1 (en) 2000-05-20 2004-03-16 Equipe Communications Corporation Hierarchical fault descriptors in computer systems
US7023845B1 (en) 2000-06-13 2006-04-04 Ciena Corporation Network device including multiple mid-planes
US6718474B1 (en) * 2000-09-21 2004-04-06 Stratus Technologies Bermuda Ltd. Methods and apparatus for clock management based on environmental conditions
US6819726B2 (en) * 2000-12-07 2004-11-16 International Business Machines Corporation Dynamic phase alignment circuit
US7263597B2 (en) * 2001-04-19 2007-08-28 Ciena Corporation Network device including dedicated resources control plane
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6816018B1 (en) 2002-07-19 2004-11-09 3Com Corporation System and method for partitioning a system timing reference among multiple circuit boards
US7034596B2 (en) * 2003-02-11 2006-04-25 Lattice Semiconductor Corporation Adaptive input logic for phase adjustments
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
TWI242205B (en) * 2003-07-18 2005-10-21 Via Tech Inc Method and circuit for generating the tracking error signal using differential phase detection
US7292670B2 (en) * 2003-08-06 2007-11-06 Gennum Corporation System and method for automatically correcting duty cycle distortion
KR100533915B1 (en) * 2003-10-21 2005-12-06 한국전자통신연구원 Clock signal selecting device and method for guaranting its clock continuity
JP3892847B2 (en) * 2003-12-03 2007-03-14 株式会社東芝 Semiconductor integrated circuit and test method for semiconductor integrated circuit
US7109760B1 (en) * 2004-01-05 2006-09-19 Integrated Device Technology, Inc. Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles
US7279938B1 (en) * 2004-01-05 2007-10-09 Integrated Device Technology, Inc. Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein
EP1553478A1 (en) * 2004-01-06 2005-07-13 Alcatel A redundant synchronous clock distribution method, a related clock module and a related clock slave device
US7149145B2 (en) 2004-07-19 2006-12-12 Micron Technology, Inc. Delay stage-interweaved analog DLL/PLL
JP4862984B2 (en) 2005-03-30 2012-01-25 日本電気株式会社 Clock switching device and clock switching method
US7434082B2 (en) * 2005-09-30 2008-10-07 Agere Systems Inc. Multi-stage clock selector
US7697647B1 (en) * 2005-10-03 2010-04-13 Avaya Inc. Method and system for switching between two (or more) reference signals for clock synchronization
KR20080039021A (en) * 2006-10-31 2008-05-07 삼성전자주식회사 Intergrated circuit system and control method thereof
US7671634B2 (en) * 2007-07-30 2010-03-02 Hewlett-Packard Development Company, L.P. Redundant clock switch circuit
US7932756B2 (en) * 2007-08-01 2011-04-26 Texas Instruments Incorporated Master slave delay locked loops and uses thereof
US7952404B2 (en) * 2008-08-15 2011-05-31 Mosaid Technologies Incorporated Apparatus and method for modeling coarse stepsize delay element and delay locked loop using same
US7898286B2 (en) * 2009-02-11 2011-03-01 International Business Machines Corporation Critical path redundant logic for mitigation of hardware across chip variation
US8004329B1 (en) * 2010-03-19 2011-08-23 National Semiconductor Corporation Hardware performance monitor (HPM) with variable resolution for adaptive voltage scaling (AVS) systems
US9537591B2 (en) * 2011-03-30 2017-01-03 Tejas Networks Ltd Method for zero traffic hit synchronization switchover in telecommunication network
US8836394B2 (en) * 2012-03-26 2014-09-16 Rambus Inc. Method and apparatus for source-synchronous signaling
US9225344B2 (en) 2013-01-16 2015-12-29 Altera Corporation Methods and apparatus for aligning clock signals on an integrated circuit
US9369119B2 (en) * 2013-10-21 2016-06-14 Globalfoundries Inc. Adjustable delay calibration in a critical path monitor

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3769607A (en) * 1972-03-08 1973-10-30 Bell Telephone Labor Inc Switched oscillator clock pulse generator
IT1051350B (en) * 1975-12-09 1981-04-21 Cselt Centro Studi Lab Telecom TRIPLE TIMING SYSTEM FOR DUPLICATED SYSTEMS CONTE NENTI LOGIC CIRCUITS
US4229699A (en) * 1978-05-22 1980-10-21 Data General Corporation Multiple clock selection system
US5184027A (en) * 1987-03-20 1993-02-02 Hitachi, Ltd. Clock signal supply system
US4755704A (en) * 1987-06-30 1988-07-05 Unisys Corporation Automatic clock de-skewing apparatus
US4868514A (en) * 1987-11-17 1989-09-19 International Business Machines Corporation Apparatus and method for digital compensation of oscillator drift
US4789996A (en) * 1988-01-28 1988-12-06 Siemens Transmission Systems, Inc. Center frequency high resolution digital phase-lock loop circuit
US4899351A (en) * 1988-07-18 1990-02-06 Western Digital Corporation Transient free clock switch logic
JPH02105910A (en) * 1988-10-14 1990-04-18 Hitachi Ltd Logic integrated circuit
SE469203B (en) * 1988-11-18 1993-05-24 Ellemtel Utvecklings Ab PROCEDURE AND DEVICE TO RESTORE A DATA SIGNAL
ATE134284T1 (en) * 1989-04-28 1996-02-15 Siemens Ag CLOCK DISTRIBUTION DEVICE
US5258660A (en) * 1990-01-16 1993-11-02 Cray Research, Inc. Skew-compensated clock distribution system
US5204559A (en) * 1991-01-23 1993-04-20 Vitesse Semiconductor Corporation Method and apparatus for controlling clock skew
US5260979A (en) * 1991-05-28 1993-11-09 Codex Corp. Circuit and method of switching between redundant clocks for a phase lock loop
US5272390A (en) * 1991-09-23 1993-12-21 Digital Equipment Corporation Method and apparatus for clock skew reduction through absolute delay regulation
US5214680A (en) * 1991-11-01 1993-05-25 Hewlett-Packard Company CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration
US5317202A (en) * 1992-05-28 1994-05-31 Intel Corporation Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle
US5298866A (en) * 1992-06-04 1994-03-29 Kaplinsky Cecil H Clock distribution circuit with active de-skewing
US5289138A (en) * 1992-07-30 1994-02-22 Amdahl Corportion Apparatus for synchronously selecting different oscillators as system clock source
EP0596657A3 (en) * 1992-11-05 1994-12-07 American Telephone & Telegraph Normalization of apparent propagation delay.
JP2511370B2 (en) * 1993-02-26 1996-06-26 富士通株式会社 Receiver circuit
US5416807A (en) * 1993-03-31 1995-05-16 Intel Corporation Method and apparatus for synchronizing periodic sync pulse generations by a number of high speed circuits
US5422915A (en) * 1993-12-23 1995-06-06 Unisys Corporation Fault tolerant clock distribution system

Also Published As

Publication number Publication date
JPH09510338A (en) 1997-10-14
CA2193207C (en) 2001-01-23
EP0766892A4 (en) 1997-09-24
FI965093A0 (en) 1996-12-18
MX9606694A (en) 1997-03-29
WO1995035608A1 (en) 1995-12-28
US5515403A (en) 1996-05-07
EP0766892A1 (en) 1997-04-09
FI965093A (en) 1997-02-19
JP3069916B2 (en) 2000-07-24

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