CA2195459C

CA2195459C - Disciplined time scale generator for primary reference clocks

Info

Publication number: CA2195459C
Application number: CA002195459A
Authority: CA
Inventors: George Philip Zampetti
Original assignee: Symmetricom Inc
Current assignee: Microsemi Frequency and Time Corp
Priority date: 1994-07-21
Filing date: 1995-07-20
Publication date: 2002-07-09
Anticipated expiration: 2015-07-20
Also published as: WO1996003679A1; EP0771438A1; JPH10503282A; US5666330A; CA2195459A1

Abstract

Methods and apparatus are disclosed for providing disciplined clock signals at a plurality of nodes located throughout a network. In the preferred embodiments, a plurality of clocks are ensembled to provide ensemble time ba se information. A universal clock signal such as from a global positioning satellite (GPS) or Loran receiver is also provided and the ensembled time information is disciplined to the frequency or the phase of the universal clock signal to provide syntonisation or synchronization throughout the network.

Description

~ wo96103679 ? l 9 5 4 59 ~ JlO~

DISCIPLINED TIME SCALE GENERATOR
FOR PRIMARY REPCRUICE CLOCKS
NOTIÇE OF COPYRIGHTS
A portion of the disclosure of this patent document contains material 5 which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKCROUND OF THE INVENTION ___ _ Field of the Invention _ _ This invention relates to time scale ye,l~,dLiu" and particularly relates to traceable time scale ~t:"t:, at;ul 1.
Backaround of the Invention _ _ In many , ,: ' 1S such as telephone networks, power networks, and 15 computer networks, clock signals are generated for ..u"t" " ~y timing. For instance, LOw frequency, RAdio Navigation (Loran) and Global Positioning Satellites (GPS) may be used as clock sources. Although Loran and GPS
provide inexpensive and precise time scale sources, there are several d~ .L ~kc that have resulted in such sources not generally being used.
20 Typically, Loran and GPS master clocks are cu, lbidtlr t~d ~" ,de~i, aLJle because the communication link to the source -- a radio signal -- provides a relatively noisy communication link. Such noisy communication links result in injecting noise into the master clock as perceived at the node. Typically, rather than using these external timing sources, many of these clock signals are 25 generated at each switch or node in the network. Clock signals generated at a switch or node provide a local time base for tracking and controlling the relaUve occurrence of events. Examples of such time scale ~ dLu include ceramic oscillators, crystal oscillators, quartz oscillators, rubidium oscillators, and cesium oscillators. Cesium oscillators, which are so-called 30 primary atomic clocks, typically provide time base r~ l Ices with the highest degree of precision, accuracy and stability, but at the greatest cost.

W0 96103679 2 1 9 5 4 5 ~

Each of thess prior art oscillators may be used as a local time base generator and has a precision and stability that may depend on a variety of factors such as temperature, noise, system biases, etc. When it is necessary for many of the nodes of the network to communicate with each other, there typically is a requirement that these individual nodes have to be operating in Syl 11.:111 Ul li~dLiU~ I or s)" ILvu i::~dLiVI I with each other. Sy, n,hl u, li~dliUI I means that measured against some reference, there is a specific timing (phase and frequency) rt~ldLiUI l:~hil~ with a given level of precision between the clocks at two different nodes. Syl ILullisdliu~ ~ means that measured at a given level of 1û precision the frequency of the ciock sources at two different nodes is the same.
Various types of master or reference sources may be used. For example, the master clock source such as a cesium clock may be a cesium oscillator that is distributed over the network to each node. Each node in the network may i"co, ~u, dLt~ a less stable oscillator such as a rubidium oscillator and receives the master clock signal over a communication link.
To lock such oscillators to the master or reference clock source, various high precision phase and frequency locked loops such as the Stratum Model ST2, ST3 and ST3E which are available from the assignee of this ,, "
2û have been developed. These clock circuits provide high precision tracking of the reference or master signal with accuracy in the range of one part in 1011 over a day. However, cl~,u~"vi"g upon the amount of precision and accuracy desired, the use of these oscillators results in increased complexity and greater cost.
The most common method of obtaining sy~uh~u~ dLivll or syl~lunisdLion is to use phase locked loops or frequency locked loops, respectively, that are locked to a reference or master clock signal that is distributed throughout the network. A disadvantage of such distribution of a master clock signal throughout the network is that noise in the communication link and/or various error sources in the phase or frequency Iocked loop may cause timing (phase) errors or frequency errors in the network. Such timing or frequency errors result in slippage in the timing of ~WO96103679 2 1 9 54 5 q ~ C ~

data or other types of i, If ullllaLiul1 frames between various nodes. Where phase or frequency errors occur, this may result in slippage of, for example, timing intervals, resulting in the loss of data.
As a further means of improving local time scale y~ aLiOI l, various ~ 5 ~.~ucesses have been developed for improving stability. One common method for improved time scaie gencn aLiul1 is to have several highly accurate different sources such as oven-based rubidium oscillators and average the signals of the oscillators to try to minimize errors - 'Iy.
A further improvement of such averaging techniques is ensemble time base gt:,1e, 1. In ensemble time base y~:l1e'dtiu'1~ a variety of clock and other time base sources are provided. Rather than taking a simple IllaL~ nldti~al average of the timing source, various weighing factors are taken into account for gell~ldliu~ of the time scale based upon either the predicted or measured accuracy and stability of the various different time sources. There are several examples of ensemble time scale y~ laliOIl methods including public domain methods such as the AT1 and the AT2, which were developed by the National Institute of Standards and Technology (which is part of the United States D~:pal 1" ,c:, IL of Commerce) and describedin M. Weiss & T. Weissert, "AT2, A New Time Scale Al30rithm: AT1 Plus Frequency Variance," Metroloqia No. 28 p. 65-74 (1991).
N~ tl,eless, ensemble time scale ge~ ", fails to provide either sy".,h~u"i~dLioll or sy,,Lu,,i,dliun. Therefore, it is a first object of this invention to provide a Syl l-;hlul ,j~aL,lt: or s~" ILul lisabld time scale generator to provide synul~lu"i~dt;u" or syl~LunisdLiull throughout a network. It is a further object to provide a time scale generator using a bLIdiyhL~ulward and relatively inexpensive architecture. It is a further object to provide a , l; ,ed time scale generator that disciplines the ensemble time source to a reference clock. It is yet a further object of the invention to use GPS timingto provide the reference or master clock signal.
Summarv of the Invention These and other objects are a..;ul"~ '1ed through e"lbodi",dl,L~ of di~, 'i"ed, ensemble time scale g~ne,aLu,~. A plurality of nodes in the ... . . , .. , . = ,, . , . ,,,, . , .,,, _ _ _ _, . .. . .

wo s6/03679 4 network has a variety of time scale ~ lalu~b available such as a plurality of rubidium oscillators, a cesium oscillator and a network clock lldu b ulilLt:dfrom a master clock at another node. The plurality of clocks are ~, Ibel ul.led to provide an ensemble time scale generator having good stability due to the 5 ~,'t;~,;iu~'ly based deptl u ;~el1cy upon a plurality of reliable sources. These ens~",bled clocks are then subjected to frequency discipline from a clock source having fullddllleut~A'!y better long-term stability and accuracy that is available throughout the network. An example of such a time source is GPS.
In addition, the frequency ~ ,ed time scale may then be further subjected to time discipline from this same highly reliable clock source, providing sy,1uhluu i~aLi~.lll.
A reliable core hardware engine architecture is disclosed that permits efficient i" I,ul~l "e, lldLiun of frequency and time scale discipline of the e, Ib~:ll uLJled clock sources by a l~ic~Uplucessul i"l,ulel,,~uLdLiuu. This architecture requires a GPS receiver, a pair of multiplexers with each multiplexer coupled to the various local, network and Universal r;~ , IL ,i"9 Clocks, a digital synthesizer coupled to the output of the first multiplexer, and a time interval measuring device such as a starVstop counter having a start input coupled to the output of the second multiplexer and the stop output coupled to the synthesizer. This core architecture engine uses a Illiulu~Jlucebbul that ~IUCdbbds the a~ lulJIidL~ input signals to obtain the enst:"ll.led time iuiulllldLiul1 and then frequency disciplines the t,ns~", led time iufulllldLiull to provide a frequency ' , li~ldd time base signal.
Alternatively, a time (phase) '; , " ,ed time base signal may be provided.
Brief Description of the Drawinas _ _ _ Figure 1 is a block diagram showing a network embodiment of the invention.
Figure 2 is a hitlldlullicdl process diagram for an elllL udillltlllL of the invention used in a node in a network.
Figure 3 is a block diagram of a further t:" Ibodi" ,t:, IL of the invention fora node in a network to provide synLunisdliuu~

~ W096/03679 - 2 1 9 5 4 ~ 9 ~ . ;/C~16~

Figure 4 is a block diagram of additional Cu""~011t"1t:, that may be contbined with the e" ,L,odi" ,e"L of Figure 3 to obtain sy, l.:l " u, li~dLiUI 1.
Figure 5 is a bloclc diagram of an additional ulllbo.li,,,c,,,L of the invention.
Figure 6 is a bloclc diagram of an additional ~ L,o.iilll~llL of the invention.
Figure 7 is a block diagram of a local primary reference source for a telephone switching office.
Detailed Description of the Preferred C"lbo~li, "~"t:, Figure 1 shows a ne~work 10 having one or more nodes embodying the invention. The network .,o, "u,ise~ a plurality of nodes 12, 13, 14, 15, 18 and 19 communicating with each other over one or more L~ dl lal "is:,iu, I channels 20, 21, 22, 23, 24, and 25, and the nodes may comprise telephone switching offices. Each node has a plurality of clock sources, which may include two rubidium oscillators (RbA and RbB) such as in the ST2 available from the assignee of this ~ , one or two quark oscillators such as the ST3E
available from the assignee, a cesium oscillator (CS), a global po:,iLiu"ing satellite receiver (GPS) providing a GPS clock output, and a network oscillator source L, dna" litl~d from another node serving as the master clock.
Each node may also have other clock sources such as a Loran (not shown).
Figure 2 shows the basic operation of a network node containing an e" ,L~o~i" ,~"~ of the disclosed invention. The plurality of clock sources such as the two local rubidium clocks RbA and RbB, a local cesium clock Cs and a network clock Nt, which may be a rubidium clock at another node in the network, are ~":,t " IL~led 30. Tne e"s~" ,~ ' ,y is well known to those of skill in the art according to e~ldl,li~l ,ed protocols using a software engine and is preferably according to the AT2 protocol set forth in M. Weiss & T. Weissert, ~AT2, A New Time Scale Algorithm: AT1 Plus Frequency Variance," Metroloaia No. 28 p. 65-74 (1991 ), which is i"~,o"~o, dLtld by reference as if fully set forth.
In the AT2 protocol, the oegree to which a given clock source contributes to the overall time scale may be managed by both _ priori estimates of clock stability as well as by on-going measurement of clock stability. In the wo 96/03679 Z I ~ 5 4 ~ ,lo~ ~

standard ~",L,o~li",e"L of AT2 the i~L~yl ~ time of the frequency state estimates is largely d~ :L~I l "i, ~ed by an _ PriorL estimate of each clock's level of random walk frequency modulation noise while the weight of each clock's contribution to the time state is .It,lt"",i"ed adaptively based on measured 5 levels of white noise frequency modulation. In general all time scale alyul itl " ":, share as a common basis a standard clock model and time scale 91:111t:1dLiUII equations. The variation is in the Ill~Lhoduluyy used to controlthe weights and il lLt:yl d;ivn times used. This ~ boLli,, ~~ ~l encAps~ ~IAt~s the particular time scale algorithm as a fully iln~ tllldelll co,,,,uone,,l. The 10 precise manner in which the time scale algorithm is managed is not critical.
For example in certain " ,~ of this el"L,o.li",~"L ~.on~i,it:,t:d by the assignee both the weights and illL~yldi;~ll times are dt:lt"",i"ed _ Driori.
The output of this first stage is an ensemble time scale clock or clock state illFuulldti~ that is based upon the available clock sources.
The node then provides frequency " " ,il ,g to the enst~ I.Ied time scale by dl :l~l I l lil lil Iy 32 the frequency error between the ensemble time and a "Universal D: ' Iil Iy Clock" (UDC) which may for example be the clock reference signal L, dl 1:.11 liLL~ :d in a global po~iLiu"i"g satellite signal as detected by a GPS receiver (not shown). Alternatively for r~etworks occupying a 20 smaller geoyld~Jlli-; area Loran may be used. The measured frequency error is then used to generate a frequency correction factor to alter the frequency of the ensemble time scale over a long time interval such as several hours to that of the UDC. If each node in the network includes the l; ' ~i"y of the ense" ,bled time scale to the UDC then the network will be 25 in s~" ~Lul ~ Lion meaning the frequency of the _IL~ ed time scales at each network will be the same with a very high degree of precision.
Further as shown in step 34 the frequency 1; ' ,ed time scale provided may also be time di~ ' ~ed. Time ~' " li"g differs from frequency ~'~ ' Ii"g in that it removes the phase error between the 30 frequency ~ ed ensemble time and the Universal D;r li"g Clock such as GPS. Time ' " lil Ig occurs over a much longer period of time to~minimize data frame slippage.

~ W096103679 2 ~ 95459 r~ 5/~ 16>

~ , .
Figure 3 shows an t~ bodi~ 100 with such t:ns~", ,9 and ,i"g in block diagram form. An ens~" ,l-ler 102 has as its inputs each of the available clock sources including two rubidium clocks (RbO and Rb1), a cesium clock (Cs) a network clock (Nt) and optionally a Global 5 Positioning Satellite clock (GPS) provided from a GPS receiver. The output of the e"~",L,lt5, is preferably a 20 Mhz clock signal which is then divided down to provide a four Khz clock signal (for telephone :3p, '~ ,) by divider 104.
The four KHz output from the divider 104 is provided to four time interval measurino devices 106 108 110 and 112 which may comprise start/stop counters. Trne measuring device 106 measures during a sampling interval the phase difference between the GPS clock signal and the enst:"lL,l~d time. Tme measuring devices 108 110 and 112 measure the phase difference between the ensemble time and the cesium (Cs), network (Nt) and RbA clocks respectively. Each of these time measuring devices may be a starllstop counter driven by a clock signal that measures the ,c,t~. ,il,ed time (phase) difference between the start (one of the RbA Cs and Nt clocks) signals and the stop signal (ensemble time) The phase difference from each one of these time measuring devices 106 108 110and112duringasampleintervalprovidesacountvalue. That count value may be p, ucea~ed over a particular interval by a " ,iu, u~, ucessu~(CPU) 114 using frequency error estimate techniques that are well known in the field. That frequency error estimate is then " IdLI ,e" IdLi~ :y altered by a hltering function p~, ~u" "ed in the " ,iu, u~., UCt:ssu, 1 14 to provide a correction factor to alter the output frequency of a first numerically controlled oscillator 116. The numerically controlled oscillator 116 alters the frequency of the four KHz signal to provide a frequency .'i~ ~ed time scale output 118.
To obtain disciplined time scale throuohout a network a GPS clock signal from a GPS receiver will typically be selected as it has extremely good long-term stability and accuracy and on average is available virtually everywhere on earth. Thus the GPS signal serves as a Universal Disciplining Clock. To perform the di lillg the counts from the time measuring ~.

21 954~;9 W0 96/03679 I ~ JS io~

device that measures the phase diflerence between the '; ', " ,i"g time source and from the el1st" "L,led time are sampled and stored from time to time by the CPU. The samples are then ,~, uce~:,ed by the CPU for altering the correction factor for the numerically controlled oscillator. For a 'i~, " ,i"g time source such as GPS, the frequency control loop time constant is typically on the order of several hours while for a more short-term stable ' , " ,i"g source such as a Loran signal time scale, the time interval for .'i~, " ,ing may be much shorter, such as on the order of an hour.
Where a cesium clock having high short-term stability is being used in the 1û absence of a UDC, the interval may be only a few minutes. The updating of the time estimate may be done every 25.6 seconds.
It should be noted that the CPU can also monitor the various clock signals, including the various local clocks, such as RbA and Cs, and the UDC's, such as GPS and Loran, to determine the various clocks' pt" ru", Idl ,ce. If the l l li-,l u~, ucesso" for example, starts noting significant and varying changes in phase between any of these various clocks and ensemble time, indicating that the reliability and stability of that particular clock has de.;,t~d:.ed ay~ ,idbly, the clock may be discounted by the ~ ,cllllblel. Similarly, if the CPU notes that there has been a significant decrease in the stability of the Universal D -, ' ,i"g Clock such as GPS or Loran, the CPU may select a different Universal rk , ~ ,i"g Clock. In either event, the CPU may cause a fault indicator to be activated on a display either at the network node containing the CPU 114 or at a remote location elsewhere in the network.
Still further, a majority vote criteria may be used to control the weight d:.:.i~l 1111~1 IL for each of the available input signals. Such voting may be done after each estimate. Although the Universal D - , ' ,i"g Clock is less stable over the short term, it still may be used in this voting to assign the weights because it will help detect local clocks that have become unstable.
Figure 4 is a further ",~ to the tlllbo.lil"t:"l of Figure 3 that takes the frequency ~ ' , ' led output from the oscillator 116 and provides s~ ;l"u"i~dLion to the selected universal time source such as GPS. In 21 9545~
~ W096/03679 1~ 6.~

_ g _ particular, the syntonised output 118 from the oscillator 116 of Figure 3 is provided to a second NCO 150. The output 152 of the second NCO 150 is coupled to the time measuring device 154 that measures the phase d~ference between the output of the second oscillator 150 and the selected 5UDC time source 156 such as the GPS clock signal that has been selected for obtaining s~" ,tu, li::,aliul 1. The output of the time measuring device 154 is provided to the input of a digital filter 158 to provide an output indicating the average phase difference between the syntonised time from the second NCO
150 and the UDC time source. The average short-term stability of the UDC
source and the long-term stability of the ensemble time scale will determine the time constant of the filter 158, which may be ~ljl lct~hle Therefore, for a relatively short-term unstable UDC source such as GPS, the time constant should be fairly long; i.e., in the order of a day. When in the absence of a UDC time source, a local cesium clock having more short-term stability is used, the filtering time constant can be much shorter. Thus, by phase locking the second NC0 152 to the average phase of the GPS, or other UDC
time source, Syl l~hlul li~a~iull between the nodes within the network having the disclosed embodiments can be attained.
For all other nodes in the network that have the e" Ibo.li" ,t" ,l of Figure 4, full sy, l~,l " u" ~' ~ for all such nodes is attained. It should be noted that to avoid ullllect,s:,dly slippage of frames, the phase correction of the frequency li~ , " ,ecl time scale clock signal from the oscillator 150 by the second oscillator 152 should be much slower than the frequency correction.
Figure 5 shows a further ~ L o,lilllellL 200 of a disciplined time scale with a more efficient architecture. Each of the clock sources, such as the local time sources rubidium A (RbA) and rubidium B (RbB), a cesium atomic clock (Cs) and the Universal D , 'i. ,i"g Clock source, which is preferably GPS, and any other time sources such as a network time source (Nt), are provided to two multiplexers 202, 204. The selected output of the multiplexers 202, 204 is controlled by a central p~uces~ g unit (CPU) 206, which may be any high speed ",i~;,up,ucessu, and is preferably a digital sipnal processor. Control line 203 is generally not changed unless the W096/03679 21 9 54 59 r~ 6~

selected input becomes unstable. Ordinarily control linr~ 203 is set to select as the output of multiplexer 202 the most reliable and stable short-term time source available as dtlL~I " ,ined by the CPU 206 which is typically the cesium time source (Cs). Selection of a different time source such as one of the 5 rubidium time sources (RbA and RbB) only occurs if the CPU 206 ~ s that the previously selected source has become unstable or if there is no cesium in the office. The selected time source is provided as an input to the synthesizer 210 which may be an NCO or swallow counter.
An output 212 of synthesizer (Synt) or NCO 210 is fed back to an input 10 of a starVstop time measuring device 214. The other input of the time measuring device 214 is coupled to the output of the second multiplexer 204.
Under CPU 206 control over control 205 multiplexer 204 p~ ' 'Iy (from time to time) provides a control signal to provide a different time source for CC/I I IIJdl iaOIl by the time measuring device. Thus the time measuring device 15 provides successive phase measurements or samples of the following at sampling intervals controlled by the CPU 206 from which the following is r,zllr.l ~ tclr!
Table I
l~X(RbA-Synt) I~X(RbB-Synt) ~X(Cs-Synt) ~X(Nt-Synt) ~X(GPS-Synt) ~X(Counter Bias) where ~X is the ill-l~",enLdl time error (phase error uulllldli~t:d with respect to the nominal frequency) measured over the sampling period which is p~ o~ n~al to the frequency difference between the _ _ _ _ _ . . . .. _ .. _ . . . _ _ _ _ ~ W0 96103679 2 1 9 5 4 5 9 two time bases within the pd~ Lhese~, and where ~X (Synt-Synt) is a measure of the i"~ " ,~ dl time offset in the timing measurement device to permit the CPU 206 to ~.ull~ ensdlt~ for this offset variation as a function of temperature and Sother envi,o"",_"ldl factors; it is measured by applying an input clock to the start and stop terminal of the counter; and where Synt is the output of the synthesizer.
The CPU 206 may through simple manipulation obtain a "pairwise"
difference matrix illdtl~ ellclt:lll of the synthesizer input. For example, the 10pairwise difference between successive samples of the RbA and RbB time sources may be attained by the following as the synthesizer frequency co"~,uu"~"l may be canceled by subtraction:
~X(RbA-Syn~
b~-Syn~
~!(RbA-~bf~
With summation the i".i, ~r"e, lldl time error pairwise data can be converted to time error data which is normally used in time scale dlgo,itl ""s.

~a~RbA-Rbl3~ qRbA-Rbf~
15Each of these pairwise dif~ nces between successive samples of the different time sources can be obtained in a like manner by the CPU 206 to provide a pairwise matrix as shown in Table ll, where i and j are the indices for the pairwise matrix:

W 0 96/03679 2 1 9 5 4 5 q F~~

Table ll j~ 1 2 3 4 S

1X~Rb/.RbA)X(RbA-RbB) X(RbA-C ) X(RbA-Nt) X(RbA-GPS) 2X(RbB-RbA)X(Rbb'-RbB) X(RbB-C-) X(Rb~N~ X(Rbeu~PS) 3X(Cs-RbA) X(Cs-RbB) X(Cc-Cs) X(C~N~ X(C~GPS) 4X(Nt-RbA) X(rt-RbB) X(ht-Cs) X(Nh-Nt) X(Pt-GPS) SX(GPS RbA)X(GPS-RbB) X(GPS ~) X(GPS-N~ X(GPS-GPS) (Of course for computational ease the pairwise di~ ces of the samples 10 along the matrix diagonal (Xj j) running from top left to bottom right (the axis of symmetry) need not be calculated as these values are naturally zero.
Also the pairwise .lill~ ces below the matrix s axis of symmetry can be obtained by simple two s co" ,~ "e"l ~ ~ Idthe~ d~ , as is readily apparent.)Each of the pairwise matrix cu" I~JUl ,e"t~ may then be provided to any 15 of several well known time scale software engines to provide state estimates for the time and frequency difference of each input with respect to ensemble time. The state estimates of the ensemble time are produced by the CPU
206 and stored in RAM and the state estimate of the ensemble time is the computational analog of the ensemble time provided to the time measuring 20 devices in the elllbodi~ of Figure 3. The output of the time scale algorithm provides the correction factors needed to Colll~Jellsdltl any of the inputs onto ensemble time. In this tllllbodi",~llL this co",,uel1sdliol1 is pt:lluu~ed directly on the synthesizer output.
The control of the synthesizer output combines the correction needed 25 to r;o",pt", ~i the output onto ensemble time scale and the correction needed to uo~ rllsdl~ the ensemble timescale onto the long term UDC
frequency in a single algorithm. Before d ~5~,1ibi~y this control servo algorithm the Ii. ,i"g frequency correction calculation is described.
The is ,i, ,9 algorithm utilizes the timescale i"- ~ ~" ~utdl time state estimate for the selected UDC input to determine the 1 ,i"y frequency 2~ 95~9 W096/03679 P~,l/u... '~,lo~

correction. The discipling ~ ' , is pel~ulllldd at the same update interval as the timescale algorithm. In the case that GPS is the UDC source, the timescale algorithm will assign the GPS timing input zero weight. This is desirable since the GPS timing signal is much less stable in the short term 5 than the local oscillator sources (such as two local robidiums). The timescalealgorithm will provide state estimates for a zero weight input without allowing it to influence the actual output timescale.
The, '; , ' ,i"g algorithm illl~ , a digital low pass filter on the i"~;, u" ,e, ILdl UDC time state estimate to reduce the excessive phase noise on10 this signal. The filter output is cJtl~,il, IdLt:d 50 that the 'i~ , " ,i"g frequency correction factor is updated every nth timescale state update cycle. In the case of GPS, the nominai i, ILt:yl dLiUIl time of the filter is 30 minutes, and the y frequency correction factor is updated nominally every 30 minutes. The digital lowpass filter is illl~.lu~ Ltld to avoid truncation and 15 round-off error.
The digital filter output is the current l; , ' ,i"g frequency estimate.
This current estimate is compared to the previous. If the two estimates agree within the expected qll "~ , threshold then the current estimate is accepted. An accepted estimate is given as input to an d~ tnltdl 20 s" ,ouLhi"y filter to calculate the r' - , ' ,i"g frequency correction. The time constant of the filter is selected to minimize the frequency instability of the overall output. This is co":,L, dil ,ed a follows: For short time constants, theinstability of the UDC source dolllilldLe:s, and for long time constants the instability of the timescale dulllilldLe:s. In the case of GPSI a nominal two 25 hour time constant provides operation in the region of maximum frequency stability for rubdium local oscillators.
Given the timescale state estimates, and the calculated discipling frequency correction, the control servo alaorithm to steer the single synthesizer in this ~" Ibodi, "e, IL can be desired. Assume for this e,~la, IdLiOn 3û that the input to the synthesizer 210 is selected to be RbA via multiplexer 202. The synthesizer control word is the sum of a frequency control word (F ::W) and a phase control word (PCW).

wos6/0367s 2 l 9 54 59 1~l",~

The frequency control word is calculated directly from the timescale frequency state and the " , " lil Iy frequency correction as follows:

FCW= ~ RbA-E7)+ ~ET- UDC~

where Y is the fractional frequency error of the clock with respect to its nominal frequency and is therefore measured in parts per million;
Y is the estimation of the true fractional frequency error;
where Y (RbA-ET) is the timescale frequency state estimate for the RbA input and 1û Y (ET-UDC) is the current d i~ , " ,i"g frequency correction.
The frequency control word can be viewed as the open loop or feed forward CUI I II_Itll ladliUIl to correct the output synthesizer to nominally correct frequency. The phase control word (PCW) provided to the NC0 is the closed loop correction feedback factor to remove any residual error resulting from small bias and resolution effects ~ c.~ d with the hardware NC0 (SYNT). The phase control word is calculated as follows:
PCW = ~ (Residual Time Error) 2 where 0~ is the ~lupOIliurldl time constant.
The residual time error is dtdcn I l lil ,ed by cu" I,Udl il ~g the measured time 2û error between the output and input to the hardware synthesizer (NC0) with respect to the calculated expected phase ramp.
The i".;,t""~, ILdl time error is:

~X (RbA-Synt) Measured iln~ ellldl time error between RbA and Synthesizer (input and output of Synthesizer) + ~X (CounterBias) Cu~ ellsaliull term for il l~ uidl bias in time measuring device ~X (RbA~Synt~) Measured ill~ llltniidl corrected time error 3 ~X (RbA-Synt~) isthecc""~e~ dltld measuredilIU~"It~ dl phase ramp.

~ wo 96/03679 2 1 9 5 4 5 9 r~"~ 3i~

The calculated expected time error can be daLullllilldd from the bmescale frequency state and the discipling frequency correction, and is plulJolLiulldl to the negative of the frequency control word:

~(RbA- UDCJ=[ ~(RbA- E7) + Y(ET- U~C)]~ T 4 where ~T is the timescale update interval.
The illult~ Ldl residual time error is the difference between the measured corrected ill~ llldl time error and the calculated ill~,l~llltllltdl time enror:

~ ResldualTime)=~X~RbA~ RbA-UDC~) 5 The residual time error is the summation of the iln,l~ tdl residual time error. The phase control time constant is selected based on the measurement noise in the time measurement device and the bias and resolution efforts in the hardware synthesizer. Typically a time constant in the range of 1ûO to 1000 seconds will achieve the desired stability.
The output of the synthesizer can be controlled by the CPU 206 according to standard dlÇ101 al ", la to provide ens~:" Ibled time based upon the two rubidium clocks, one cesium and one network clock available from the matrix. Further, the same time scale engine can use the ensemble time and the frequency difft~ ces between the computed ensemble time and the 2û averaged received GPS signal to generate a frequency ' , ' ,ed time base to provide s~"~lu,liadLiun with a Universal rb, ~i"y Clock. In addition, if desired, the CPU 206 can also compute the dlJ,UIUplidlt~ phase increment update according to these engines to provide s~"-,i " u, li~dLiUI 1.
A further improvement for use with this approach is the use of an illult~ llLdl pairwise matrix instead of the pairwise matrix shown in Table ll above. The i".,, t" l I~U Ldl pairwise matrix cu" ~yl i:~ds the difft:l e" ICe5 between successive pairwise samples:
.

W O 96/03679 2 1 9 5 4 5 9 . ~ 6~ ~

- 1 6 ~

~Xll~+~)=xllt+~)-xll~ 6 where Xj j(t) is the j,i element of Table ll at time sample interval t;
and where Xj ,(t+~) is the same j,i element of Table ll at the next time sample interval t+l.
5 Thus, the delta pairwise matrix is defined at Table lll below:

Table lll Vi 1 2 S 4 S

1 ~X~RbA-RbA) ~X(RbA-RbB)~X(RbA Cs) ~X(RbA~ XiRbA4PS) 1 0 2 ~X(RbB-RbA) ~X(RbB-RbB)~X(Rbb'-C ~ ~X(Rbi~ X(RbB~iP~

3 ~X( ~ RbA~ ~X(C~RbBj ~X(C C~ ~X(C ~1 ~X(i'~C=P~

4 ~X(i~n-RbAi ~X(it-RbB) ~X(h-Cs) ~X( t-i~ ~X(i~-GPS) ~X(GPS-RbA) ~X(GPS RbS)~X(GPS~C )~X(GPS- 1 ~X(GPS4 PS) 15 A benefit of using the delta pairwise matrix instead of the regular pah-wise matrix of Table ll above is that the range of the matrix values and the range of the state estimates for the time and frequency di~ ws between the clock source and the synthesizer output have a siy" ' lily smaller range of values permitting the use of integer math, particularly with respect to the 20 phase error.
Further, if time discipline in addition to frequency ~ " , " ,i"g is required between the UDC and the output of the synthesizer, instead of outputting the frequency correction factor, a time correction factor may be ~:z~ lzi~Qrl This time correction factor can be derived by calculating the frequency P i , " ,ed 25 time scale state and based upon the filtered, differential errors of the time measuring device between the GPS source and the output of the synthesizer, the correction factor may be calculated by the I l liului ilucebbo for the phase error correction factor to provide s~" ,.,1 " ~ diii n.

~ WO 96/03679 2 1 9 5 4 5 9 r~ Slo~
_ 1 7 -A unique advantage of ~i~ , " ,i"g the clock source to GPS is that GPS
is generally universally available throughout the yeOs~,d~l,ic area of the network. Therefore, if each node in the network has a frequency .'is , " led clock such as shown in Figure 3, then each of the nodes in the network is in sy~Lv~iadLiv~l with the UDC time source (for example, GPS) -- and the other nodes that are di~ , ' ,ed to the UDC time source.
Further, by using en:~el l l' " ,9 time scale, if the UDC time source such as GPS is lost due to, for example, solar flare activity, the use of " , ' led tll ISel, IL,led time provides a highly stable local time source. Upon loss of the GPS or other UDC time source, due to the highly stable local time source provided by ense",L led time, each node in the network can still maintain s~" ~Lu, l;~ vn and possibly even s~l luhl uni~aLiull with the other nodes in the network for a substantial period of time. In particular, each node in the network may preferably upon detection of the loss of the UDC time source enter into a holdover state whereby each of the NCO's is held in a fixed state. Since the local time source for each node is an e"se"lL,led time, which is much more stable than each of the constituent time sources in the ellselllblecl time scale, each node will stay in syllLùnisaL;vll with the other nodes for a substantial time interval until the UDC time scale, such as GPS, is reacquired.
Figure 6 is a block diagram of a local primary reference source 300 using an el ~ Ibodi,, lel ,l of the invention. The source 300 is preferably coupled to a global reference poaiLiullillg timing receiver (GTR) 302 designed to receive a global pu~iL;vl ~ g signal and preferably mounted on the roof of the office where the local primary reference source 300 is located. The GTR 302 receives the global po~iLio"i"g signal from a satellite network and has a lightening suppressor 304, and a fiber cable link 306 to the omce including the local primary reference source 300. The source 300 includes a global pvailiul lil l9 timing interface 400 and various audio and visual alarms 308 forerror .,ondiLivn:, and a power supply 310. Also coupled to the source 300 is a digital clock distributor system (DCD) 320 such as is available from the TelPcom Solutions division of Syllllllet~icolll, Inc. of San Jose Califomia. The WO 96/03679 ' 2 l 9 5 4 ~ ~ Y~ 2 ~

DCD 320 includes preferably two rubidium clock sources RbA and RbB that may be ST2's 322, 324 available from Telecom Solutions. Also included are a, lldil ll~l Idl lI..tH nterface system 326 and multiple reference clock co"t" " ~ a A and B (MRCA 327 and MRCB 328) which may receive external multiple 5 reference clock sources 330 and the outputs of the GTI for clock distribution throughout the office.
Figure 7 shows a more detailed timing diagram of part of the LPRS 300.
The 5 MHz square wave clock sources RbA and RbB are coupled to divide by 1250 dividers to provide 4 KHz signals RbA and RbB signals to selector 402. The output of the selector 402 is coupled to a 20.128 MHz phase lock loop that along with the 4KHz RbA, 4KHz RbB and UDC 4 KHZ signal from the GPS receiver are supplied to an ISAM 404 that is available from Telecom.
Normally, the 20.128 MHz phase lock loop 404 is driven by one of the 4KHz RbA and RbB signals.
The GTI utilizes the ISAM (illlt:y, ' synthesizer and measurement) hardware engine to provide a cost effective and high pe, lu~ ~ l lal ,ce d i~ , ' Itld timescale function. The GTI ISAM is designed to support up to five channels of phase measurement, and a 32 bit coherent digital synthesis integrated into a FPGA. The digital synthesizer is i~lpltull~ d without the use of a D/A
converter. Instead, a digital mixer technique is employed to suppress synthesizer jitter and improve hardware resolution. The digital synthesizer has the following ~l .e~ Ul ~
1. Resolution: 1.4E-11 (Extended to 6E-15 by Steering Control Servo).
2. Jitter: <200ps.
3. Nominal Output Frequency: 20 MHz.
The multi-channel phase measurement sub-system measures up to five input channels with respect to the synthesizer output. Each input channel is con~ io,1ed to be a sampling pulse train to the FPGA. The pulse train may be at rates of 4KHz, 8KHz, 16KHz or 32KHz. For rates lower than 32 KHz, the phase measurement is p~l~ul~ d effectively at the 32KHz harmonic fre~uency. In the GRI, all input channels are at the 4KHz sampling pulse ~ W0 96/03679 ' 2 1 9 5 4 ~ 9 ~ u~ o~

, rate. The nominal pulse width is 500 ns. The phase measurement sub-system has the following s~
1. Settling rlme (Time after selecting an input channel until it is ready to be measured): 80ms.
2. Single Shot Measurement Interval: <2ûms.
3. Single Shot Measurement Resolution: 640ps.
4. Measurement Range: 31.25 ~ ;, usecu, ,.b (0 to BEC5 Hex on 16 bit l/O) from FPGA).
In the GTI, 4 phase measurement channels are utilized. The channel 1 û asbiyl " "t, ~b are:
1. 4KHz sampling strobe derived from local oscillator input A.
2. 4KHz sampling strobe derived from local oscillator input B.
3. 4KHz sampling strobe derived from GTR timing input.
4. 4KHz sampling strobe derived from 20 MHz Synthesizer output (G '' dLiull Channel).
A measurement cycle consists of collection one single shot measurement from each of the four channels. A measurement cycle is ~;o" l~ d every 400ms.
The numerically controlled oscillator and integrated phase measurement system cu~ libeb an ISAM engine 406 illl~ ult~llL~d in a gate array that is available from the Telecom Solutions Division of Syllllll~LIiuulll. The ISAM
engine 406 provides two outputs, a 10 MHz output and a 20 MHz output that is in tum provided to a 1.544/ 2.048 MHz framer phase lock loop 408.
Whether the loop 408 is operating at 1.544 MHz or 2.48 MHz depends upon whether the outputs are to be in a T1 or an E1 data format. The output of the framer PLL 408 is coupled to the T1/E1 framer 412 for distribution on output busses Out A and Out B by line interface units 414. The GPS 4 KHz signal is also made available at an output. If desired, the ISAM engine 406 may also receive a LORAN timing signal.
The 4 KHz GPS signal is supplied from the GTR 302 in the following manner. An optical sensor module 416 is coupled to fiber 306 and converts an opbcal pulse train from the fiber 306 into an electrical signal for decoding wosrj/0367s 21954~9 r~ oS~

by a '' ,ol,e~l~r decoder 418 to provide the 4 KHz GPS signal for distribution over bus 420. The " Idl l~.h~ ,. decoder also receives an 18.432 MHz clock signal and provides a signal to the 1 pulse per second (1 PPS) decoder 424 based upon a ~ d~t~""i"ed sequence contained w'lthin the 5 signal from the GTR to provide a one pulse per second datum for use by a time of day module 422 that provides the time of day in a variety of different data formats. Data from the time of day module 422 may also be provided through the engine 416 to the GTR over the fiber 304. Time of day data may also be communicated serially from the engine 416 to a UART on the 10 I l li~;l Upl ucbssor 440.
Data may also be provided to the GTR 302 through the moduie 416 by the ruiu,o~u,uue:x~ul 440 which preferably is a Z180 available from Zilog of Campbell, California. The ",iu,u~,,u~.esso, 440 preferably includes a 2400 baud UART for communication with the GTR 302 and a UART 9600 baud port that is coupled to the MIS 326 through a serial interface using the RS232 protocol. The 1 PPS decoder 422 also provides a pulse once per second to the 2400 baud UART port.
Preferably, the " ,i.,, u~, uceasor has three hardware interrupts, INT0, INT1 and INT2 coupled respectively to the output of the 1PPS decoder 424 and the time of day engine, a maskable interrupt responsive to a status register in an l/O interrupt controller 452, a direct memory access (DMA) controller, and a serial port coupled to the framer 412. The framer 412 provides a framed all one's signal optionally in either a T1 (at 1.544 MHz) or E1 CC (at 2.048 MHz) format using either a Dallas Semiconductor DS2180A or DS2181 respectively.
Also included are EEPROM 442 that may contain the program for the Z18û, data RAM 444 for use by the processor, flash RAM containing the boot program 446, a real time clock module 448 such as a ICM 7170 available from Harris Semiconductor, and a front control panel 450 including a multi-line display module such as a DMC16101A. The EEPROM may be Ib~uy~dl""~d by Lldll~ Lillg data over the network to the MIS 326 for 5~ ~hsec1uent rel~ dl ISI I lis~iUn to the CPU 440. At a non-maskable interface, the -~ ~ W0 96/03679 2 ~ 9 5 4 3 q ~ L~ . Ds lO~

Illil;lU,UlUUt~ UI 440isalso~ uu"-;~etoawatch dogtimer ~WDT) 441. The l/O intsrrupt controller 452 is also coupled to generate both audio and visual alarms and to generate the alarm cut off output. There are both major and minor alarms that are used for alerting personnel either in the office or at 5 remote locations of specific error co"di~iu"s such as loss of or instability in the GPS signal, loss of or instability in the RbA and RbB signals, etc.
Preferably, not only does the GTI 400 include its own power supply but the GTI also includes the GTR power supply 460 that it may turn on and off.
The GTI also monitors the current and the voltage for the GTR power supply over the status bus 462. Also coupled to the status bus are the monitor 410 that monitors the presence and stability of the RbA and RbB signals, the lock condition of the 20.128 MHz PLL 404, whether the ISAM engine 406 has co, I l~-k,'~d a phase measurement signaled through the BSY line, whether the 1.544/2.048 MHz PLL 408 is in lock and whether the LlU's 414 are outputting data. The monitor 410 cu, "~ ,es a one shot set for each of RbA and RbB
three 5 MHz clock periods (600 nsec) and can only be reset by the processor 440. The output of each one shots is coupled to the l/O controller 452 via the status bus 462. A low level indicates a failure of the RbA or RbB
clock.
Control bus 464 is coupled to provide control from the l/O interrupt controller 452 to various cc",,uone"b including the source for the selector 402, the enabling of the ISAM engine 408 and enabling the LIU outputs 414 and the GTR power supply 460. The ST input to the ST2 engine 408 permits the ST2 engine to perform a phase measurement and a strobe to cause the ST2 engine to store the thirty-two bit frequency data for the numerically controlled oscillator.
Also provided is a data/address bus 466 that permits the Z180 ;luylucess~ 440 to transmit and receive data from the various blocks.
In particular, the ST2 engine 406 provides the phase difference data to the I l liUI u~., ucessDl 440 for pe, iUI I I Iil lg the various matrix control O,OI~:I d~iOns to provide the Universal D: , " ,ed Time. To take the phase measurements, phase meas--rements are taken every 100 IIP' : 1d~ by using a 20 W096/03679 2 1 9 54 59 ~ 2 ~
. -22-", " - . Id timer of the processor 440.
The memory for the system is as follows:

Ske Description 128K Bytes D~ IIUd~,ldBh3 Progrsm Mcmory (Flash or EEPF~OM) 128K Bytes Data Memory (RAM) Ths ~ u~oce~:~or uses both external memory for the program and data and uses memory mapped inpuVoutput. Preferably, the " ,i~,, u~,, u~ea~ol 440 writes a thirty two bit word to the ST2 engine 406 for setting the frequency of the ST2 output while receiving phase difference measurements from the various clock sources (4KHz RbA and RbB, GPS, Loran etc.) for use by the " ,i~,, u~-, uGe~:,o~ 440 to derive the universal d~i~ ', " ,ed time. The measured phase difference from the ST2 engine for each of the phase measurements is also stored in the RAM. In particular, as noted above, the ST2 engine 406 provides the various phase measurements of table I so that the " ,i.,, u,o, uce~:.u, can determine the thirty two bit frequency value provided to the ST2 engine 406. The " ,ic, u~., uu~aSOI performs all of the manipulation for table ll above and optionally table lll to derive an estimate of the universal time. This estimate is then used for creating the thirty-two bit word used to control the ST2 to be in frequency and phase lock according to the calculations given above for equations 1 through 5.
The memory map is also used for controlling the selector 402, the real time clock 448, the time of day engine 422, the l/O InterrupVStatus registers in l/O interrupt controller 452, the interrupt mask register 463, and the two control registers, control register A and control register B, also contained in the l/O interrupt controller 460. In addition, the strobe, start and strobe lines for starting the .l~el l l lil ling of and the reading of the measured phase error between the various inputs to the ST2 engine 406 and the watch dog reset and clearing of the 1PPS 424 interrupt are also controlled by memory accesses.

~ W096/03679 2 1 9 5 d~ ~ 9 r~ ) . OSIo~

The Status/lnterrupt Register in the 1/0 interrupt controller can be divided into two bytes with allocation of the bits in the most significant byte being as follows:
Bh Name Description 7 Raserved 6 Stratum Done Indicates STZ engine 402 is Finished Measurin~ Phase Dfflerence Rasalved 4 GTR Len~th Meas. Done 0=Nommai 3 Scroll Display Pushbutton 0=Normai, 1=Depressed i 0 Z Stratum Lock Indicates STZ is in Lock Primary (RbA) PLL Lock Indicates RbA is vaiid O Reference (RbB) PLL Lock Indicates RbB is valid ,:

W09R03679 2l 95459 1~l/. ' C31~2 ~

The Status/lnterrupt Register u, ~Jdl li~dLiUIl tor the Least Significant Byte of the interrupt register is as follows:

Bit Name Description GTR No Voitage 0=normal, 1 =no voitage 4 GTR No Current 0=normai, 1 =no current 3 Output Monitor 0=nomnal, l=fail 2 GPS4i<Hz Monitor 0=normal, 1=fail 1 RbB Monitor 1=normal, 0=tail 0 RbA Monitor 1=normal, 0=fail The mask register provides acld~ dblt~ masks so that interrupts can be deactivated by the IlliuluiJluceaaul and the mask bit mapping for the 15 mask re~iister is the same. The masked output is coupled to Interrupt number 1.

~ W0 96/03679 2 1 9 5 4 5 9 llle Hardware Control Register A Most Significant Byte is as follows Bit Narne Description 7 Fail LED

6 Status LED
10=green, 01=red, 00=ofl, 11sofl 4 Output LED
10=groen, 01=red, 00=ofl, 11=off 2 Activity IED 0=ofl, 1 =ofl Reserved 0 P~eserved WO 96/03679 2 1 9 5 4 ~ 9 r~l~u~ .O~ ~

The Hardware Control Register A least signifir ant byte is as follows.

Ba Name Descrip~ion 7 Major Alarm 0=normal, 1=slarm B MinorAlarm 0=normal, 1=alanm Status Alarm 0=normsl, l=alarm 4 ACO 0=off, 1=on 3 ACO Clear 0=off, 1 =on 2 Reserved Rese~ed 0 Reserved W096/03679 r~ 16 The Hardware Control Register B is as follows:

Bit Name Description 7 MIS RTS 1 =rer~uest to send .

MIS TX Enable 1 =enabled 6 OutputEnable 1=enable 0=dlsabletortheLlUs.

4 G rR Power On 1 =on 0=ott s Sync Serial Port Enable 1=enable 0=disable 2 Syn~SerialPortSelect 1=framcr 0=other Retorence Select Mux Bit 1 Select Input tor 20.128 MHz PLl o Reterence Select Mux Bit o Thus Figures 6 and 7 show an ~IllbO~.lillltlllL of a clock distribution system providing a universal ~ led time scale as a local primary reference source for an office or the like.
Although the speciflc elllLJOdillltllll was described beiny done v~ith digital Lt:ul " luluyy, it would be readily Ul ,d~, aLuOd that the various en IL,o.lil 1 I~Uts could be in ~le~ l IL~d in whole or in part using for example voltage controlled oscillators in lieu of NCO s and phase detectors in lieu of tjme measuring devices. In addition various other crj",~u"t:"t~ may be 20 modified as will be readily Ul Id~ ,Luocl by those of ordinary skill in the field.
Also although the specific e",L odi",e"L~ are more particularly directed to Lt~ oo,,,,,,unications the t:"~L~odi,ll~l,b may be used in local and wide area computer networks and electrical power distribution networks. The scope of the invention is of course defined by the claims.

Claims

1. A method of attaining syntonisation between a local clock and a universal time source, wherein the universal time is transmitted via a signal over a medium that is subject to adding linear and non-linear noise effects to the signal, the method comprising:
providing a plurality of constituent time clocks, each time clock providing a clock signal at the output;
ensembling the outputs of the time clocks to provide ensembled time clock information, wherein the ensembled time clock information is more stable than any of the constituent time clocks;
receiving the universal time clock signal repeatedly determining the difference in frequency between the universal disciplining clock signal and the ensembled time clock information; and generating from a plurality of said frequency differences and at least one of the constituent time clocks and the ensembled time, a clock signal at the same frequency as the universal time clock signal.

2. The method of claim 1, wherein the method further comprises providing a receiver adapted to receive a global positioning satellite timing signal to provide the universal time clock signal.

3. The method of claim 1, wherein the method further comprises providing a receiver adapted to receive a Loran timing signal to provide the universal time clock signal.

4. The method of claim 1, wherein the method further comprises:
providing a time measuring device having two inputs to provide information representative of the phase difference between the two input signals repetitively selecting different constituent clocks as a first input to the time measuring device and providing the information representative of the phase difference between the output clock signal and the selected one of the constituent clock signals; and producing a data matrix based upon the information from the representative phase differences for use in ensembling the clock signals.

5. The method of claim 4, wherein the matrix comprises a pairwise matrix.

6. The method of claim 4, wherein the matrix comprises an incremental pairwise matrix.

7. A time scale generator having:
a plurality of local clocks, each local clock producing timing information, the timing information having a level of reliability and stability;
an ensembler responsive to the plurality of local clocks to produce time scale information, the time scale information having a level of reliability and stability greater than the levels of stability and reliability of the timing information of each of the local clocks;
a receiver adapted to receive from a communications channel that is subject to adding linear and non-linear noise to a universal disciplining signal having timing information therein;
a universal disciplining clock signal generator producing universal disciplining clock information having timing parameter information in response to the received signal; and a means for disciplining the ensembled time base information to the timing parameter information of the universal disciplining clock information to provide a disciplined output signal.

8. The time scale generator of claim 7, wherein the universal time clock information is a universal time clock signal and the ensembled time information is an ensembled clock signal and the generator further comprises:
a time measuring device to provide information related to at least one of the frequency and the phase difference between the ensembled time clock signal and the universal disciplining clock signal;
a controllable oscillator responsive to the ensembled time clock signal and control information to produce a clock signal based upon the ensembled time clock signal and the control information; and a controller responsive to the output of the time measuring device to produce the control information for the controllable oscillator such that the output of the oscillator is frequency disciplined.

9. The time scale generator of claim 8, wherein the controller averages the information from the time measuring device over a lengthy period of time.

10. The time scale generator of claim 7, wherein the generator includes a processor that performs the programmatic steps of:
producing pairwise data for each local clock and the universal disciplining clock signal;
producing data representative of the ensemble state based upon the pairwise data for each local clock;
determining the difference between the ensemble state and the universal time clock signal at various points in time to obtain an average difference; and outputting a clock signal based upon the difference between the ensemble state and having the long-term frequency of the universal clock signal based upon the average difference.

11. The time scale generator of claim 10, wherein the pairwise data is incremental pairwise data.

12. A telecommunication network having a plurality of switching offices having a plurality of local clocks having a frequency with a stability and reliability, wherein the telecommunications network exists in an area that receives a signal over a medium that is subject to adding errors to the signal containing universal disciplining clock timing information having a frequency, wherein the improvement comprises at a plurality of at least some of the switching offices:
a means for ensembling the plurality of local clocks for that office to provide ensembled time base information having a frequency and the ensembled time base information having a reliability and stability greater than each of local clocks for the office;
a means for determining repeatedly the frequency difference between the ensembled time base information and the universal time base clock information; and a means for providing a local time base signal for use by the local office having a frequency based upon the average frequency difference between the ensembled time and the universal time clock information, whereby the local time base signals at said each of the plurality of switching offices are in syntonisation with each other.

13. The telecommunication network of claim 12, wherein each of the local time base signals is a four kilohertz clock signal.

14. The telecommunications network of claim 12, wherein each of said plurality of switching offices has a receiver coupled to provide the universal time scale information to the determining means.

15. The telecommunications network of claim 12, wherein the means for determining at least a plurality of comprises a stop/start counter.

16. The telecommunications network of claim 12, wherein the means for determining at least some of the plurality of comprises a phase detector producing a signal dependent upon the frequency difference.

17. The telecommunications network of claim 12, wherein the signal containing the universal time clock information is a GPS signal and each of said plurality of has a GPS receiver providing the universal time clock information to the determining means.

18. The telecommunications network of claim 12, wherein a clock source from a first is also used by the means for ensembling to provide the ensembled time base information.

19. A method of providing in a network comprised of a plurality of nodes transmitting units of information between each other, wherein the network being located in an area where a signal including universal time clock information is receivable through a medium that is subject to adding errors to the universal time clock information, syntonisation between a plurality of the nodes, the method comprising:
generating local clock information at each of the plurality of nodes;
receiving the universal time clock information at each of the plurality of nodes;

determining at each of the plurality of nodes from time to time the frequency difference between the local clock information and the universal time clock information;
generating based upon a plurality of the determinations said syntonised clock signal at each of the plurality of nodes having the same frequency.

20. The method of claim 19, wherein the network comprises a telephone network.

21. The method of claim 19, wherein the network comprises a data local area network.

22. The method of claim 19, wherein a plurality of the nodes in the network comprises a telephone switching office.

23. The method of claim 19, wherein the local clock information comprises a plurality of local clocks at each node in the network.

24. The method of claim 23, wherein the method comprises:
determining at each of the plurality of nodes the frequency difference between at least some of the local clocks repeatedly;
producing based upon the frequency differences of the local clocks ensemble time information for each of the plurality of nodes;
generating repeatedly second frequency difference information between the ensemble time information for each of the plurality of nodes and the universal clock information;
generating based upon the second frequency difference information at each of the nodes a clock signal syntonised to a clock signal at each of the other plurality of nodes.

25. The method of claim 24, wherein the ensemble time information for at least some of the plurality of nodes is based in part upon a local clock located at another node.

26. A method for disciplining an ensembled group of clock signals to a universal time source signal provided over a channel having both linear and nonlinear noise effects, the method comprising:
using a time scale algorithm on information relating to the group of clocks and the universal time source signal to provide state estimates of the difference between an ensemble time and each of the group of clocks and to provide an ensemble time state with no weight being given to the universal time source signal in the ensemble time state;
disciplining the ensemble time state to the universal time source signal through a low pass filtering algorithm to provide a disciplined time state; end generating a clock signal based upon the disciplined time state.

27. An apparatus for disciplining a collection of clock sources to a universal time scale received over a noisy channel, the apparatus comprising:
a controllable oscillator providing as an output a clock signal disciplined to the universal time scale; and a processor responsive to each of the clock sources and the universal time scale to provide an ensemble time scale giving the universal time scale zero weight and using the difference between the ensemble time scale and the universal time scale to control the oscillator.