CA2204005C - Wafer-stage temperature compensation for ic components - Google Patents

Abstract

An integrated circuit has at least two components described in the form of two ideally matched transistors, each of which operate interdependently as a function of temperature and at least one physical parameter associated with each of said components when implemented in integrated form. The circuit further includes compensation means (Q9-Q16, R2-R4), disposed in the integrated circuit, for generating and applying a bipolar compensation signal (Isym) to at least one of said components (Q6) so that said two components interdependently operate predictably, consistently and independently of temperature variations and differences between the physical parameter of said two components. The bipolar current is necessary so that both the level and polarity of the compensation signal can be appropriately adjusted during the manufacture of the integrated circuit as a wafer so as to eliminate the need to compensate for any mismatches in the two components following such manufacture.

Description

WO g6/1S586 PCriUSgS/lS442 WAFER-STAGE TEMPERATURE COMPENSATION FOR IC COMPONENTS

Eield of the Invention

2 The present i~ tion relates generally to the coll~,clion for ~ rh~5

3 lxl~. ~en or among h~ )cla~c; ~ P lll circuit colll~)ullc~l~ of an integr~ted circuit,

4 and more particularly to the adj~ P ~1 at the wafer stage for the coll~ ion ofS certain ,;~ hf s ~lwccll or among circuit colll,uo~ t~ which are a part of the6 same ;--t~ t~i circuit structure and which for operational ,uul~oses are r~luir~d to 7 be ~ hr~ over a lf-~ range.

9 ~k~ound of the Invention There are many circuit designs which include circuit CO111~UO~C11~ both active 11 (such as l-. --~: to,~) and passive (such as l~Si~LUl~), which are required to be 12 ...~trl-~A during their ope~,.l;ol-, over a telll~lalule range. Where the circuits are 13 co~lluct~d of dis~ co",l~on~ , if l~f~ for opt;---;~;--g system ~.rullllallce, 14 ,-,~ typically must be made during the m~nllf~rtll~in~ ~locess when 15 ass~ubling the circuits to insure col~ollclll ".llrlling. This can be costly due to the 16 labor lhluu~,d to make the ~~ 1 for each m~mlf~tmed circuit. Often times 17 such a~ r-.l~ provide CfJll~tiOIl only at the tcnl~c~alul~ at which the initial 18 ~lj--~l,~ ,l is made, which may not be ~ r~tuly for other ~)perational 19 t~ alul~s. In ~d~1itiQn~ some settings may be subject to shifts due to n~fh~.~if~l vil)l~1;n.~ these circuits in inte~,àtcd or ~onolithic form often 21 .~f~ . ;ly ,. ~lu~l~ s the provision of e Ytf rn~l cil.;uilly for providing these 22 ~~lj--~l---~--l~ following the m~mlf~~1llre of the IC part, but does not u~e~collle the 23 above-noted problems.
24 For example it is well known that the class of electronic gain control circuits known ~ log-antilog electronic multipliers or VCAs (voltage controlled 26 ~ .l;r.~ ui~cS a~lj--~l-- nl means (generally lefe.l._d to as ~y~ el~y 27 adj~ -.f) to coll")e~alc for ~ rh~s among the various l.~Si~O~ that 28 Il,le.l~ l the gain-control function. The re4uilcl~ ll for such adjllctm~nt is 29 ~. n~ioned in U.S. Patents Nos. 3 714,462 and 4 403 199 issued to David E.
SUBSTITUTE SHEET (RULE 26) WO g6/15586 1 ~ s442 Rl~L ",t~, onJar~lary 30, 1973 and September 6, 1983 ~ ly; 4,234,804 issued 2 to Gary I3~r~ ulll on November 18, 1980; 4,331,931 issued to Robert W. Adams 3 on May 25, 1982; and 4,225,794 and 4,341,962 issued to Paul C. Buff on 4 Sept~-.. kl 30, 1980 and July 27, 1982, l~ ly. This adj~ as

5 hi!~lu- ;r~lly been made via a potentiomt~ter and acsoci~d fiAed l~ u~, arranged

6 to apply an adjustable pot~ial to one or more of the bases of the ~ ul~ in the7 gain-control circuit. Such an ~dj~,l...r..l m~thod is costly due to the parts 8 ll~ celves~ and the labor l~luil~d to adjust the potçnti-....- h~ during the g ",~.,-,r~t~ c~s~ of each circuit board. Further, such mt~thtulc often yield a 0 COll~liOll ~Gl~-l1;al that is only correct at the t~ at which the initial 11 adj~ was made. Finally, the potPntinmPter setting is subject to s_ifts due to 12 ",t~r~ iral v;l~
13 The most prevalent .. ~de .. IA~1~1eS of such gain-control circuits are 14 ;,,.~ t~ ed in mt nt lhhit~ IC ter1-n. logy, which is well suited to these circuits ac 15 t_ey require well~ A l~ ~n~ ~lu. . that operate at ~b~l .n;~lly the same 16 t~ . An t~ k- of a VCA is shown in Fig. 1.
17 The VCA shown in Fig. 1 inrllldes an eight ~ lol cell. Eight l.~ or 18 cell VCAs are known. See, for ~Y~mple~ U.S. Patent No. 4,331,931 issued to19 Robert W. Adams on May 25, 1982 and U.S. Patent No. 4,341,962 issued to Paul C. Buff on July 27, 1982. As shown in Fig. 1, an input hlrol.. al;~-n signal (e.g., 21 an audio signal) I," is applied to the input t~rmin~l 10. Termin~l 10 is co,~Pcled to 22 the coll~tor of plill~ log (pnp) l~nC QlOI Q3 and the collector of the pl,ll,al~ log 23 (npn) ~ or Q5. The coll~tors of pl~y antilog ~ o.s Q4 and Q6 (pnp and 24 npn l.,..~ U~ s~c~ti~,ly) are joined at j~ l;on 12 so as to form output ~ inal 25 14 for output current I~,~. One gain control signal is applied to the po~ilive-sense 26 gain-control port 16 as E~p, and to the neg&live-sense gain-control port 18 as E~
27 The syl~ .,h~r adjust signal E""", is applied to the ~1~ port 22. As shown, the 28 ~o~ control signal input t~nninql 16 is conl-Pclr~ to the base of the ~lilll~ log 29 ~ Q3, while the ~egaLivc control signal input t~ ....in~l 18 is cG..n~cl~d to the 30 b. se of pl.~ log ~.A~c;~lor Q5 and ~lilnal~ antilog Ll~siSlol Q4. The emitter of 31 each ~ lol Q3, Q4, Q5 and Q6 is co.. ~ ed to the emitter of a l~,*,e~Live 32 seco~ A~ OI Q" Q~, Q7 and Q8. with each secolld&l~ l~An.C;~IOr being of a SUBSTITUTE SHEET (RULE 26) WO g6/15S86 PCIrUS9S/154A2 cc..~ ity type 0~)05ill~ to that of the ~ h~ ol to which it is co...-Pc~l 2 The bases and collectors Ofl~ ol~ Q, and Q2 are tied together, and cimi1~rly the 3 bases and coll~ctors ofllA..c;clu~ Q7 and Q8 are tied ~oge ller. A voltage bias source 4 Vb,~ is col-n~ d ~h._~ the bases and collectors ofl~A..~:~o.~ Q, and Q2 and the 5 bases and collectors ofl~ lul~ Q7 and Q8. In addition, the bases and collectors 6 ofllA--c:clol~ Q7 and Q8 are col~f~h ~ to a current source i~lir~t. ~1 as Ipo~~ The

7 input If ~ l 10 is also con~ .f ~ led to the ilvel ~g input of op~r~tionql amplifier 20,

8 with the non-h,~ ing input cc.. ~t~l to system ground and the output con.-~d

9 to the bases and coll~ctors ofl.~ Ql and Q2.
In g~n~pl, lJCCa~lSf of the log~ l.. ir rel~l;ol~ch;l, ~et~ ,n base to emitter11 voltage Vbc and the collector current Ic of a bipolar ~AI.~ or, the log !~A.~ ol~ will 12 provide a voltage signal at the coll~tors of the secondary l.~.lc:~loli which is 13 propollional to the log~ l---- of the input current. The antilog I~A~;CIOI~ will 14 ~Jrovide the output current Io~ as a r - .- Iic"- of the antilo&A. ;11---- of the voltage signal.
15 nee~ cr the control voltage Ec is applied to oppos~g polarities of both the log and 16 antilog IIAII~ ~IO1~, v~ing Ec will vary the ratio of the output current Iout to the input 17 current Iin. The s~ ehy adj~l.... n sigDal, E""", is applied to the ~y~eh~ adjust 18 l~-.--;--~l 22. The le~luile,ll~t for s~ llleh~ l arises from ...i~ s in 19 the base-to e~ voltage (Vbc) - coll~rtor current (Ic) cl~ r~ I;r-s among the log 20 and antilog l.~ o.~ in the gain-control circuit. This may be seen by obs~ ing21 Fig. 1 and the VCA ~r~. filn~ti~n 22 (1) I = G v l~e 2v~ b ¦~ 2VT
ou~ 2 ~ ~ I5~ 15~I53) '\ 2 G ~ ~ I55/J, 23 ~l~,~iin I~" is the VCA output l.;U
24 Iin is the YCA input ~;u~ E~_E~
G is the nomiTlAl VCA current gain ~e 2VT );
26 E~p is the pot~ial applied to the po~ilive-sense gain-control port;
~ 27 E~" is the potential applied to the negative-sense gain-control port;
28 E~ is the potential applied to the ~ ~ eLI,~ POrt;
29 IbiS the n--min~l bias current in the logging and anti-logging ~ e;~ol ~i when the gain-control circuit is set for unity gain;
SUBSTITUTE SHEET (RULE 26) W O96/lSS86 PCTnUSgS/1S442 VT = kT is the ~ 1 voltage", a CO~ pr~ollional to the ~bsolute 2 Ir.n~ (PTAT); and 3 Isl through Is8 are the le~ salulalion ~Ull~ for the logging and anti-loggir~ C~ Ql through Q8.
6 If all of the individual log/antilog pairs of l.~.~c;clu,~ (Q,/Q2, Q31Q4, Q51Q6.
7 and Q7/Q8) are i~entir~lly ~ 'h~l for their Vb, - Ic c~ tp-rictirs such that:

9 (2) Isl = Is2~ Is3 = Is4~ Iss = I,6, and Is7 = I
11 and Es~ is set to equal Ecp~ then eq~1~tion (l) reduces to:

13 (3) Io~ = GI,...

15 which is the ideal case in which the output current is a linearly scaled version of the 16 input current. In l,la -lice, ho..~ , there exist ...;Q... h h~s among the pairs of 17 t..~n.Q;~ , such that, witlluul proper adj~ of the potential E,~" the output 18 current will consist of, in ~ n to a scaled version of the input current, second 19 h~ ;f d~lullion and gain~-,~n~ dc offset Cûlll~OL~ s~-~1~1 by the second term in e~ ;on (1) l~luced as follows:

22 (4) I2 I2 E""" - E~ 1s21s4 23 ~ 2 G ~ \ Is5ls7 '\ IslIs3~
24 These disl~l~n and gain~ 1 offset co~l,o~ ~ are undesirable in high-25 quality audio app1ir~;ol-Q-, as well as other ap~ ;ol-~ where a faithful scaled 26 replica of an input signal is desired.
27 It is possible to plùl clly adjust E""" to cû.. l~lctely el;~in~le these undesirable 28 CGlll~Ol~ i in the output signal. E~"" must be adjusted such that the second term 29 in ~-I;ol~ (1) goes to zero. Thus, it is desirable that:
3 l (5) E~", Ecp 32 ~ Is5Is7 '\ IslIs3 SUBSrlTUTE SHEET ~RULE 26) WO g6/15S86 PCr~USgS/lS442 Solving for Es~nn 4 ym P ~ I,I31d~8 S In practice the ~lo~ c1~ achievable with m~Aern IC pfocesses is 6 such that the desired Es9" potcllLal is no more than a few millivolts dirr~ from 7 Ecp with E~p typically being in the range of -700 to +400 millivolts. Thus, it is 8 co~ ie.lt to consider the dirr~r~ cc beh.~.l these two ~ot~ c:

1l Eod~ = Es~ Ecp = 2V~n Is s s 57 12 as the desired -Aju~ )ote lLal. From the fol~,gohlg it can be seen that beca.lse 13 V~ is plo~olLo~l to absolute ~ the l~ Uh~d E"dj also must be 14 ~lupo~lional to abso?ut~ temperature (PTAT).
It should be noted that the circuit used in d~,.iving the equations above is used 16 for illustrative ~ullJG~S. The effects of base l.;U~ i, Early effect, and non-ideal 17 log collrullllàn~ due to finite ohmic base and emitter l"~ Ps in the logging and 18 and-logging !-~ ;C~ul~ have been ignored for clarity. The t~hni~les taught in US
19 Patent No. 4,234,804 (Ik.~llulll) and US Patent No. 4,403,199 (Rl~L~ ,) to 20 ;I;g~P the effects of finite ohmic bace and emitter r~C;r~ r~s in the logging and 21 anti-lo~ging ~ are entirely c0~ ,1c with the invention to be desç~ ;hed, 22 and in fact serve to bring the behaviol of actual gain-control circuits closer to the 23 ideal behavior of the simple circuit d~,~ ;l~d in Fig. 1. The same is true of the 24 terhniT~e taught in US Patent No. 4,454,433 (Welland) for ,,,;I;g~ the effects of Early effect .n;~ tfh among the log and antilog l~ o. i. For gain-control 26 circuits utili7in~ a cell of only four ~ C:-h-.~, such as that d~sc~ ed in US Patent ~ 27 No. 3,714,462 (Blaclaner), it is easily shown that the l~.lUil~l Eadj is of the same 28 form as that of eq latinn (7) and that the present invention is equally applicable to 29 such circuits.
In comi~P~in~ the prior art, as each gain control circuit is made it is not 31 .~ce~-. ;ly known ~L~ E"d; should be a posilive voltage, or a l~galiv~ voltage.
32 The log ~ , as well as the antilog ~ ul~, are m~trh.o.d as closely as SUBSTITUTE SHEET (RULE 26) WO g6/lSS86 PCTi~SgS/15442 possilJ'~ so that any ...~ ng is l~ .e5~ y u~~ ktble and ~ ." This 2 would suggest l~,e~le that just as many circuits would require a pOsili~ E"d; as 3 would require a l~gdliVe E,dj. Accoldillgl~, the source of E"d; not only should 4 include the means for adju~ling the level of E,~,; in order to correct for Vb, - IC
S mi~m~~t -h~s, but also for ~ ~ cti~ the polarity of E,dj so that E9dj can be made 6 ~osili~_ or l~aLi~e. The most co.. n prior art ~loach for a~ s~ E,dj to the 7 desired polarity and value is ill~ A in Fig. 2. A le~ l Rl is cQI~n~t~l ~t~n 8 the bases of antilog ! . ~ lor Q6 and log ~ lor Q3, and a l~ or R2 is col-l-~
9 be~. ~n the base of ~ tor Q6 and the wiper of a lJOh ~ t~ R3. The ends of

10 potentiomPtpr R3 are c~ ~t~.~n pot~ lC VpO5 and V",g (typically, but notf~:SS~;ly, equal and oy~osil~ voltages) to create a variable ~ot~ idl at the wiper.
12 The values of these co~ o~ t~ are typically chosen such that the ~ of R213 is much larger than the l~,s~ e of R3, and the ratio of R2 to Rl is chosen to14 restrict the range of voltages across R~, to the few millivolts .~ to coll~tl~/
15 adjust the VCA sy~ . Further, R~ is typically chosen to be less than 100 ohms16 so as not to add excessively to the base l~ f~ of antilog l.~n~ Q6. Finally, 17 Ecp is typically driven by a very low-;~ r~ voltage source. Under these 18 con~litio~ E""" may be a~lvx;~ l by:

(8) E = V ~ R, ~ + E ~ R2 ~
21 ~Rl+R2) CP~RI+R2) 22 where V,r,p" is the voltage at the wiper of R3. The net ~voltage E"d;
23 developed across R, will be:

/~E~ = E~ - Ey = V~I~R +IR ) + E'P¦R +R -1~ = (V~ Ecp)lR +R ~

27 The S~ u~ l is typically made with Ecp and ECD both set to 0 28 volts so that the current gain of the VCA is unity. As can be seen from e(lu~lion 29 (9), if the posilive-se~se gain control port 16 is then used for ~dj~cl;,~g the gain of the VCA, either in co,~ cLion with or instead of ~e ll~aLivc-sense gain control 31 port 18, the E~; put~ ial will deviate from the desired value as the E~p potel,Lial is SUBSTITUTE SHEET (RULE 26) WO 9611SS86 PCIlUSgS/15442 varied. This leads to degraded d~t~llion and offset-versus-gain p-,lr~ at gains 2 other than unity.
3 When this t,~ hn; l~J~ is ;.. l l~ tl ~ using discl~t~ ulle l~ for R" R2, 4 and R3, applo~ ' t ~ , co~ ~l;nn of the E,tj ~t~ l can be ~chi~ed 5 by using a ~ e ~ r~en~ l resistor for Rl. If R2 is much larger than Rl 6 (which is typically the case) and R,'s value varies .33% for every one deg~ee 7 centigrade vq-riqtirn from room ~ c while R2's value l~ai~ fixed, then E,dj 8 will vary appl."~ ly in PTAT fqQhir,n Of course, it is ~liffirnlt to ensure that the 9 discl.,le l~ lur stays at exactly the same t~ -..~-Ah~.., as ~ ul i Ql through Q8.
10 While ;..t~ the l~ s onto the s~ne IC with the !-~--.'; 'OlS might solve this

11 problem, it is ~liffir,ult with current IC technnlogy to fabricate hl~E5la~d l~ u

12 with ~pe~;rr, well-controlled t~ e~ .e co~îr.

13

14 Objects of the Invention A p.;.. ~;~ql object of the present hl~ ioll is to reduce or ~b~ lly 16 u~ colllc the disadvantages ~le.,--~ d above in co.~ ct;n~ with the prior art.
17 Another object of the present i~ tion is to adjust at the wafer stage for the 18 CC~ c~ion of ",i,~",A1.-h~s b~h.~n or among circuit colll~o~ t~ which are a part of 19 the same ;~t~lA1rA circuit s~ , so that the Co~ o~ are ..~ h~ over a 20 t'----lU-io~ C range.
21 And a~u~cr object of the pre~nt in~e~iûll is to plu~ride means, on the same 22 i..t. ~ . A circuit i lcol~ol~ting a gain-control circuit, for ~lc,~idi~g proper ~ lllCLI~
23 A~ for .n;~qt~h~s in the Vbc - IC cl~ ;r.~ beh. ~,n or among l ' ;"-~;~lU-?
24 in~ 11y Of h.~ _.;A1;.~
25. Still ar~ . r object of the present inv.ention is to ;~... l,l~--.. ~n~ a gain control 26 circuit of the type having two gain control ports so that ~yl~ ,hy .~ l."rl is 27 , rr~ by the pot~ ~tial at either of the two gain control ports, thus leaving them 28 both available for use.
29 Yet a~ llel object of the present i l~ioll is to exploit the use of l~ ~;clul~, f~bl;- ~tn~ in accol~ce with IC .-.. r;~ te~hn~ C, that track over a wide 31 range of ~.~ s, in providing ~eh~ 71j--~1-"~ for a gain control circuit 32 i...~ ...t.~ in IC for n.
SUBSTITUTE SHEET (RULE 26) WO 9611SS86 PCIiUS9Srl5442 ~ -8-And still a~ er object of the p~ 1 invention is to plu~ride an ~ lct~hle 2 bipolar ~y~ letly ~lj..cl.,.r.,l signal to one or more h~ ols of a hA~ tor cell of 3 a gain control circuit so that the polarity and level of the sy~ adj~ signal 4 can be a~propl;~t"l~ adjusted during the manufacture of the gain control circuit as S a wafer so as to ~Ubs~ ly el;~ the need to col.&~ e for any lic~lrhf s 6 in the ~ ;cto~ ~ following manufacture.
7 And yet ~tL.,l object of the present invention is provide a ~y~ ,h y adjust 8 signal to a gain control integrated circuit, ;. ~lfpen~f--l of the absolute power supply 9 used with the ;--t E,;~t~ circuit over a l~co.~ e range of voltage levels of the power supply.

12 Summary of the Invention 13 These and other objects of the invention are achie~d by an ;l~t~ f-d circuit 14 of the type having at least two CU~ JU1~ each of which operate i~ Gpen~ ly

15 as a fim~tion of ~ , and at least one physical ~ h ~ ~coci~ d with each

16 of the Colll~o~ when ;.-~ -.t~1 in ;~.t~.A~A form. The circuit furlher inrhl-les

17 co---pe - -I ;~n means, ~ in the ;--t- ~ 1~ circuit, for generating and applying

18 a bipolar cu. . .l.e~Q~ ~1 ;- ... signal to at least one of the coll,l)o~l~ so that the level and

19 polarity of the bipolar Cu--.l,f-~ signal can be ~ during the ~ri ~~e of the ;l~1~gl~led circuit such that the two col,.yon~"l~ inter~n~ ly operate 21 predictably, c~ t -nly and ;~ f~ly of t~ e v~ri~tion~ and dirr~,e~ces 22 ~l~n the phy~icdl y~ h- of the two COlllyO~t~.
23 Preferably, the integrated circuit is of the type that Cn~ f,S a gain control 24 circuit for genf. ~ an output signal as a r~ ;on of the y~ c~ of an input signal 25 and a gain control signal. The gain control circuit ;rl~ Fs at least two ~
26 l~uh~d to be -I~-hf~ so that the opc ~.1;ol~1 ch~.qt~ s of the ~ u~ are 27 i-1Pntir~l in order to ...;n;~ . signal distortion by the gain control means. In 28 accol~ce with the present h~ lioll, the ;.,t~ d circuit further inrh~d~PS means, 29 disyosed within the il~t~ t. ~3 circuit, for ge~ a bipolar signal for providing ~y~ llt tly ~1j.-~1.. - -~1 beL-._e,- the two ~ UI t as a Çu~ ioll of any .. ;~ cll 31 ~ n the Vbe - Ic ch~ -t~ ;rs of the L~ tul ~ so that the Lli. n~ ol~ operation 32 is ~ rh~ indepen~l~ontly of L~,..l~c.alule ~ I;on~ and the gain control signal.
SUBSTITUTE SHEET (RULE 26) WO g6/lS586 ~ ).,3~115442 Brief Description of the D~
2 Fig. 1 is a SC~ I;r ~lia~m of a example of a prior art gain-control circuit 3 of the voltage controlled ~mplifier (VCA) type employing log-antilog pairs of 4 I-d~ OI:~i and sLuwillg the need for ~ l ~eh~ ~dj~
Fig. 2 is a scht m~tir t'~ of the gain control circuit shown in Fig. 1 and 6 .~n~;r.~d in acco~ ,vith a prior art t~rr~ of ge~c.~ling a Sy~ adjust 7 signal;
8 Fig. 3 is a s~bt . ~;r ~ --n of a first ~-,f~,-l~ embo~lim~nt of the present 9 in~e.ltiUll for providing a ~ llue~ adjust signal as a filnrtion of a c~ .rC~c~ n 11 Fig. 4 is a sc1.f~ ;r fliqgram showing a general i,ll~lc~ ;on of a bipolar 12 current source for ~ the S~ h~l adjust sigDal;
13 Fig.5isa Sh-~ t;r~ show~amoret3Pt~ilP~ r~~nofone 14 of the current sources shown in the Fig. 4 e~.lbo~l;r-~1, Fig. 6 is a sC~ ;r tliq~m i.howillg a more ~et~iled i,l~ ion of the 16 Fig. 4 ~,ubo~;~.d;
17 Fig. 7 isa ~1~ ;r ~liak~ huw~gamore~l~Pt~i1P~ /lr l~ ;ol~ofthe 18 Fig. 6 embo~imPnt and the pl~f~ cd P- "l~;"' - ~t; and 19 Fig. 8 is a sCl~n~ r ~ .. of a second ~l~f~let embo.1;.. ~ ~~ of the

20 present i~ tio~ for l)rovidi~g a ~l~ h~ adjust signal as a filnrtion of a

21 a~ul~;n~-l;nn current.

22

23 Detailed Desclipt;on of the D~

24 In the ~llawi~s~, the same letters and .~ are used to id~ tir~/ the same or similar parts.
26 A pl~f~lcd l,~bo~l;n.P .I for achi~,i~ proper s~ a~j~1stmPnt 27 ;- -~l~ pr~enl of t~ e variations and gain-control voltages is i1111~tr~tPd in Fig 28 3. In this c.llbo~ fn~ a variable current source I""" is co~m~ d to the base of 29 antilog ~ ;clol Q6. replacing the resistor R2 and potentinmpter R3 shown in Fig 30 2. The ~agi~ P of I~ is ~ropollional to VTtR where R is a l~-s;~ ce having 31 ch~i '-t~ ;~I;r~ (prim~rily l~ atu~'~ cCse-rr~ ) ".-Il,;"~ those of R,. The 32 re~~llting Syl~ ,hy adjll~tmPnt pul~lltial E~d; Will be approxim~tP-ly:
SUBSTITUTE SHEET (RULE 26) W O gC/lSS8C P Cr~ SgS/lS442 (10) E,~ = Es~ ECp = KVT( R ) 3 if I5ym iS much greater than the base current of llal~Si~ls)l Q6.
4 A bipolar current source circuit with such rhq~ct~ irs, and which can be 5 imple ..~ in IC form, is shown in Fig. 4.
6 In Fig. 4, a po~ilive current source 30 provides a posiLive current A into 7 jlml~tinn 34, while the ~ega~ive current source 32 provides a negative current B from 8 j.. ~ ;r.l~ 34. The sources 30 and 32 are ~e-signP~l so that the output of each is 9 ploi)vlLional to VT/R. Thus (A - B) is propollional to VT/R v~L~IllcL the mqgni~
10 of A is greater than the mq~i1llde of B (A>B), or the .~ Jde of A is less than 11 the magni~e of B (A<B). The exact value of A - B is Isym~ and as described 12 above Isym is ~lupolliondl to VT/R where R is a l~ re having characteristics 13 (prim~rily t .~ coerr~ 1) " ~ ,;~ those of Rl of Fig. 2. One such 14 e; ...plf of a known unipolar current source for ~lo.~iding a current pç~pollional to 15 absolute ~.~ dture is ill--'l.~t ~'3 in Fig. 5.
16 In Fig. 5, a pair of npn l ~ ;C~o.~ Q~ and Q2 are connP~It;d so that the 17 coll~tor of !.~ ~r Q2 l ~ ;~-,S an input current I"" while the collector of 18 ~ lor Q~ provides the output current I~t. The collector and base of ~al~ or Q2 19 are tied lOg. Il.rl and to the base of 1.~ tOl Ql with the voltage at the jull~lule 20 being defined as V3. T~ Q3 and Q4 are also provided, with the collector and 21 base of l.~ or Q3 CQ~ t~ d ~ ly to the base and collector of l.~ or Q4, 22 with the emitter of ~ lor Q3c~....f..t~d through resistor R to system ground, and 23 the emitter of l~ C clor Q4 C~ ~r~l_A to system ground. The emitter of tr~n~i~tor 24 Qlisc~ t~ to the co~ector of haL~t~l Q3, and the emitter of ~ lor Q2is CQ--~ *~l to the collector of ~ ;clor Q4. The voltage at the julll;lul~, of the emitter 26 of !-,.--.~- -t ~1 Ql, the base of l~ t~,l Q4 and the collector of h~ lor Q3is defined 27 as V2, while the voltage at the jUll.;~ of the emitter of !.,..-c;clor Q2, the base of 28 I~A~ J~l Q3 and the co~ector of ~ ;cto~ Q4 is defined as V,. ~c~lming that 29 1 -ictors Ql, Q2, and Q4 have i~Pntir~l cbku~t~ I;rs(inr1~ n~ saturation current 30 I,) and that h~n~ lor Q3is similar, but with emitter area A times larger than the 31 other three, and i~ base ~;ull~;n~, the following can be stated from ~cl~e~;lion 32 of Fig. 5: SUBSTITUTE SHEET (RULE 26) WO g6/lSS86 PCT/US95/15442 (11) V~ = IoU,R + VTln( 3 (12) V2 = VT In(I ) 6 (13) V3 = V2 + VTh1( I ) I T (I5~
7 S~bs~ ;0g the first two eqll~tion~ into the third yields:

10 (14) Vrln(~ + VT~(I~~) = I ,dR + VTln(1~~) + VTln(l~) 11 and solving for I~":

(15) VTln( I ) Io~ T (AIs) (16) IO~ = -RT~L4 17 It should be noted that the as~lion that base CUI~ lki may be ignored in the 18 folegoillg analysis will be valid if the ~ de of I", is of the same order as that 19 of Io"l. It should also be noted that small "~ tr1.r-s among the t~i~n~;~i1u.~ will have the effect of slightly ~1tP.rir~ the value of the con~ A.
21 A current source such as that shown in Fig. 5 will not fulfill the ~ uil~ .nls 22 of I,9", in Fig. 3 because I,~", must be b,dil~;liollal or bipolar. That is, it must be 23 ~dj1~t~l le to both ~o~ilive and ~ 1ive values of current since the l~ Ui~d 24 ~~ l-.n1 pot~al E,~j rnay be l)osilive or negative. Fig. 6 shows an embo~limpnt that fulfills all of the ~ uil~lle~ co~ c1~A. to an eight l ~ lol cell gain control 26 circuit.
27 Refe.li~g to Fig. 6, the current source inr.h1-lP.~ a positive voltage rail Vpo5 28 and a ~galivt voltage rail V"~g. The positive voltage rail Vpo5 iS COnnf~C~ through 29 1e~iSlOr R3 to the emitter of pn~ si~lor Q,5 and directly to the emitter of pnp ~ or Q16. The base and collP~tor of ~ or Ql5 are conl~ r~SpeClively 31 to the collector and base of llansi~lol Q,6. The base of l~ lor Q~6 and the 32 collPctor of tr~nCistor Q~5 are CO-~I~PC P~ to the emitter of pnp tr~n~i~tor Q,3, while SUBSTITUTE SHEET (RULE 26) W O9611SS86 PCTnUSgS/15442 the base of ~ tor Ql5 and the collect( r of ~ lor Q~6 are co.-l.~c~,d to the 2 emitter of pny ~ C:c~or Ql4- The base and collector of ~ (or Ql4 are conn~ d 3 to the base of I~ C tor Ql3. while the collector of I~ lOI Ql3 provides currentI~3.
4 The lf~ portion of the current source, inr~ Qg and Q1O (which 5 correspond to ~ OI~ Qls and Q~6),I"~nC;~O1~ Qll and Q~2 (which coll~,;.yolld to 6 ~ ul~ Ql3 and Ql4) and resistor R2 (which coll~s~o~ds to l,_si~lor R3)~lllrlir~tes 7 the circuit to the extent ~f s~ d so as to provide current I~l. I"", is formed as the 8 dirL~ ce bcl~ the cull~l.b Il3 and Ill. A resistor R4 is provided ~n the 9 collectors of IIA-II~ '~UI ~ Q~2 and Q~4. In this circuit resistor R4 sets the current 10 through ~ u. ~ Qlo~ Q~2. Q~4. and Q~6 (which collc*,o.lds to I", in the circuit of 11 Fig. 7) at ayylo~ rly 13 (17) V~ - V"~ - 4Vb, 15 where Vb" l~,pies~ the base elliltel fOIvval~ voltage of Q~6. Ql4. Q~2 and Q~0, 16 appro~;.. t~ ly equal to 0.7V. This current is chosen, as .. ~I;n~.fA above, so that 17 it is of the same order of ",~ fs as the desired range of Il3 and I" to .~
18 the effects of base ~ ~. The coll~ctor .;U11~ of l~ OI:j Q" and Ql3 are 19 then (via an analysis similar to that above for Fig. 6):
21 (18) Ill= R InA

23 (19) I,3 = RT~&4

25 I~"", is then:

26

27 (20) I~ = Il3 - I = VTInA V~lnA ~R2 _R3 29 and, thus, the a~ 1 pot~ial E"d; will be:
31 (21) E"d; = E - ECp = RII~ = Rl(R2 R3) V~lnA

SUBSTITUTE SHEET (RULE 26) WO g6/lSS86 1 ~ /lS442 If resistors Rl, R2, and R3 are of like types so that they exhibit similar ~ e~ u~
2 coeffirient~ then the adjll~tm~nt ~o~ Lial will be PTAT as desired, and will be 3 ;.-~1e-pe~ of the pot~ at either control port to the extent that Early effect in 4 LIA~ UI~ Qll and Ql3 may be ignored. The put -n;~l may be a~ 1~l by !~
S l~siOL~ra R2 and/ûr R3 using any of the collll~on techniq~es known in the art.
6 Resistor Rl is, again, typically chosen to be less than 100 ohms in order to avoid 7 adding si~nifirAntly to the base l~C;cl;~nre of transistor Q6.
8 Fig. 7 shows a pl~fi_,l~ embo~ of the current source used with a VCA,9 wh~,eill cascode l~d~ 1o Ql7 and Q18 have been added in series with l~ Q ~lUI~
Ql3 and Ql4 (with the e---;l~-~ of pnp l~~.nc l,~J~ Ql7 and Qlgl~opc~ dy CC~
11 to the collectors of l~nC;~ur Ql3 and Ql4~ the bases of !~ lGl~i Ql7 and Ql8 12 conl-~clr~ to each other and to the coll~rtor of l.~ or Ql8~ and the collectQrs of 13 !.,-';clolO Ql7 and Ql8 co~nr~t~ to the output of the current source and ~OioLor R4 14 I.,s~ccli~ely). Similarly, cA~c~de LlalloiolOlo Ql9 and Q20 have been added in series with Ir~ s Qll and Ql2 (with the ~ a of pnp ~ lo~O Qlg and Q20 16 l~Opccli~ely conn~3 to the collectors of ll~ aialOr Qll and Ql2~ the bases of 17 !~ ;Q-lOla Qlg and Q20 CQn~-r~ to each other and to the collector of ~ Q~ ~I Q20-18 and the collectors of ~n~;~lOIa Qlg and Q20 con~ ~d to the output of the current 19 source and lesi~lor . ~ li~ ). The cacc~e I Uli Ql7 and Ql8 serve to ill~lease the output ;",l~A~r~ of the upper current source, as is well known in the 21 art. Tl,.~ Ola Qlg and Q20 serve this r ~ - for the lower current source. This 22 ;--;~ PS the effects of Early effect in the l~ u.~ and makes the circuit behave 23 more ideally with regard to infl~y~ e from eh~ees in the ~ot~ at E~,. The 24 circuit is also ~ecigTlPd so that orlly a single resistor, R3, need be a~j1)st~d This 25 lei,is~ol iS typically ~dju~l ~t .~n a .-- ~i---value that is es~f~;~11y an open 26 circuit to a .. i~.;.. value of R2/2. This yields a range of adj!~s1~ nl potential of:

28 (22) RIVT~&4 ~ E~j ~ -R~VTlnA

29 2 2

30 Diode co.-n~ l~iatOl Q21 is added to ~ the emitter of tl,..-~ or Qls from

31 floqti~ when R3 is open eil~;uil~d. It ensures that current Il7 will be n~gligihly srnall SUBSTITUTE SHEET (RULE 26) WO g6/lSS86 1 ~ sll5442 under these con~1itinnQ (eQQ~ 11y equal to the base current of !.~ lol Ql6) while 2 not il~telr~ lg with normal circuit ope~ o 3 An ~ n~ , to the current sources shown in Fig. 7, and a~ r pl~f. ll~d4 embo~im~-nt is shown in Fig. 8. In Fig. 8, PNP ~ n~ Ql3-QI8 and ,es~tùl R3S function identir~11y to the c- u~m~ l COlly)O~ of Fig. 7 so as to ge~ ale a 6 current:

8 (23) I~3 = -- I~ZA
g R3 Resistor R4 and diode~o.. ~f~ l tr~ Q21 also filnrtion identir~11y with their COU~ in Fig. 7. PNP L~ rt.:., Qg-Q~2~ Ql7 and Ql8 and diode-connP~
12 tr~n~i~tor Q22 along with r~si~lul~ R2 and R5 (all shown to the right in Fig. 8) form 13 an id~ntir~1 circuit as the circuit formed by ~.~nc:-~ Ql3-QI8 and Q21, and l~,SiSlUl:i 14 R3 and R4 (all shown to the left in Fig. 8) so as to ~nf-~ a current:
16 (24) Il1A = -- I~LA

18 T1;.n~:~lo.~ Q23 and Q24 form the ~ P"l form of a current mirror circuit and are 19 formed as two NPN ~ J~ , ~h~,~ the NPN ~ nC;~ l Q23 has its collector 20 Uj~nfC~d to its base and to the collector of ~ -c:~or Ql7. and its emitter c~nP~
21 to the ll~gaLivc voltage rail VNEG. NPN l~n~ J~ Q24 has its emitter conn~-el~d to 22 the ~CE,dlivc voltage rail VNEG~ its base c~ t,~i to the tl~islul Q23 and its 23 co11Prtor con~ ~ with the collP~tor of h~ lul Ql7 (of the circuit portion shown 24 in the left side of Fig. 8) to the s~ cLI~ adjust tP~min~l 22. While NPN L~ lu.~
25 . Q23 and Q24 form a simple current mirror, it will be evident to those skilled in the 26 art that other types of current milIors can be used. ~he current mirror serves to 27 replir~te current Ill. This current serves the same fi1nrtioD as its countc.~all in Fig.

29 In opePtion~ when IIIA (which is ill~ntir~l to Ill by virtue of the current mirror) is less than Il3, I""" will be of a posiLi~ polarity and flow in the direction 31 shown in Fig. 8. If IIIA (and Ill) is greater than I,3, then I~, will be of a ~egalive

32 polarity and flow in the o~osilc direction from that shown in Fig. 8.
SUBSTITUTE SHEET (RULE 26) WO 96/lSS86 PCIlUSgS/lS442 In the cmhot1im~nt of Fig. 8, the PTAT current source is imp'~ ..t~3 with 2 the same polarity devices, and ler~ ced to the same r~f~,le~ce voltage (in this case, 3 Vpo5) as the PTAT current source of Fig. 7. The current mirror is used to g,..~F~
4 the o~posi~ polarit,v current I~l so that the bipolar nature of the co~ ioll current S I"", can be re~li7~
6 With the ~11iti~n of the current mirror, the u~1r~ tio.. of Fig. 8 utili_es 7 a few more collll)o~e~ than the re~li7~ti~-n shown in Fig. 7, but there are occ~cjonc 8 when it may be ~l.,fell~d. In the most c~-.. - .. 1y available j~ 1;o.~-isolated bipolar 9 IC ~locess the vertical NPN ~ ols e~hibit high c~ -base current gain over lO a wide range of Opeldtill~ ;u~ nls~ while the current gain of the lateral PNP
G-:~iS typically much lower, and falls off rapidly at col1PctQr ~;Ull~ above 12 a few tens of i,_loalll~)s. For this reason it may be dei,il~le to implement both 13 PTAT current sources with NPN ~ J~ (the o~po~it~ co~l~ ul~lion from that 14 shown in Fig. 8).
Another occ~ .. where the circuit of Fig. 8 may be ~l.,f,~l~ is when the 16 wafer-stage ~ m~th~ known as "zener ~pillg~ is used to adjust R2 and R3.
17 This ~ C1~ Je involves C1~ , ~f~ lf~t~ ~ CQ-~ CI ;~ . e~n colll~o~c~ at wafer 18 test by passing a short-duration high current through a zener diode. This mPthod 19 lc-luu~,s mPt~11ir cQ~neC1;ol~ (pads) for probe tips to be ~tt~rhP~ to both ends of 20 each zener diode that m ay be sclf~ i~,~ly shorted. Having both PTAT current 21 sour~es; ll ~hf~ to the same ,ef, ,~ voltage ~ in Pig. 8 allows tbe l~,f~ ce 22 voltage node to serve as one end of all co...-~ ~;on~ to be made, which l~uces the 23 1~ Uil~d die area. ~ itit~n~1ly, since the initial state of all sPlPrt~Pd cQnnPrtions is 24 ess~ l1y an open circuit, R2 and R3 may be open circuits before any ~.;.. ;.~ is 25 done. Thus, an ~--11-;------f-~3 version of the device may be ~--r~ ,d with 26 ...;n;...~.. test time by merely o...;ll;.~ the trim pr~hll.,. This is in cO~ dsl to the 27 circuit in Fig. 7, where in order to provide for seleclivc CO~ ;I n of R3, a probe 28 pad must be added at VNEG~ which may not be l~ U ICd ~lth~ iSc.
29 The ch.. ~ n circuits shown in Figs. ~8 provide an easy way to adjust 30 at the wafer stage for the co,l~lion of Opf ~I;o~ es in circuit co",~o~
31 which are a part of the same ;--t~ circuit Sh~lCIulc and which for operational 32 I,~yoses are required to be .".t. 1~ over a ~elalu,c range. More sr~ec-ifi~-~lly, SUBSTITUTE SHEET (RULE 26) WO 96115~ ~ls442 the current source ~ ~"v~ ,, the meal~s~ on ~e same integ~ated circuit 2 i~l~ati~, a gain-co~ol circuit, for providiDg proper ~ for 3 mismatches in the Vb, - I, chara~t~ s of ~he ~ .c~ n~le~ U1f~ Of 4 tempera~re variationS. The d;~~ln5~ c-~h~;--.~m~ ~v-;de a way to implement a gain control circuit of the type having two gain conIrol ~.. ;.. ~1c so that ~hy 6 adjvs~ is ~ rr~ ~t ~1 by the potential at ei~er of ~e two gain control ~ -"~ 1c, 7 thus leaving them both available for use. The ~loacL exploits the use of l~i;~U~.
8 fabricated in ac~ld~ with readily available IC m~nufactunng h r1~n.~ S, that 9 track over a wide range of !-~ .. ",J~ S, in ~ idi~ ap~ liâtely t~ r~c-~ e-10 ~c~-m1 ~t ~~ .h~ adj.,~ for a voltage controlled ~",I.l;r,. ~ implemen~ed as 11 anIC.
12 It is noted ~bat while the c~ sdtion means has been desc~i~d in 13 cn.~ with the type of VCA shown and ~lc~-- il~ incQI~ withFig. l, the 14 Lu~ on can be employed with other types of circuits which are .-.~...r; ,h~.Cd in 15 IC form, and can be used with other types of VCAs, such as those shown in the16 two Frey pateD~s, US Patent Nos. 4,560,947 and 4,823,093. In addition, it should 17 be noted ~hat the c~ of the ~ h~ !-;------;~ ~u~ul~ to the base of 18 ~ J3r Q6 iS but one form of imple~ n with respect to the VCA circuit 19 shown. It may just as easily be cc.~ t ~ to any of the bases of the four log or aD~og ~ (Q3, Q4, Q5, or Q6) with i~ ;t~l no~ts. If the S~ Ch~
21 adj~ 1 al p~ C were co---~r~t~ to the base of !-~ JI Q3, then E~ would be 22 applied to the base of transistor Q6. If it were c~ r~ ~ to the base of ! . ,~ J~Ir Q4, 23 ~en R~ would be co-.-~ A between the bases of ~ Q4 and Q5, with E", 24 applied to the base of transistor Q5, and E,p applied to the bases of I~~ t!~i Q3 and Q6. Similarly, if it were ~)""f'~t~l to the base of ~ or Q5, then R, would again26 be cc ~~ ~ between the bases of 1.~ Q4 and Q5, with E~" applied to the base 27 of transistor Q4, and E~p applied to the bases of 1~ s Q3 and Q6 This is true 28 of all of the ~ a~ljv~ q.~s A,e~.il.~l herein.
29 SiD~e certain ~ a~es may be made in the above ~ s willloul de~alLing from the scope of the ill~e.~li n herein Lu~ol~.,d, it is ;~t --A~d that all matter 31 C-. ~1s ;f~A, in the above ~ or shown in the arc~ ug dl~WiL12~:; shall be 32 int~ ~d in an i~ 1;ve and not in a 1;~ sense.
SUBSTITUTE SHEET (RULE 26)

Claims (24)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An integrated circuit comprising:
at least two components, each of which operate interdependently as a function of temperature and at least one physical parameter associated with each of said components when implemented in integrated form;

compensation means, disposed in said integrated circuit, for generating and applying an adjustable bipolar compensation current to at least one of said components so that the level and polarity of said compensation current can be adjusted during the manufacture of the integrated circuit such that said two components interdependently operate predictably, consistently and substantially independently of temperature variations and differences between the physical parameter of said two components;
wherein said compensation means comprises a positive current source and a negative current source, each source includes at least one output transistor having a collector, and wherein the output transistor of the positive current source is complementary to the output transistor of the negative current source, and (a) current generated through the collector of one of said output transistors is of a positive polarity and is proportional to absolute temperature, (b) current generated through the collector of the other of said output transistors is of a negative polarity and is proportional to absolute temperature, and (c) the positive polarity current is greater than the negative polarity current when the compensation current is of a positive polarity and the positive polarity current is less than the negative polarity current when the compensation current is of a negative polarity.

2. An integrated circuit according to claim 1, wherein said two components are additional transistors, wherein said additional transistors operate interdependently as a function of absolute temperature.

3. An integrated circuit according to claim 2, wherein said physical parameter is the base-to-emitter voltage (V be) to collector current (I c) characteristics of each of said additional transistors.

4. An integrated circuit according to claim 1, wherein said means for generating and applying said adjustable bipolar current includes at least a pair of transistors disposed in said integrated circuit, said adjustable bipolar compensation current is a function of the emitter area ratio of at least a pair of transistors.

5. An integrated circuit according to claim 4, wherein said integrated circuit includes a resistive element coupled to one of said components and having a predetermined resistance with a determinable temperature coefficient, and said means for generating an adjustable bipolar compensation current provides said compensation current as a function of wherein VT is a voltage proportional to absolute temperature, R represents a resistance having a temperature coefficient characteristic matching the temperature coefficient of said resistive element, and A is the emitter area, ratio of said pair of transistors.

6. An integrated circuit according to claim 4, wherein the level and polarity of said bipolar current is a function of the emitter ratios of at least a pair of transistors of said positive current source and at least a pair of transistors of said negative current source.

7. An integrated circuit according to claim 5, wherein said means for generating and applying said adjustable bipolar compensation current includes at least four transistors, wherein three of said transistors have identical operating characteristics, and said fourth transistor is identical to each of said three transistors but includes an emitter area A times larger than the emitter area of each of the other three transistors.

8. An integrated circuit according to claim 1, wherein said means for generating and applying said adjustable bipolar compensation current includes means for generating said adjustable bipolar compensation current as a function wherein R2 and R3 are resistive elements having respective resistances, each adjustable during the manufacture of said integrated circuit, VT is a voltage proportional to absolute temperature and A is the emitter area ratio of at least one pair of transistors.

9. An integrated circuit according to claim 1, further including means for increasing the output impedance of each of said positive current source and the negative current source.

10. An integrated circuit according to claim 9, wherein said means for increasing the output impedance of each of said positive current source and the negative current source includes a pair of cascode transistors.

11. An integrated circuit according to claim 1, wherein one of said current sources includes (a) means for generating a first current signal, and (b) a current mirror for generating a second current signal of an opposing polarity in response to said first current signal.

12. An integrated circuit comprising:
gain control means for generating an output signal as a function of an input signal and a gain control signal, said gain control means including at least two gain control transistors required to be symmetrically matched so that the operational characteristics of said gain control transistors are identical in order to minimize signal distortion by said gain control means and by changes in operating temperature;
and current source means, disposed within said integrated circuit, for generating a bipolar symmetry adjustment current so as to provide symmetry adjustment between said two gain control transistors as a function of any mismatch between said gain control transistors so that the level and polarity of said bipolar current can be adjusted during the manufacture of the integrated circuit such that said two gain control transistors operate predictably, consistently and substantially independently of temperature variations and said gain control signal;
wherein said current source means comprises a positive current source and a negative current source, each source includes at least one output transistor having a collector, and wherein the output transistor of the positive current source is complementary to the output transistor of the negative current source, and (a) current generated through the collector of one of said output transistors is of a positive polarity and is proportional to absolute temperature, (b) current generated through the collector of the other of said output transistors is of a negative polarity and is proportional to absolute temperature, and (c) the positive polarity current is greater than the negative polarity current when the symmetry adjustment current is of a positive polarity and the positive polarity current is less than the negative polarity current when the symmetry adjustment current is of a negative polarity.

13. An integrated circuit according to claim 12, wherein said gain control means includes means for generating a first signal as a logarithmic function of the input signal, and means for generating the output signal as an antilogarithmic function of the gain control signal and the first signal.

14. An integrated circuit according to claim 12, wherein said bipolar symmetry adjustment current is a function of the emitter area ratio of a pair of transistors.

15. An integrated circuit according to claim 14, wherein said integrated circuit includes a resistive element (a) coupled to at least one of said gain control transistors and (b) having a predetermined resistance with a temperature coefficient, and said means for generating said bipolar symmetry adjustment current provides said bipolar current as a function of wherein V T is a voltage proportional to absolute temperature, R represents a resistance having a temperature coefficient characteristic matching the temperature coefficient of said resistive element, and A is the emitter area ratio of at least one pair of transistors.

l6. An integrated circuit according to claim 15, wherein said means far generating said bipolar symmetry adjustment current includes at least four transistors disposed in said integrated circuit, wherein three of said transistors have identical operating characteristics, and said fourth transistor is identical to each. of said three transistors but includes an emitter area A times larger that the emitter area of each of the other three transistors.

17. An integrated circuit according to claim 12, wherein the level and polarity of the bipolar symmetry adjustment current is a function of the emitter area ratios of at feast one pair of transistors.

18. An integrated circuit according to claim 12, wherein said means for generating said bipolar symmetry adjustment current includes means for generating said bipolar symmetry adjustment current as a function of wherein R2 and R3 are resistive elements having respective resistances, each adjustable during the manufacture of said integrated circuit, V T is a voltage proportional to absolute temperature and A is the emitter area ratio of at least one pair of transistors.

19. An integrated circuit according to claim 12, wherein said current source means further includes means for summing said positive and negative polarity currents.

20. An integrated circuit according to claim 19, wherein at least one of said positive current source and said negative current source includes means for adjusting the corresponding positive or negative polarity currents.

21. An integrated circuit according to claim 18, wherein each of said positive and, negative current sources are disposed in said integrated circuit and includes at least four transistors, wherein three of said transistors have identical operating characteristics, and said fourth transistor is identical to each of said three transistors but includes an emitter area A times larger that the emitter area of each of the other three transistors.

22. An integrated circuit according to claim 19, further including means, disposed in said integrated circuit, for increasing the output impedance of each of said positive current source and the negative current source.

23. An integrated circuit according to claim 22, wherein said means for increasing the output impedance of each of said positive current source and the negative current source includes a pair of cascode transistors.

24. An integrated circuit according to claim 19, wherein one of said current sources includes (a) means for generating a first current signal, and (b) a current mirror for generating a second current signal of opposing polarity in response to said current signal.