CA2212089A1 - Bist memory test system - Google Patents

Bist memory test system

Info

Publication number
CA2212089A1
CA2212089A1 CA002212089A CA2212089A CA2212089A1 CA 2212089 A1 CA2212089 A1 CA 2212089A1 CA 002212089 A CA002212089 A CA 002212089A CA 2212089 A CA2212089 A CA 2212089A CA 2212089 A1 CA2212089 A1 CA 2212089A1
Authority
CA
Canada
Prior art keywords
memory
test
data
resulting data
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002212089A
Other languages
French (fr)
Other versions
CA2212089C (en
Inventor
Peter B. Gillingham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Priority to CA002212089A priority Critical patent/CA2212089C/en
Priority to US09/000,968 priority patent/US6182257B1/en
Publication of CA2212089A1 publication Critical patent/CA2212089A1/en
Application granted granted Critical
Publication of CA2212089C publication Critical patent/CA2212089C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches

Abstract

A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.
CA002212089A 1997-07-31 1997-07-31 Bist memory test system Expired - Fee Related CA2212089C (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA002212089A CA2212089C (en) 1997-07-31 1997-07-31 Bist memory test system
US09/000,968 US6182257B1 (en) 1997-07-31 1997-12-30 BIST memory test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA002212089A CA2212089C (en) 1997-07-31 1997-07-31 Bist memory test system

Publications (2)

Publication Number Publication Date
CA2212089A1 true CA2212089A1 (en) 1999-01-31
CA2212089C CA2212089C (en) 2006-10-24

Family

ID=4161170

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002212089A Expired - Fee Related CA2212089C (en) 1997-07-31 1997-07-31 Bist memory test system

Country Status (2)

Country Link
US (1) US6182257B1 (en)
CA (1) CA2212089C (en)

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US6725403B1 (en) * 1999-11-02 2004-04-20 Infineon Technologies Richmond, Lp Efficient redundancy calculation system and method for various types of memory devices
US6928593B1 (en) 2000-09-18 2005-08-09 Intel Corporation Memory module and memory component built-in self test
US6829728B2 (en) * 2000-11-13 2004-12-07 Wu-Tung Cheng Full-speed BIST controller for testing embedded synchronous memories
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US6988231B2 (en) * 2001-03-16 2006-01-17 Emosyn America, Inc. On-chip method and apparatus for testing semiconductor circuits
JP2003031666A (en) * 2001-07-12 2003-01-31 Mitsubishi Electric Corp Apparatus and method for simultaneously testing semiconcudotr device or semiconductor wafer
JP3795822B2 (en) * 2002-04-03 2006-07-12 Ｎｅｃエレクトロニクス株式会社 Embedded self-test circuit and design verification method
US20030212934A1 (en) * 2002-05-07 2003-11-13 David Bovitz Debug port for on-die dram
US7047466B2 (en) * 2002-06-03 2006-05-16 International Business Machines Corporation Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing
US6590818B1 (en) * 2002-06-17 2003-07-08 Motorola, Inc. Method and apparatus for soft defect detection in a memory
DE10229164B4 (en) * 2002-06-28 2004-07-22 Infineon Technologies Ag Memory chip with a data generator and test logic and method for testing memory cells of a memory chip
US6879530B2 (en) * 2002-07-18 2005-04-12 Micron Technology, Inc. Apparatus for dynamically repairing a semiconductor memory
JP2004079072A (en) * 2002-08-16 2004-03-11 Oki Electric Ind Co Ltd Method for testing semiconductor memory device, and semiconductor memory device
US6957372B2 (en) * 2002-08-26 2005-10-18 International Business Machines Corporation Repair of address-specific leakage
US7073100B2 (en) * 2002-11-11 2006-07-04 International Business Machines Corporation Method for testing embedded DRAM arrays
US7356741B2 (en) * 2002-11-26 2008-04-08 Infineon Technologies Ag Modular test controller with BIST circuit for testing embedded DRAM circuits
US7467343B2 (en) * 2003-11-05 2008-12-16 Texas Instruments Incorporated Apparatus and method for performing a multi-value polling operation in a JTAG data stream
US6922649B2 (en) * 2003-11-25 2005-07-26 International Business Machines Corporation Multiple on-chip test runs and repairs for memories
US7248066B2 (en) * 2003-12-29 2007-07-24 Stmicroelectronics Pvt. Ltd. On-chip analysis and computation of transition behavior of embedded nets in integrated circuits
US7568134B1 (en) * 2004-02-02 2009-07-28 Advanced Micro Devices, Inc. Method of exhaustively testing an embedded ROM using generated ATPG test patterns
US8621304B2 (en) * 2004-10-07 2013-12-31 Hewlett-Packard Development Company, L.P. Built-in self-test system and method for an integrated circuit
US20060090105A1 (en) * 2004-10-27 2006-04-27 Woods Paul R Built-in self test for read-only memory including a diagnostic mode
US7346815B2 (en) * 2005-03-31 2008-03-18 Intel Corporation Mechanism for implementing redundancy to mask failing SRAM
US7562271B2 (en) * 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
JP4686350B2 (en) * 2005-12-09 2011-05-25 株式会社東芝 Nonvolatile semiconductor memory device and self test method thereof
US7447956B2 (en) * 2006-03-03 2008-11-04 Qualcomm Incorporated Method and apparatus for testing data steering logic for data storage having independently addressable subunits
ATE492885T1 (en) * 2006-05-18 2011-01-15 Dialog Semiconductor Gmbh MEMORY TEST APPARATUS
US7665003B2 (en) * 2006-12-15 2010-02-16 Qualcomm Incorporated Method and device for testing memory
US8090965B1 (en) * 2008-04-17 2012-01-03 Lsi Corporation System and method for testing memory power management modes in an integrated circuit
US7925949B2 (en) 2008-10-15 2011-04-12 Micron Technology, Inc. Embedded processor
JP5595514B2 (en) 2009-11-20 2014-09-24 ラムバス・インコーポレーテッド Bit exchange technology for DRAM error correction
US9037928B2 (en) * 2012-01-01 2015-05-19 Mosys, Inc. Memory device with background built-in self-testing and background built-in self-repair
TWI451428B (en) 2010-06-03 2014-09-01 Sunplus Technology Co Ltd Programmable loading test system with advance features for completed memory system
KR101806807B1 (en) * 2010-11-08 2017-12-11 삼성전자주식회사 Memory card
US9411678B1 (en) 2012-08-01 2016-08-09 Rambus Inc. DRAM retention monitoring method for dynamic error correction
US9734921B2 (en) 2012-11-06 2017-08-15 Rambus Inc. Memory repair using external tags
US9257199B2 (en) * 2013-07-24 2016-02-09 Advanced Micro Devices, Inc. Canary circuit with passgate transistor variation
US10607715B2 (en) 2017-06-13 2020-03-31 International Business Machines Corporation Self-evaluating array of memory
US10748635B2 (en) 2018-03-22 2020-08-18 Marvell Asia Pte, Ltd. Dynamic power analysis with per-memory instance activity customization
CN109065094B (en) * 2018-08-09 2021-04-27 晶晨半导体（深圳）有限公司 Method and system for obtaining mass production frequency of double-rate synchronous dynamic random access memory
JP6746659B2 (en) * 2018-11-09 2020-08-26 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． Memory device and built-in self-test method
TWI676989B (en) * 2018-11-20 2019-11-11 華邦電子股份有限公司 Memory device and built-in self-test method thereof
US10971242B2 (en) 2019-09-11 2021-04-06 International Business Machines Corporation Sequential error capture during memory test
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US5987632A (en) * 1997-05-07 1999-11-16 Lsi Logic Corporation Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Also Published As

Publication number Publication date
US6182257B1 (en) 2001-01-30
CA2212089C (en) 2006-10-24

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Effective date: 20160801