CA2231362C - A data maximizing serial to parallel bus interface in a data processing system and method therefor - Google Patents
A data maximizing serial to parallel bus interface in a data processing system and method therefor Download PDFInfo
- Publication number
- CA2231362C CA2231362C CA002231362A CA2231362A CA2231362C CA 2231362 C CA2231362 C CA 2231362C CA 002231362 A CA002231362 A CA 002231362A CA 2231362 A CA2231362 A CA 2231362A CA 2231362 C CA2231362 C CA 2231362C
- Authority
- CA
- Canada
- Prior art keywords
- serial
- data
- parallel
- bus
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
Abstract
A serial/parallel interface for interfacing the serial port of a microcontroller with parallel bus devices, and a protocol for communicating with the same. The interface operates to maximize through-put with minimum handshaking. When the bus device is a nonvolatile memory containing the operating software of the microcontroller system, the interface provides for dynamic updating of the operating program. It also relieves the constraints imposed on the number of bus devices accessible to the microcontroller system because of the limited number of I/O pins available on the microcontroller.
Description
A DATA MAXIMIZING SERIAL TO PARALLEL BUS INTERFACE IN A DATA
PROCESSING SYSTEM AND METHOD THEREFOR
The present invention relates in general to embedded controller systems, and in particular, to a serial bus to parallel bus interface in an embedded controller system.
BACKGROUND INFORMATION
In systems employing an embedded microcontroller, the limitations of the microcontroller with respect to the available I10 pins and on-device memory can impose unacceptable design constraints on the system. The number of IIO pins that are available constrain the size of the address space accessible by the microcontroller.
This then limits the size and number of bus devices that reside in the address space. This need not only limit the size of memory available for software and data, but also may limit peripheral devices that are accessible by the microcontroller. Furthermore, on-device nonvolatile memory is typically very limited in its size, making storage of the operating software in an external memory space essential. Moreover, the microcontroller often is a one time programmable ("OTP") device, so that once the software is "burned into" the on-chip nonvolatile memory, it cannot be modified. The system software then cannot be updated without replacing the microcontroller chip itself.
Therefore, it may be desirable to store the system software in a nonvolatile programmable memory that resides in the external memory space. Updating of the system software could then be performed by downloading the new software into the nonvolatile memory. However, having the system program reside in the external memory space rather than on-chip only exacerbates the problem of a limited number of IIO pins.
Therefore, there is a need in the art for a method and circuitry to interface a microcontroller with nonvolatile memory containing its operating software such that the software can be easily updated by downloading the new software into the nonvolatile memory without exceeding the pin count of the microcontroller.
SUMMARY OF THE INVENTION
The previously mentioned needs are fulfilled with the present invention. The present invention satisfies the foregoing need by making use of the serial port available on a microcontroller in association with a serial-to-parallel bidirectional bus interface (hereinafter referred to as the seriallparallel interface). The seriallparallel interface accepts serial cycles from the microcontroller, and then converts them into cycles that are recognizable by the nonvolatile memory, which is a parallel bus device. Data representing the code to be downloaded is clocked out of the serial port of the microcontroller into the seriallparallel interface. The serial/parallel interface then presents this data on its parallel data bus, enabling the data to be read into the nonvolatile memory residing on the address space of the seriallparallel interface. Use of the serial port on the microcontroller in association with the seriallparallel interface is advantageous in that it makes the limited number of inputloutput ("IIO") pins available on the microcontroller available for parallel bus devices, including random access memory ("RAM") devices that require real time access by the microcontroller. Another advantage of the present invention is that it enables the system software to be updated dynamically. In operation, the microcontroller runs under the control of its system software which is located in a RAM residing in the address space of one of the microcontroller's I/O ports. The operating code is uploaded into RAM at startup from the nonvolatile memory through the seriallparallel interface and the microcontroller serial port. Updated software can then be downloaded to the nonvolatile memory through the microcontroller serial port and seriallparallel interface while the microcontroller runs under the control of the software code resident in RAM.
In this way another objective of the invention is achieved.
In order to maximize data through-put between the microcontroller serial port and the nonvolatile memory, it is desirable to minimize handshaking between the microcontroller and the seriallparallel interface. This is achieved in the present invention by incorporating logic within the seriallparallel interface itself to control the flow of data.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGURE 1 illustrates a block diagram of an embodiment of a microcontroller system using the present invention;
FIGURE 2 illustrates a block diagram of an embodiment of the seriallparallel interface of the present invention;
FIGURE 3 illustrates a block diagram detailing another embodiment of the seriallparallel interface of the present invention;
FIGURE 4 illustrates a flow diagram of the row, column/count state machine of FIGURE 3; and FIGURE 5 illustrates a flow diagram of the readlwrite state machine of FIGURE
3.
DETAILED DESCRIPTION
In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details.
In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art. During the following description of the implementation of the present invention, the terms "assert"
and "negate"
and various grammatical forms thereof, are used to avoid confusion when dealing with a mixture of "active high" and "active low" logic signals. "Assert" is used to refer to the rendering of a logic signal or register bit into its active, or logically true, state. "Negate" is used to refer to the rendering of a logic signal or register bit into its inactive, or logically false state.
Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
An invention that alleviates the pinout problem in a microcontroller system, and incorporates dynamic updating of the operating software will now be described in detail.
Referring to FIGURE 1, there is shown a microcontroller system 100 in accordance with one embodiment of the present invention. Microcontroller 101 communicates with the seriallparallel interface 102 by means of three signal lines, Reset 111, Serial clock 112, and Rx/TxD 113. An operation which might either download data to a parallel bus device 103 or upload data from the parallel bus device 103 is initiated by a signal on reset line 111. Serial data is either clocked out of microcontroller 101 serial port or into microcontroller 101 serial port depending on the operation. Serial data is communicated between the bidirectional serial port of microcontroller 101 and the seriallparallel interface 102 on the bidirectional serial data line, RxITxD line 113. The serial clock of microcontroller 101 is sent to serial/parallel interface 102 via serial clock line 112. In a download, or write, operation, serial data is received by the serial/parallel interface 102, and provided to parallel bidirectional data bus 122. Data bus 122 is an m-bit parallel data line, where m is a predetermined integer number of bits. Conversely, in an upload, or read, operation, bus device 103 sets up the data to be sent to microcontroller 101 on the bidirectional data bus 122 where it is received by the seriallparallel interface 102. Data is then clocked out by the seriallparallel interface 102 on line RxITxD 113 where it is received at the serial port of microcontroller 101. The address at which data is either to be written or read is provided to seriallparallel interface 102 on its address line 121.
Address line 121 is an n-bit address bus, where n is a predetermined integer number of bits.
Seriallparallel interface 102 informs bus device 103 when a read or write operation is being executed using readlwrite ("RIW") control bus 123. Seriallparallel interface 102 may access more than one bus device. In such an embodiment, RIW control bus 123 would implement a chip select signal on one of its lines. Chip select operation and circuitry are understood by artisans of ordinary skill in the art. Bus device 103 may be implemented as a memory, including nonvolatile memory, or a peripheral bus device in one embodiment of the invention. Additionally, it should be noted that bus device 103 may be any device in a data processing system that communicates via a parallel bus.
Microcontroller system 100 may also include other bus devices such as bus device 104 which reside in the address space of microcontroller 101. Data is transmitted to, or received from, bus device 104 on parallel data bus 142, and the address at which the read or write operation takes place is provided by an address bus 141 of microcontroller 101.
Microcontroller 101 informs bus device 104 as to a read or write operation by asserting read/write bus 143. A more detailed understanding of the invention may be had by now referring to FIGURE 2 depicting a block diagram of an embodiment of seriallparallel interface 102.
An operation is initialized by microcontroller 101 (not shown in FIGURE 2) asserting reset line 111. In response to the signal on reset line 111, control logic 207 resets address logic 203 and clock sequencing logic 201 by asserting the interface reset line 272.
Microcontroller 101 then clocks out the initial n-bit address to be asserted on address line 121. The initial n-bit address corresponds to the location of the first block of data to be uploaded or downloaded. This address is clocked into shift register 202 by register clock 211 generated by clock sequencing logic 201. Clock sequencing logic 201 receives the serial clock from microcontroller 101 on serial clock 112. Register clock 211 is synchronized with serial clock 112. Microcontroller 101 may send the initial address byte-by-byte. In such an embodiment, microcontroller 101 sends bytes of the address sequentially until all n-bits of the address have been sent. Clock sequencing logic 201 accumulates serial clock cycles. After all n-bits are received, clock sequencing logic 201 latches the address which appears on the parallel bus 221 of shift register 202 into address logic 203 by asserting address latch 212. Parallel bus 221 is Z bits in length, where Z is predetermined integer value.
Afterthe initial address has been transmitted, microcontroller 101 sends a command byte. Control logic 207 receives the serial clock from microcontroller 101 on serial clock line 112. It accumulates clock cycles until the eight bits of the command byte have been clocked in. It then latches the command byte which it receives on the parallel bus 221 of shift register 202. The state of the first bit of the command byte determines whether the operation to be performed is a read or a write. The control logic 207 then uses this to establish the state of R/W enable 271. Input data buffer 205 and output data buffer 206 are enabled or disabled according to the state of R/W enable line 271.
Read operation commences when microcontroller 101 issues a read command to its serial port. The serial clock signal 112 is passed to the output data buffer 206 by clock sequencing logic 201 via data clock line 213. Output data buffer 206 has been enabled by the signal on the R/W enable line 271. A read state is also asserted on R/W
control bus 123 informing the bus device 103 that a read is being performed. The m-bits of data are serially read out, then control logic 207 asserts the address count increment signal 273, causing address logic 203 to address the next m-bit data block. After m-bits of data have been provided to microcontroller 101, clock sequencing logic 201 stops issuing clock signals to output data buffer 206. M-bit blocks of data are sequentially received by microcontroller 101 by repeating this operation. The read operation is terminated when microcontroller 101 asserts reset 111, to indicate that serial/parallel interface 102 should be reset in anticipation of the next operation.
Write operation commences when microcontroller 101 writes data to its serial port in response to an instruction in the software code. This is not shown herein, but it is well understood by one of ordinary skill in the art. Input data buffer 205 receives the m-bit data block on the parallel bus 221 of shift register 202. The data are latched into input data buffer 205 in response to data clock 213. Control logic 207 may control the latching of data into input data buffer 205 via input data buffer control line 274. In an alternative embodiment, alternative means may be used to latch data into input data buffer 205. Such means are well know in the art. Control logic 207 also receives data clock 213. In response thereto, control logic 207 asserts a write state on RIW control bus 123, causing bus device 103 to access the data on the data bus 122. Control logic 207 also asserts address count increment 273, causing address logic 203 to increment an address counter.
The address of the location into which the next n-bit block of data is to be downloaded is then provided on address bus 121 by address logic 203. The write operation continues to execute these steps until all of the data to be downloaded has been transmitted.
Microcontroller 101 then signals the end of the write operation by asserting reset line 111, to inform the seriallparallel interface 102 to reset in anticipation of a next operation.
Data may be downloaded byte-by-byte in an interleaved fashion. In such an embodiment, if a write operation has been contemplated, the last four bits of the command byte contain the lower four bits ("low nibble") of the first output byte. If a read operation is contemplated, the value of bits one through seven of the command byte are ignored.
Control logic 207 decodes the first bit of the command byte, and on detecting the write operation, instructs input data buffer 205 to latch these four bits. Control logic 207 decodes the first bit of the command byte, and on detecting the write operation, instructs input data buffer 205 to latch these four bits. Then, the low nibble of the first output byte sent by microcontroller 101 contains the upper four bits ("high nibble") of the first data byte, and the high nibble of the first output byte contains the low nibble of the next data byte to be downloaded. Control logic 207 steers the latching of the output byte into internal registers (not shown) in input data buffer 205, via input buffer control bus 274. This steering effects the assembly of the two nibbles, transmitted in interleaved fashion, into a full data byte. It would be well understood by an artisan of ordinary skill that communication of data bytes using this method is independent of whether the mode of data representation is least significant bit ("LSB") first, or most significant bit ("MSB") first.
Control logic 207 continues to accumulate input data byte-by-byte until all m-bits of data have been assembled. It then loads the data into input data buffer 205 and operation continues as described above. Further understanding of the operation of the invention may be had by now referring to FIGURE 3 in which a block diagram of another embodiment of the invention is shown.
In FIGURE 3, operation begins with microcontroller 101 (not shown in FIGURE 3) asserting reset 111 to causes readlwrite state machine 307, row, column-count state machine 308, and command logic 309 to reset. Microcontroller 101 then commences to download an initial address on address bus 121 at which a download or upload operation is to begin. Microcontroller 101 transmits the n-bit address by clocking the address out of its serial port on RxITxD line 113. The address is clocked into shift register 202 on serial/parallel interface 102; the address transfer may be byte-by-byte.
Microcontroller 101 also outputs its serial clock on serial clock line 112. Clock generator 301 receives serial clock 112 and outputs interface serial clock pulses on interface clock line 311. The interface clock is synchronized to serial clock 112. Clock generator 301 may output an interface clock pulse on each of the rising and falling edges of serial clock 112. Clocking of shift register 202 is controlled by the signal on interface clock line 311.
The initial address is stored by a plurality X of mutiplexers-with-latch referred to as 304-0 through 304-X, where X is an integer value equal to a predetermined number of multiplexers-with-latch. The initial address may be stored byte-by-byte.
Mutiplexer-with-latch 304-1 through mutiplexer-with-latch 304-X are coupled to the parallel bus 321 of shift register 302. A mutiplexer-with-latch that will store the current block of the m-bit address being transmitted is selected by decoding the row and column count signal provided on output bus 381 of row, column-count state machine 308. A block of the n-bit address may be a byte in length. After the current block has been clocked out of microcontroller 101 and into shift register 202, the address is latched into the selected one of mutiplexer-with-latch 304-0 through mutiplexer-with-latch 304-X by an interface clock pulse on line 311. After all n-bits of the address have been sent, the address is loaded into address counter 303.
AT9-97-210 ~ o Row and column select signals are generated by row, column-count state machine 308. Row, column-count state machine 308 receives interface clock pulses from clock generator 301 on interface clock line 311. A flow chart of an embodiment of a row, column-count state machine 308 is illustrated in FIGURE 4.
After reset, row, column-count state machine 308 accumulates interface serial clock pulses received on interface serial clock line 311. The logic to accumulate clock pulses is internal to row, column-count state machine 308 and is not shown in detail.
If the number of clock pulses accumulated has not reached Y, the row, column-count state machine 308 increments the column count, outputs the row and column-count and continues to interface serial clock cycles recf:ived on interface serial clock line 311. Y is a preselected integer corresponding to the length of a data block to be downloaded in a single download cycle. Furthermore, in an embodiment in which all m bits of data are downloaded on one cycle, Y would equal m. An embodiment downloading byte-byte would have a value of Y equal to eight. Moreover, in the present invention, after microcontroller 101 first sends an n-bit address, row, column-count state machine 308 may adaptively set Y. For example, in an embodiment where the entire address is sent as a block, Y is initially set equal to n. After the n-bits have been received, row, column-count state machine 308 may set Y to a new preselected value. This new preselected value would be m in an embodiment in which m data bits are to be downloaded in a block. In an embodiment in which both the n-bit address and the m-bit data are sent byte-by-byte, Y would have a fixed value of eight.
If the clock accumulator has reached Y, the row, column-count state machine increments the row count, resets the column count, and outputs the row and column count on its output bus 381. If a reset has not been received from microcontroller 101 on reset line 111, the row, column-count state machine 308 continues to accumulate clock cycles and continues to increment the row and column-counts as previously described.
If a reset has been received on reset line 111, then the row, column-count state machine 308 resets.
When the next operation commences, row, column-count state machine 308 begins accumulating clock cycles as they are received. The timing of the sequential operation of row, column-count state machine 308 is controlled by its internal clock (not shown). The internal clock need not be synchronized with the interface serial clock pulses on line 311, and the rate of the internal clock may be much greater than the rate of the interface serial clock pulses on line 311.
After sending the n-bit initial address, microcontroller 101 sends a command byte.
Command logic 309 decodes a row and column address received from row, column-count state machine 308 on output line 381. After the eight bits of the command byte have been clocked into shift register 302, command logic 309 latches the command byte which it receives on the parallel bus 321 of shift register 302. The state of the first bit of the command byte informs the seriallparallel interface 102 whether the operation to be performed is a read or a write. Command logic 309 ascertains the state of the first bit of the command byte and sets the state of read/write state machine 307 through output line 391 of command logic 309. In one embodiment of the present invention in which data transfer is byte-by-byte, if a write operation is to be performed, the last four bits of the command byte includes the lowest nibble of the first data byte to be downloaded, as describe above.
Read and write operations are controlled by readlwrite state machine 307. A
flow chart of an embodiment of a readlwrite state machine 307 is illustrated in FIGURE 5.
Readlwrite state machine 307 receives the output row and column addresses on the row and column address bus 381 by the row, column-count state machine 308. If the command logic has been addressed, then readlwrite state machine 307 tests the state of the output line 391 of command logic 309. If line 391 is in a read state, readlwrite state machine 307 asserts a read on RIV1I control bus 123. It then commands read data buffer 206 to latch the data on data bus 122 via line 371. The first block of data to be sent resides at the initial address loaded into address counter 303. If, after m-bits have been sent, a reset has not been asserted, RIW state machine 307 increments address counter 303 so that the address of the next block of data to be read appears on address bus 121.
Address counter 303 increments the address on address bus 121 in response to the address increment signal received from readlwrite state machine 307 via address counter increment line 372. After latching the data, read data buffer 206 clocks the data out via serial data line RxITxD 113. Clocking of the data is controlled by the serial clock pulses asserted by clock generator 301 on interface serial clock line 311. After the address counter 303 has been incremented, the cycle repeats until a reset is asserted on reset line 111 by microcontroller 101 (not shown).
If a write is to be performed, readlwrite state machine 307 accumulates the number of bits received. When m-bits have been received, read/write state machine 307 asserts a write on RIVII control bus 123. Read/write state machine 307 then tests to see if a reset has been asserted. If a reset has been asserted, readlwrite state machine 307 resets, otherwise, it increments address counter 303 via address counter increment line 372. This cycle repeats until a reset has been asserted on reset line 111 by microcontroller 101. The timing of the sequential operations of RIW state machine 307 is controlled by its internal clock (not shown). The internal clock may not be synchronized with the interface serial clock on line 311, and the rate of the internal clock may be much greater than the rate of the interface serial clock pulses on line 311..
In a write operation, data to be written to data byte 122 is received by data logic 305. Data may be transmitted from microcontroller 101 byte-by-byte. In such an embodiment the command byte includes the lowest nibble of the first data byte to be downloaded, as discussed above. Data lagic 305 receives the command byte on the parallel bus 321 of shift register 202. The next byte sent by microcontroller 101 through its serial port, RxITxD 113, contains the high nibble of the first data byte in its lower four bits, and the low nibble of the next data byte in its four upper bits. Data logic 305 receives the next byte transmitted by the parallel bus 321 of shift register 302 and latches this output byte. Data logic 305 then concatenates the low nibble and the high nibble of the first data byte and transfers it to data bus 122. Microcontroller 101 continues to transmit data on serial line RxITxD 113 in this interleaved fashion. Data logic 305 latches the output bytes as they are received and concatenates the low nibble and high nibble of each byte of data as described above. Latching of the data at data logic 305 is controlled by the interface serial clock pulses generated on line 311. It would be well understood by an artisan of ordinary skill that communication of data bytes using this method is independent of whether the mode of data representation is LSB first, or MSB first. After m-bits of data have been transmitted, the data is written to bus device 103 by readlwrite state machine 307 asserting a write state on R/W control bus 123. If, after m-bits have been sent, a reset has not been asserted, RIW state machine 307 increments address counter 303 so that the address of the next block of data to be read appears on address bus 121. Address counter 303 increments the address on address bus 121 in response to the address increment signal received from readlwrite state machine 307 via address counter increment line 372. Subsequent m-bit blocks of data are transmitted in this way until all the data to be downloaded has been sent, and microcontroller 101 asserts a reset on reset line 111. Seriallparallel interface 102 is then ready to begin the next operation.
The data processing system and methodology represented in the embodiments described herein are effective solutions to the associated problems of interfacing bus devices with an embedded controller having a limited number of parallel I/O
buses, and dynamic updating of the operating software of the data processing system.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
PROCESSING SYSTEM AND METHOD THEREFOR
The present invention relates in general to embedded controller systems, and in particular, to a serial bus to parallel bus interface in an embedded controller system.
BACKGROUND INFORMATION
In systems employing an embedded microcontroller, the limitations of the microcontroller with respect to the available I10 pins and on-device memory can impose unacceptable design constraints on the system. The number of IIO pins that are available constrain the size of the address space accessible by the microcontroller.
This then limits the size and number of bus devices that reside in the address space. This need not only limit the size of memory available for software and data, but also may limit peripheral devices that are accessible by the microcontroller. Furthermore, on-device nonvolatile memory is typically very limited in its size, making storage of the operating software in an external memory space essential. Moreover, the microcontroller often is a one time programmable ("OTP") device, so that once the software is "burned into" the on-chip nonvolatile memory, it cannot be modified. The system software then cannot be updated without replacing the microcontroller chip itself.
Therefore, it may be desirable to store the system software in a nonvolatile programmable memory that resides in the external memory space. Updating of the system software could then be performed by downloading the new software into the nonvolatile memory. However, having the system program reside in the external memory space rather than on-chip only exacerbates the problem of a limited number of IIO pins.
Therefore, there is a need in the art for a method and circuitry to interface a microcontroller with nonvolatile memory containing its operating software such that the software can be easily updated by downloading the new software into the nonvolatile memory without exceeding the pin count of the microcontroller.
SUMMARY OF THE INVENTION
The previously mentioned needs are fulfilled with the present invention. The present invention satisfies the foregoing need by making use of the serial port available on a microcontroller in association with a serial-to-parallel bidirectional bus interface (hereinafter referred to as the seriallparallel interface). The seriallparallel interface accepts serial cycles from the microcontroller, and then converts them into cycles that are recognizable by the nonvolatile memory, which is a parallel bus device. Data representing the code to be downloaded is clocked out of the serial port of the microcontroller into the seriallparallel interface. The serial/parallel interface then presents this data on its parallel data bus, enabling the data to be read into the nonvolatile memory residing on the address space of the seriallparallel interface. Use of the serial port on the microcontroller in association with the seriallparallel interface is advantageous in that it makes the limited number of inputloutput ("IIO") pins available on the microcontroller available for parallel bus devices, including random access memory ("RAM") devices that require real time access by the microcontroller. Another advantage of the present invention is that it enables the system software to be updated dynamically. In operation, the microcontroller runs under the control of its system software which is located in a RAM residing in the address space of one of the microcontroller's I/O ports. The operating code is uploaded into RAM at startup from the nonvolatile memory through the seriallparallel interface and the microcontroller serial port. Updated software can then be downloaded to the nonvolatile memory through the microcontroller serial port and seriallparallel interface while the microcontroller runs under the control of the software code resident in RAM.
In this way another objective of the invention is achieved.
In order to maximize data through-put between the microcontroller serial port and the nonvolatile memory, it is desirable to minimize handshaking between the microcontroller and the seriallparallel interface. This is achieved in the present invention by incorporating logic within the seriallparallel interface itself to control the flow of data.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIGURE 1 illustrates a block diagram of an embodiment of a microcontroller system using the present invention;
FIGURE 2 illustrates a block diagram of an embodiment of the seriallparallel interface of the present invention;
FIGURE 3 illustrates a block diagram detailing another embodiment of the seriallparallel interface of the present invention;
FIGURE 4 illustrates a flow diagram of the row, column/count state machine of FIGURE 3; and FIGURE 5 illustrates a flow diagram of the readlwrite state machine of FIGURE
3.
DETAILED DESCRIPTION
In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details.
In other instances, well-known circuits have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art. During the following description of the implementation of the present invention, the terms "assert"
and "negate"
and various grammatical forms thereof, are used to avoid confusion when dealing with a mixture of "active high" and "active low" logic signals. "Assert" is used to refer to the rendering of a logic signal or register bit into its active, or logically true, state. "Negate" is used to refer to the rendering of a logic signal or register bit into its inactive, or logically false state.
Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
An invention that alleviates the pinout problem in a microcontroller system, and incorporates dynamic updating of the operating software will now be described in detail.
Referring to FIGURE 1, there is shown a microcontroller system 100 in accordance with one embodiment of the present invention. Microcontroller 101 communicates with the seriallparallel interface 102 by means of three signal lines, Reset 111, Serial clock 112, and Rx/TxD 113. An operation which might either download data to a parallel bus device 103 or upload data from the parallel bus device 103 is initiated by a signal on reset line 111. Serial data is either clocked out of microcontroller 101 serial port or into microcontroller 101 serial port depending on the operation. Serial data is communicated between the bidirectional serial port of microcontroller 101 and the seriallparallel interface 102 on the bidirectional serial data line, RxITxD line 113. The serial clock of microcontroller 101 is sent to serial/parallel interface 102 via serial clock line 112. In a download, or write, operation, serial data is received by the serial/parallel interface 102, and provided to parallel bidirectional data bus 122. Data bus 122 is an m-bit parallel data line, where m is a predetermined integer number of bits. Conversely, in an upload, or read, operation, bus device 103 sets up the data to be sent to microcontroller 101 on the bidirectional data bus 122 where it is received by the seriallparallel interface 102. Data is then clocked out by the seriallparallel interface 102 on line RxITxD 113 where it is received at the serial port of microcontroller 101. The address at which data is either to be written or read is provided to seriallparallel interface 102 on its address line 121.
Address line 121 is an n-bit address bus, where n is a predetermined integer number of bits.
Seriallparallel interface 102 informs bus device 103 when a read or write operation is being executed using readlwrite ("RIW") control bus 123. Seriallparallel interface 102 may access more than one bus device. In such an embodiment, RIW control bus 123 would implement a chip select signal on one of its lines. Chip select operation and circuitry are understood by artisans of ordinary skill in the art. Bus device 103 may be implemented as a memory, including nonvolatile memory, or a peripheral bus device in one embodiment of the invention. Additionally, it should be noted that bus device 103 may be any device in a data processing system that communicates via a parallel bus.
Microcontroller system 100 may also include other bus devices such as bus device 104 which reside in the address space of microcontroller 101. Data is transmitted to, or received from, bus device 104 on parallel data bus 142, and the address at which the read or write operation takes place is provided by an address bus 141 of microcontroller 101.
Microcontroller 101 informs bus device 104 as to a read or write operation by asserting read/write bus 143. A more detailed understanding of the invention may be had by now referring to FIGURE 2 depicting a block diagram of an embodiment of seriallparallel interface 102.
An operation is initialized by microcontroller 101 (not shown in FIGURE 2) asserting reset line 111. In response to the signal on reset line 111, control logic 207 resets address logic 203 and clock sequencing logic 201 by asserting the interface reset line 272.
Microcontroller 101 then clocks out the initial n-bit address to be asserted on address line 121. The initial n-bit address corresponds to the location of the first block of data to be uploaded or downloaded. This address is clocked into shift register 202 by register clock 211 generated by clock sequencing logic 201. Clock sequencing logic 201 receives the serial clock from microcontroller 101 on serial clock 112. Register clock 211 is synchronized with serial clock 112. Microcontroller 101 may send the initial address byte-by-byte. In such an embodiment, microcontroller 101 sends bytes of the address sequentially until all n-bits of the address have been sent. Clock sequencing logic 201 accumulates serial clock cycles. After all n-bits are received, clock sequencing logic 201 latches the address which appears on the parallel bus 221 of shift register 202 into address logic 203 by asserting address latch 212. Parallel bus 221 is Z bits in length, where Z is predetermined integer value.
Afterthe initial address has been transmitted, microcontroller 101 sends a command byte. Control logic 207 receives the serial clock from microcontroller 101 on serial clock line 112. It accumulates clock cycles until the eight bits of the command byte have been clocked in. It then latches the command byte which it receives on the parallel bus 221 of shift register 202. The state of the first bit of the command byte determines whether the operation to be performed is a read or a write. The control logic 207 then uses this to establish the state of R/W enable 271. Input data buffer 205 and output data buffer 206 are enabled or disabled according to the state of R/W enable line 271.
Read operation commences when microcontroller 101 issues a read command to its serial port. The serial clock signal 112 is passed to the output data buffer 206 by clock sequencing logic 201 via data clock line 213. Output data buffer 206 has been enabled by the signal on the R/W enable line 271. A read state is also asserted on R/W
control bus 123 informing the bus device 103 that a read is being performed. The m-bits of data are serially read out, then control logic 207 asserts the address count increment signal 273, causing address logic 203 to address the next m-bit data block. After m-bits of data have been provided to microcontroller 101, clock sequencing logic 201 stops issuing clock signals to output data buffer 206. M-bit blocks of data are sequentially received by microcontroller 101 by repeating this operation. The read operation is terminated when microcontroller 101 asserts reset 111, to indicate that serial/parallel interface 102 should be reset in anticipation of the next operation.
Write operation commences when microcontroller 101 writes data to its serial port in response to an instruction in the software code. This is not shown herein, but it is well understood by one of ordinary skill in the art. Input data buffer 205 receives the m-bit data block on the parallel bus 221 of shift register 202. The data are latched into input data buffer 205 in response to data clock 213. Control logic 207 may control the latching of data into input data buffer 205 via input data buffer control line 274. In an alternative embodiment, alternative means may be used to latch data into input data buffer 205. Such means are well know in the art. Control logic 207 also receives data clock 213. In response thereto, control logic 207 asserts a write state on RIW control bus 123, causing bus device 103 to access the data on the data bus 122. Control logic 207 also asserts address count increment 273, causing address logic 203 to increment an address counter.
The address of the location into which the next n-bit block of data is to be downloaded is then provided on address bus 121 by address logic 203. The write operation continues to execute these steps until all of the data to be downloaded has been transmitted.
Microcontroller 101 then signals the end of the write operation by asserting reset line 111, to inform the seriallparallel interface 102 to reset in anticipation of a next operation.
Data may be downloaded byte-by-byte in an interleaved fashion. In such an embodiment, if a write operation has been contemplated, the last four bits of the command byte contain the lower four bits ("low nibble") of the first output byte. If a read operation is contemplated, the value of bits one through seven of the command byte are ignored.
Control logic 207 decodes the first bit of the command byte, and on detecting the write operation, instructs input data buffer 205 to latch these four bits. Control logic 207 decodes the first bit of the command byte, and on detecting the write operation, instructs input data buffer 205 to latch these four bits. Then, the low nibble of the first output byte sent by microcontroller 101 contains the upper four bits ("high nibble") of the first data byte, and the high nibble of the first output byte contains the low nibble of the next data byte to be downloaded. Control logic 207 steers the latching of the output byte into internal registers (not shown) in input data buffer 205, via input buffer control bus 274. This steering effects the assembly of the two nibbles, transmitted in interleaved fashion, into a full data byte. It would be well understood by an artisan of ordinary skill that communication of data bytes using this method is independent of whether the mode of data representation is least significant bit ("LSB") first, or most significant bit ("MSB") first.
Control logic 207 continues to accumulate input data byte-by-byte until all m-bits of data have been assembled. It then loads the data into input data buffer 205 and operation continues as described above. Further understanding of the operation of the invention may be had by now referring to FIGURE 3 in which a block diagram of another embodiment of the invention is shown.
In FIGURE 3, operation begins with microcontroller 101 (not shown in FIGURE 3) asserting reset 111 to causes readlwrite state machine 307, row, column-count state machine 308, and command logic 309 to reset. Microcontroller 101 then commences to download an initial address on address bus 121 at which a download or upload operation is to begin. Microcontroller 101 transmits the n-bit address by clocking the address out of its serial port on RxITxD line 113. The address is clocked into shift register 202 on serial/parallel interface 102; the address transfer may be byte-by-byte.
Microcontroller 101 also outputs its serial clock on serial clock line 112. Clock generator 301 receives serial clock 112 and outputs interface serial clock pulses on interface clock line 311. The interface clock is synchronized to serial clock 112. Clock generator 301 may output an interface clock pulse on each of the rising and falling edges of serial clock 112. Clocking of shift register 202 is controlled by the signal on interface clock line 311.
The initial address is stored by a plurality X of mutiplexers-with-latch referred to as 304-0 through 304-X, where X is an integer value equal to a predetermined number of multiplexers-with-latch. The initial address may be stored byte-by-byte.
Mutiplexer-with-latch 304-1 through mutiplexer-with-latch 304-X are coupled to the parallel bus 321 of shift register 302. A mutiplexer-with-latch that will store the current block of the m-bit address being transmitted is selected by decoding the row and column count signal provided on output bus 381 of row, column-count state machine 308. A block of the n-bit address may be a byte in length. After the current block has been clocked out of microcontroller 101 and into shift register 202, the address is latched into the selected one of mutiplexer-with-latch 304-0 through mutiplexer-with-latch 304-X by an interface clock pulse on line 311. After all n-bits of the address have been sent, the address is loaded into address counter 303.
AT9-97-210 ~ o Row and column select signals are generated by row, column-count state machine 308. Row, column-count state machine 308 receives interface clock pulses from clock generator 301 on interface clock line 311. A flow chart of an embodiment of a row, column-count state machine 308 is illustrated in FIGURE 4.
After reset, row, column-count state machine 308 accumulates interface serial clock pulses received on interface serial clock line 311. The logic to accumulate clock pulses is internal to row, column-count state machine 308 and is not shown in detail.
If the number of clock pulses accumulated has not reached Y, the row, column-count state machine 308 increments the column count, outputs the row and column-count and continues to interface serial clock cycles recf:ived on interface serial clock line 311. Y is a preselected integer corresponding to the length of a data block to be downloaded in a single download cycle. Furthermore, in an embodiment in which all m bits of data are downloaded on one cycle, Y would equal m. An embodiment downloading byte-byte would have a value of Y equal to eight. Moreover, in the present invention, after microcontroller 101 first sends an n-bit address, row, column-count state machine 308 may adaptively set Y. For example, in an embodiment where the entire address is sent as a block, Y is initially set equal to n. After the n-bits have been received, row, column-count state machine 308 may set Y to a new preselected value. This new preselected value would be m in an embodiment in which m data bits are to be downloaded in a block. In an embodiment in which both the n-bit address and the m-bit data are sent byte-by-byte, Y would have a fixed value of eight.
If the clock accumulator has reached Y, the row, column-count state machine increments the row count, resets the column count, and outputs the row and column count on its output bus 381. If a reset has not been received from microcontroller 101 on reset line 111, the row, column-count state machine 308 continues to accumulate clock cycles and continues to increment the row and column-counts as previously described.
If a reset has been received on reset line 111, then the row, column-count state machine 308 resets.
When the next operation commences, row, column-count state machine 308 begins accumulating clock cycles as they are received. The timing of the sequential operation of row, column-count state machine 308 is controlled by its internal clock (not shown). The internal clock need not be synchronized with the interface serial clock pulses on line 311, and the rate of the internal clock may be much greater than the rate of the interface serial clock pulses on line 311.
After sending the n-bit initial address, microcontroller 101 sends a command byte.
Command logic 309 decodes a row and column address received from row, column-count state machine 308 on output line 381. After the eight bits of the command byte have been clocked into shift register 302, command logic 309 latches the command byte which it receives on the parallel bus 321 of shift register 302. The state of the first bit of the command byte informs the seriallparallel interface 102 whether the operation to be performed is a read or a write. Command logic 309 ascertains the state of the first bit of the command byte and sets the state of read/write state machine 307 through output line 391 of command logic 309. In one embodiment of the present invention in which data transfer is byte-by-byte, if a write operation is to be performed, the last four bits of the command byte includes the lowest nibble of the first data byte to be downloaded, as describe above.
Read and write operations are controlled by readlwrite state machine 307. A
flow chart of an embodiment of a readlwrite state machine 307 is illustrated in FIGURE 5.
Readlwrite state machine 307 receives the output row and column addresses on the row and column address bus 381 by the row, column-count state machine 308. If the command logic has been addressed, then readlwrite state machine 307 tests the state of the output line 391 of command logic 309. If line 391 is in a read state, readlwrite state machine 307 asserts a read on RIV1I control bus 123. It then commands read data buffer 206 to latch the data on data bus 122 via line 371. The first block of data to be sent resides at the initial address loaded into address counter 303. If, after m-bits have been sent, a reset has not been asserted, RIW state machine 307 increments address counter 303 so that the address of the next block of data to be read appears on address bus 121.
Address counter 303 increments the address on address bus 121 in response to the address increment signal received from readlwrite state machine 307 via address counter increment line 372. After latching the data, read data buffer 206 clocks the data out via serial data line RxITxD 113. Clocking of the data is controlled by the serial clock pulses asserted by clock generator 301 on interface serial clock line 311. After the address counter 303 has been incremented, the cycle repeats until a reset is asserted on reset line 111 by microcontroller 101 (not shown).
If a write is to be performed, readlwrite state machine 307 accumulates the number of bits received. When m-bits have been received, read/write state machine 307 asserts a write on RIVII control bus 123. Read/write state machine 307 then tests to see if a reset has been asserted. If a reset has been asserted, readlwrite state machine 307 resets, otherwise, it increments address counter 303 via address counter increment line 372. This cycle repeats until a reset has been asserted on reset line 111 by microcontroller 101. The timing of the sequential operations of RIW state machine 307 is controlled by its internal clock (not shown). The internal clock may not be synchronized with the interface serial clock on line 311, and the rate of the internal clock may be much greater than the rate of the interface serial clock pulses on line 311..
In a write operation, data to be written to data byte 122 is received by data logic 305. Data may be transmitted from microcontroller 101 byte-by-byte. In such an embodiment the command byte includes the lowest nibble of the first data byte to be downloaded, as discussed above. Data lagic 305 receives the command byte on the parallel bus 321 of shift register 202. The next byte sent by microcontroller 101 through its serial port, RxITxD 113, contains the high nibble of the first data byte in its lower four bits, and the low nibble of the next data byte in its four upper bits. Data logic 305 receives the next byte transmitted by the parallel bus 321 of shift register 302 and latches this output byte. Data logic 305 then concatenates the low nibble and the high nibble of the first data byte and transfers it to data bus 122. Microcontroller 101 continues to transmit data on serial line RxITxD 113 in this interleaved fashion. Data logic 305 latches the output bytes as they are received and concatenates the low nibble and high nibble of each byte of data as described above. Latching of the data at data logic 305 is controlled by the interface serial clock pulses generated on line 311. It would be well understood by an artisan of ordinary skill that communication of data bytes using this method is independent of whether the mode of data representation is LSB first, or MSB first. After m-bits of data have been transmitted, the data is written to bus device 103 by readlwrite state machine 307 asserting a write state on R/W control bus 123. If, after m-bits have been sent, a reset has not been asserted, RIW state machine 307 increments address counter 303 so that the address of the next block of data to be read appears on address bus 121. Address counter 303 increments the address on address bus 121 in response to the address increment signal received from readlwrite state machine 307 via address counter increment line 372. Subsequent m-bit blocks of data are transmitted in this way until all the data to be downloaded has been sent, and microcontroller 101 asserts a reset on reset line 111. Seriallparallel interface 102 is then ready to begin the next operation.
The data processing system and methodology represented in the embodiments described herein are effective solutions to the associated problems of interfacing bus devices with an embedded controller having a limited number of parallel I/O
buses, and dynamic updating of the operating software of the data processing system.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A data processing system comprising:
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with a serial data port of processing unit, wherein a first data value communicated on said serial data port of said processing is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit, said parallel data and address busses operable communicating with bus device, and wherein said serial-to-parallel interface logic includes:
a shift register for receiving a serial data value, said shift register having a parallel output bus;
an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter;
and a control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuit configures said serial-to-parallel interface logic circuit to reflect an operation to be performed.
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with a serial data port of processing unit, wherein a first data value communicated on said serial data port of said processing is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit, said parallel data and address busses operable communicating with bus device, and wherein said serial-to-parallel interface logic includes:
a shift register for receiving a serial data value, said shift register having a parallel output bus;
an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter;
and a control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuit configures said serial-to-parallel interface logic circuit to reflect an operation to be performed.
2. The data processing system of claim 1 wherein said serial-to-parallel interface logic circuit further comprises:
a clock sequencing logic circuit coupled to said processing unit to receive a serial clock signal, said clock sequencing logic providing a first clock signal for clocking said shift register; an output data buffer for receiving a second data value on said parallel data bus of said serial-to-parallel interface logic circuit, said output data buffer operable for latching said second data value on receipt of said first clock signal from said clock sequencing logic, said output data buffer asserting said second data value on said serial data port of said serial-to-parallel interface logic circuit.
a clock sequencing logic circuit coupled to said processing unit to receive a serial clock signal, said clock sequencing logic providing a first clock signal for clocking said shift register; an output data buffer for receiving a second data value on said parallel data bus of said serial-to-parallel interface logic circuit, said output data buffer operable for latching said second data value on receipt of said first clock signal from said clock sequencing logic, said output data buffer asserting said second data value on said serial data port of said serial-to-parallel interface logic circuit.
3. The data processing system of claim 2 wherein said serial-to-parallel interface logic further comprises:
an input data buffer for receiving a download data value from said parallel output bus of said shift register, said input data buffer providing said download data value on said parallel data bus of said serial-to-parallel interface logic circuit, wherein said input data buffer is operable for latching said download data value.
an input data buffer for receiving a download data value from said parallel output bus of said shift register, said input data buffer providing said download data value on said parallel data bus of said serial-to-parallel interface logic circuit, wherein said input data buffer is operable for latching said download data value.
4. A microcontroller system comprising:
a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial data port of said microcontroller is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit;
a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value;
a shift register for receiving a serial data value, said shift register having a parallel output bus;
a clock sequencing logic circuit coupled to said microcontroller to receive a serial clock signal, said clock sequencing logic providing a first clock signal for clocking said shift register;
an output data buffer for receiving a second data value on said parallel data bus of said serial-to-parallel interface logic circuit, said output data buffer operable for latching said second data value on receipt of said first clock signal from said clock sequencing logic, said output data buffer asserting said second data value on said serial data port of said serial-to-parallel interface logic circuit;
an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter;
a control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuitry configures said serial-to-parallel interface logic circuit to reflect an operation to be performed; and an input data buffer for receiving a download data value from said parallel output bus of said shift register, said input data buffer providing said download data value on said parallel data bus of said serial-to-parallel interface logic circuit, wherein said input data buffer is operable for latching said download data value.
a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial data port of said microcontroller is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit;
a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value;
a shift register for receiving a serial data value, said shift register having a parallel output bus;
a clock sequencing logic circuit coupled to said microcontroller to receive a serial clock signal, said clock sequencing logic providing a first clock signal for clocking said shift register;
an output data buffer for receiving a second data value on said parallel data bus of said serial-to-parallel interface logic circuit, said output data buffer operable for latching said second data value on receipt of said first clock signal from said clock sequencing logic, said output data buffer asserting said second data value on said serial data port of said serial-to-parallel interface logic circuit;
an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter;
a control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuitry configures said serial-to-parallel interface logic circuit to reflect an operation to be performed; and an input data buffer for receiving a download data value from said parallel output bus of said shift register, said input data buffer providing said download data value on said parallel data bus of said serial-to-parallel interface logic circuit, wherein said input data buffer is operable for latching said download data value.
5. The microcontroller system of claim 4 wherein said control logic circuit provides a plurality of input data buffer control signals, and said input data buffer is operable for latching said download data value in response to said plurality of input data buffer control signals.
6. A method for communicating with a serial-to-parallel interface logic circuit comprising the steps of:
initializing said serial-to-parallel interface logic circuit;
sending a plurality of address bits to said serial-to-parallel interface logic circuit wherein at least a portion of said plurality of address bits comprises an address in an address space;
asserting a first command bit of a command value to select one of a read operation and a write operation;
sending said command value to said serial-to-parallel interface logic circuit;
performing one of said read operation and said write operation in response to the first command bit;
sending a reset signal to serial-to-parallel interface logic circuit, and wherein said first command bit indicates the write operation to be performed, and said write operation writes at least a first data bit to said serial-to-parallel interface logic circuit, said write operation writing a first data value to said serial-to-parallel interface logic circuit in byte increments, wherein said command value is a command byte, and wherein said step of performing said write operation further comprises the steps of:
loading a first nibble of said command byte with a second nibble of a first data byte;
sending said command byte to said serial-to-parallel interface logic circuit;
loading a first nibble of a first output byte with a second nibble of said first data byte, and a second nibble of said first output byte with a first nibble of a second data byte;
sending said first output byte to said serial-to-parallel interface logic circuit;
loading a first nibble of the second output byte with a second nibble of said second data byte, and a second nibble of said second output byte with the first nibble of a third data byte;
sending said second output byte to said serial-to-parallel interface logic circuit; and sending a plurality of next output bytes to said serial-to-parallel interface, wherein a first nibble of a next output byte is loaded with a second nibble of a previous data byte, and a second nibble of said next output byte as loaded with a first nibble of a next data byte.
initializing said serial-to-parallel interface logic circuit;
sending a plurality of address bits to said serial-to-parallel interface logic circuit wherein at least a portion of said plurality of address bits comprises an address in an address space;
asserting a first command bit of a command value to select one of a read operation and a write operation;
sending said command value to said serial-to-parallel interface logic circuit;
performing one of said read operation and said write operation in response to the first command bit;
sending a reset signal to serial-to-parallel interface logic circuit, and wherein said first command bit indicates the write operation to be performed, and said write operation writes at least a first data bit to said serial-to-parallel interface logic circuit, said write operation writing a first data value to said serial-to-parallel interface logic circuit in byte increments, wherein said command value is a command byte, and wherein said step of performing said write operation further comprises the steps of:
loading a first nibble of said command byte with a second nibble of a first data byte;
sending said command byte to said serial-to-parallel interface logic circuit;
loading a first nibble of a first output byte with a second nibble of said first data byte, and a second nibble of said first output byte with a first nibble of a second data byte;
sending said first output byte to said serial-to-parallel interface logic circuit;
loading a first nibble of the second output byte with a second nibble of said second data byte, and a second nibble of said second output byte with the first nibble of a third data byte;
sending said second output byte to said serial-to-parallel interface logic circuit; and sending a plurality of next output bytes to said serial-to-parallel interface, wherein a first nibble of a next output byte is loaded with a second nibble of a previous data byte, and a second nibble of said next output byte as loaded with a first nibble of a next data byte.
7. A microcontroller system comprising:
a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial date port of said microcontroller is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit; and a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value, wherein said serial-to-parallel interface logic circuit further comprises:
a shift register for receiving serial data value, said shift register having a parallel output bus;
a clock sequencing logic circuit coupled to said microcontroller to receive a serial clock signal, said clock sequencing logic providing a first clock signal for clocking said shift register; an output data buffer for receiving a second data value on said parallel data bus of said-to-parallel interface logic circuit, said output data buffer operable for latching said data value on receipt of said first clock signal from said clock sequencing logic, said output data buffer asserting said second data value on said serial data port of said serial-to-parallel interface logic circuit;
an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter;
a control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuitry configures said serial-to-parallel interface logic circuit to reflect an operation to be performed; and an input data buffer for receiving a download data value from said parallel output bus of said shift register, said input data buffer providing said download data value on said parallel data bus on said serial-to-parallel interface logic circuit, wherein said input data value is operable for latching said download data value, and wherein said control logic circuitry further comprise:
command logic circuitry adaptable for receiving said command value, and for providing a first command signal;
a read/write state machine adaptable for controlling read/write operations of said serial-to-parallel interface logic circuit in response to the first command signal received from said command logic circuitry; and a row, column-count state machine for outputting a plurality of row/column register select signals, said plurality of row/column register select signals generated in response to a plurality of clock signals from said clock sequencing logic, wherein said address logic circuit includes a plurality of address registers adaptable for selection in response to said plurality of row/column select signals, and said input data buffer is adaptable for selection in response to said plurality of row/column select signals.
a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial date port of said microcontroller is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit; and a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value, wherein said serial-to-parallel interface logic circuit further comprises:
a shift register for receiving serial data value, said shift register having a parallel output bus;
a clock sequencing logic circuit coupled to said microcontroller to receive a serial clock signal, said clock sequencing logic providing a first clock signal for clocking said shift register; an output data buffer for receiving a second data value on said parallel data bus of said-to-parallel interface logic circuit, said output data buffer operable for latching said data value on receipt of said first clock signal from said clock sequencing logic, said output data buffer asserting said second data value on said serial data port of said serial-to-parallel interface logic circuit;
an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter;
a control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuitry configures said serial-to-parallel interface logic circuit to reflect an operation to be performed; and an input data buffer for receiving a download data value from said parallel output bus of said shift register, said input data buffer providing said download data value on said parallel data bus on said serial-to-parallel interface logic circuit, wherein said input data value is operable for latching said download data value, and wherein said control logic circuitry further comprise:
command logic circuitry adaptable for receiving said command value, and for providing a first command signal;
a read/write state machine adaptable for controlling read/write operations of said serial-to-parallel interface logic circuit in response to the first command signal received from said command logic circuitry; and a row, column-count state machine for outputting a plurality of row/column register select signals, said plurality of row/column register select signals generated in response to a plurality of clock signals from said clock sequencing logic, wherein said address logic circuit includes a plurality of address registers adaptable for selection in response to said plurality of row/column select signals, and said input data buffer is adaptable for selection in response to said plurality of row/column select signals.
8. The microcontroller system of claim 1 wherein said plurality of address registers further comprise a plurality of multiplexers-with-latch.
9. A microcontroller system comprising:
a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial data port of said microcontroller is presented as a parallel data value on said parallel data bus said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said parallel interface logic circuit; and a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value, wherein said serial-to-parallel interface logic circuit further comprises:
a shift register for receiving a serial data value, said shift register having a parallel output bus;
a clock generator for receiving an external serial clock signal synchronized with said serial data value, said clock generator generating a plurality of interface serial clock pulses in response to said external serial clock signal, wherein said shift register clocks in said serial data value in response to said plurality of interface serial clock pulses;
a state machine, wherein said state machine generates a row/column address signal in response to said plurality of interface serial clock pulses from said clock generator;
a multiplexer-with-latch for storing an address data value received on said parallel output bus of said shift register, said multiplexer-with-latch being selected for receiving said address data value in response to said row/column address signal from said state machine;
an address counter for selecting an address on the parallel address bus of said serial-to-parallel interface logic circuit, wherein said address counter receives an initial address value from said address data value stored in said multiplexer-with-latch, said address counter incrementing the initial address value in response to an address counter increment signal;
a command logic circuit for receiving a command value from said parallel output bus of said shift register, said command logic decoding said command value to select one of a read operation and a write operation, said command logic circuit generating an operation select signal in response to said command value;
a read data buffer for receiving a second data value from the parallel data bus of said serial-to-parallel interface logic, said read data buffer operable for sending said second data value out a serial data line, said second data value being clocked onto said serial data line in response to said plurality of interface serial clock pulses from said clock generator;
a read/write state machine for receiving said operation select signal from said command logic circuit, said read/write state machine sending a control signal to the parallel data bus of said serial-to-parallel interface logic, and an enable signal to said read data buffer in response thereto, wherein said read/write state machine receives said plurality of interface serial clock pulses from said clock generators, and said row/column address signal from said state machine, said read/write state machine sending said address counter increment signal to said address counter in response thereto; and a data logic circuit for receiving the serial data value from said parallel output bus of said shift register, said data logic circuit operable for selecting in response to said row/column address signal, and outputting said serial data value on said parallel data bus of said serial-to-parallel interface logic circuit.
a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;
a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial data port of said microcontroller is presented as a parallel data value on said parallel data bus said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said parallel interface logic circuit; and a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value, wherein said serial-to-parallel interface logic circuit further comprises:
a shift register for receiving a serial data value, said shift register having a parallel output bus;
a clock generator for receiving an external serial clock signal synchronized with said serial data value, said clock generator generating a plurality of interface serial clock pulses in response to said external serial clock signal, wherein said shift register clocks in said serial data value in response to said plurality of interface serial clock pulses;
a state machine, wherein said state machine generates a row/column address signal in response to said plurality of interface serial clock pulses from said clock generator;
a multiplexer-with-latch for storing an address data value received on said parallel output bus of said shift register, said multiplexer-with-latch being selected for receiving said address data value in response to said row/column address signal from said state machine;
an address counter for selecting an address on the parallel address bus of said serial-to-parallel interface logic circuit, wherein said address counter receives an initial address value from said address data value stored in said multiplexer-with-latch, said address counter incrementing the initial address value in response to an address counter increment signal;
a command logic circuit for receiving a command value from said parallel output bus of said shift register, said command logic decoding said command value to select one of a read operation and a write operation, said command logic circuit generating an operation select signal in response to said command value;
a read data buffer for receiving a second data value from the parallel data bus of said serial-to-parallel interface logic, said read data buffer operable for sending said second data value out a serial data line, said second data value being clocked onto said serial data line in response to said plurality of interface serial clock pulses from said clock generator;
a read/write state machine for receiving said operation select signal from said command logic circuit, said read/write state machine sending a control signal to the parallel data bus of said serial-to-parallel interface logic, and an enable signal to said read data buffer in response thereto, wherein said read/write state machine receives said plurality of interface serial clock pulses from said clock generators, and said row/column address signal from said state machine, said read/write state machine sending said address counter increment signal to said address counter in response thereto; and a data logic circuit for receiving the serial data value from said parallel output bus of said shift register, said data logic circuit operable for selecting in response to said row/column address signal, and outputting said serial data value on said parallel data bus of said serial-to-parallel interface logic circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/827,744 | 1997-04-10 | ||
| US08/827,744 US5812881A (en) | 1997-04-10 | 1997-04-10 | Handshake minimizing serial to parallel bus interface in a data processing system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2231362A1 CA2231362A1 (en) | 1998-10-10 |
| CA2231362C true CA2231362C (en) | 2002-02-05 |
Family
ID=25250034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002231362A Expired - Fee Related CA2231362C (en) | 1997-04-10 | 1998-03-09 | A data maximizing serial to parallel bus interface in a data processing system and method therefor |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US5812881A (en) |
| JP (1) | JPH10326254A (en) |
| KR (1) | KR100265141B1 (en) |
| CN (1) | CN1199116C (en) |
| CA (1) | CA2231362C (en) |
| HK (1) | HK1015050A1 (en) |
| MY (1) | MY129495A (en) |
| SG (1) | SG72796A1 (en) |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6453334B1 (en) | 1997-06-16 | 2002-09-17 | Streamtheory, Inc. | Method and apparatus to allow remotely located computer programs and/or data to be accessed on a local computer in a secure, time-limited manner, with persistent caching |
| US6191713B1 (en) * | 1998-08-04 | 2001-02-20 | Intel Corporation | Conversion between serial bus cycles and parallel port commands using a state machine |
| US6256687B1 (en) * | 1998-08-04 | 2001-07-03 | Intel Corporation | Managing data flow between a serial bus device and a parallel port |
| US6119195A (en) * | 1998-08-04 | 2000-09-12 | Intel Corporation | Virtualizing serial bus information point by address mapping via a parallel port |
| US6260092B1 (en) * | 1998-09-24 | 2001-07-10 | Philips Semiconductors, Inc. | Point to point or ring connectable bus bridge and an interface with method for enhancing link performance in a point to point connectable bus bridge system using the fiber channel |
| WO2000025431A1 (en) * | 1998-10-23 | 2000-05-04 | Octave Communications, Inc. | Serial-to-parallel/parallel-to-serial conversion engine |
| CA2402886C (en) | 2000-03-14 | 2012-02-14 | James Hardie Research Pty Limited | Fiber cement building materials with low density additives |
| CN1246246C (en) | 2000-10-04 | 2006-03-22 | 詹姆斯哈迪国际财金公司 | Fiber cement composition materials using cellulose fibers loaded with inorganic and/or organic substances |
| EP1330571B1 (en) | 2000-10-17 | 2006-04-19 | James Hardie International Finance B.V. | Method of manufacturing a fiber reinforced cement composite material, a composite building material and a material formulation |
| US8831995B2 (en) | 2000-11-06 | 2014-09-09 | Numecent Holdings, Inc. | Optimized server for streamed applications |
| US7062567B2 (en) | 2000-11-06 | 2006-06-13 | Endeavors Technology, Inc. | Intelligent network streaming and execution system for conventionally coded applications |
| KR100391169B1 (en) * | 2000-11-25 | 2003-07-12 | 엘지전자 주식회사 | Serial communication apparatus for processor and external unit |
| US7969702B2 (en) * | 2000-12-06 | 2011-06-28 | Motorola Mobility, Inc. | Intelligent power supply and cable system |
| US6816935B1 (en) | 2001-03-02 | 2004-11-09 | Advanced Micro Devices, Inc. | Interrupt and status reporting structure and method for a timeslot bus |
| US7594026B1 (en) * | 2001-04-25 | 2009-09-22 | Zarlink Semiconductor (U.S.) Inc. | Method and apparatus for multi-phy communication without an ATM bus master |
| US7069464B2 (en) | 2001-11-21 | 2006-06-27 | Interdigital Technology Corporation | Hybrid parallel/serial bus interface |
| DE60226910D1 (en) * | 2001-11-21 | 2008-07-10 | Interdigital Patent Corp | User equipment (UE) with a hybrid parallel-serial bus interface |
| ES2287345T3 (en) * | 2001-11-21 | 2007-12-16 | Interdigital Technology Corporation | BASE STATION THAT HAS A HYBRID SERIAL / PARALLEL BUS INTERFACE. |
| EP1446723B1 (en) * | 2001-11-21 | 2007-07-18 | Interdigital Technology Corporation | Method employed by a base station for transferring data |
| US20030167347A1 (en) * | 2002-02-11 | 2003-09-04 | Combs James Lee | Home network printer adapter |
| US6829663B1 (en) * | 2002-08-21 | 2004-12-07 | Adaptec, Inc. | Method and apparatus for the synchronous control of a serial interface |
| US6993616B2 (en) * | 2002-10-01 | 2006-01-31 | Analog Devices, Inc. | Read-write interface system and method that accesses a leading bit in advance of a read operation |
| US7993570B2 (en) | 2002-10-07 | 2011-08-09 | James Hardie Technology Limited | Durable medium-density fibre cement composite |
| NZ541250A (en) | 2003-01-09 | 2008-09-26 | James Hardie Int Finance Bv | Fibre cement composite materials using bleached cellulose fibres |
| US7246199B2 (en) * | 2003-05-29 | 2007-07-17 | Elantec Semiconductor, Inc. | Double buffering of serial transfers |
| US20050002728A1 (en) * | 2003-07-01 | 2005-01-06 | Isaac Weiser | Plastic connector for connecting parts and method therefor |
| DE10350388A1 (en) * | 2003-10-28 | 2005-06-02 | Micronas Gmbh | Bus system with few control lines |
| CN1321382C (en) * | 2004-01-20 | 2007-06-13 | 宏达国际电子股份有限公司 | Serial/parallel data converting module and relative computer system |
| WO2006055445A2 (en) | 2004-11-13 | 2006-05-26 | Stream Theory, Inc. | Hybrid local/remote streaming |
| US7757295B1 (en) * | 2005-02-09 | 2010-07-13 | Lsi Corporation | Methods and structure for serially controlled chip security |
| WO2006102621A2 (en) | 2005-03-23 | 2006-09-28 | Stream Theory, Inc. | System and method for tracking changes to files in streaming applications |
| US8024523B2 (en) | 2007-11-07 | 2011-09-20 | Endeavors Technologies, Inc. | Opportunistic block transmission with time constraints |
| US8261345B2 (en) | 2006-10-23 | 2012-09-04 | Endeavors Technologies, Inc. | Rule-based application access management |
| EP2140556A1 (en) * | 2007-05-03 | 2010-01-06 | Icera Canada ULC | System and method for transceiver control of peripheral components |
| US8892738B2 (en) | 2007-11-07 | 2014-11-18 | Numecent Holdings, Inc. | Deriving component statistics for a stream enabled application |
| US8209927B2 (en) | 2007-12-20 | 2012-07-03 | James Hardie Technology Limited | Structural fiber cement building materials |
| US7941570B2 (en) * | 2008-02-14 | 2011-05-10 | International Business Machines Corporation | Bi-directional data transfer within a single I/O operation |
| US7840717B2 (en) * | 2008-02-14 | 2010-11-23 | International Business Machines Corporation | Processing a variable length device command word at a control unit in an I/O processing system |
| US7827342B2 (en) * | 2008-11-21 | 2010-11-02 | Texas Instruments Incorporated | Readback registers |
| DE102011007437A1 (en) | 2010-11-15 | 2012-05-16 | Continental Teves Ag & Co. Ohg | Method and circuit arrangement for data transmission between processor modules |
| US10389343B2 (en) * | 2013-09-30 | 2019-08-20 | Integrated Device Technology, Inc. | High speed, low power, isolated buffer |
| US9529764B1 (en) * | 2013-10-29 | 2016-12-27 | Exelis, Inc. | Near-to-eye display hot shoe communication line |
| US10110232B2 (en) | 2015-06-30 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiplexer and latch system |
| CN105205027B (en) * | 2015-09-14 | 2018-08-21 | 江苏金智科技股份有限公司 | Bus data access method, device and the power distribution network terminal equipment of power distribution network terminal |
| CN105242601B (en) * | 2015-10-09 | 2018-05-08 | 贵州智达科技有限责任公司 | A kind of more compatible both-way communication methods of electric heater serial ports |
| US11331924B2 (en) * | 2018-12-03 | 2022-05-17 | Hewlett-Packard Development Company, L.P. | Logic circuitry package |
| CN110046113B (en) * | 2019-05-06 | 2024-02-09 | 华峰测控技术(天津)有限责任公司 | SDRAM control system and SDRAM control method based on FPGA |
| CN112540944B (en) * | 2020-12-15 | 2022-11-25 | 安徽皖通邮电股份有限公司 | Parallel bus protocol and method for realizing data interaction between boards based on protocol |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4447804A (en) * | 1981-06-22 | 1984-05-08 | The United States Of America As Represented By The Secretary Of The Navy | Serial to parallel data conversion interface circuit |
| US4728930A (en) * | 1987-06-30 | 1988-03-01 | The United States Of America As Represented By The Secretary Of The Navy | Parallel-to-serial-data interface-adaptor |
| US5086388A (en) * | 1988-03-18 | 1992-02-04 | Hitachi Maxell, Ltd. | Semiconductor serial/parallel-parallel/serial file memory and storage system |
| US5005151A (en) * | 1988-05-13 | 1991-04-02 | Dallas Semiconductor Corporation | Interleaved arbitration scheme for interfacing parallel and serial ports to a parallel system port |
| US5016011A (en) * | 1988-06-10 | 1991-05-14 | General Electric Company | Increased performance of digital integrated circuits by processing with multiple-bit-width digits |
| US5025257A (en) * | 1988-06-10 | 1991-06-18 | General Electric Company | Increased performance of digital integrated circuits by processing with multiple-bit-width digits |
| US5099481A (en) * | 1989-02-28 | 1992-03-24 | Integrated Device Technology, Inc. | Registered RAM array with parallel and serial interface |
| US5457786A (en) * | 1990-07-03 | 1995-10-10 | Texas Instruments Incorporated | Serial data interface with circular buffer |
| USH1472H (en) * | 1992-09-11 | 1995-08-01 | The United States Of America As Represented By The Secretary Of The Navy | Computer interface adapter for supporting data communication between a parallel signal device and a serial signal device |
| US5602780A (en) * | 1993-10-20 | 1997-02-11 | Texas Instruments Incorporated | Serial to parallel and parallel to serial architecture for a RAM based FIFO memory |
| FR2721416B1 (en) * | 1994-06-20 | 1996-08-30 | Met | Device for routing data cells in asynchronous transfer mode. |
-
1997
- 1997-04-10 US US08/827,744 patent/US5812881A/en not_active Expired - Lifetime
-
1998
- 1998-02-06 KR KR1019980003470A patent/KR100265141B1/en not_active IP Right Cessation
- 1998-03-04 MY MYPI98000944A patent/MY129495A/en unknown
- 1998-03-09 CA CA002231362A patent/CA2231362C/en not_active Expired - Fee Related
- 1998-03-19 CN CNB981058280A patent/CN1199116C/en not_active Expired - Lifetime
- 1998-03-19 SG SG1998000584A patent/SG72796A1/en unknown
- 1998-04-03 JP JP10091248A patent/JPH10326254A/en active Pending
- 1998-06-15 US US09/097,477 patent/US6122683A/en not_active Expired - Lifetime
-
1999
- 1999-01-05 HK HK99100014A patent/HK1015050A1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| SG72796A1 (en) | 2000-05-23 |
| HK1015050A1 (en) | 1999-10-08 |
| JPH10326254A (en) | 1998-12-08 |
| MY129495A (en) | 2007-04-30 |
| CN1199116C (en) | 2005-04-27 |
| KR19980079678A (en) | 1998-11-25 |
| US6122683A (en) | 2000-09-19 |
| CA2231362A1 (en) | 1998-10-10 |
| CN1195821A (en) | 1998-10-14 |
| KR100265141B1 (en) | 2000-10-02 |
| US5812881A (en) | 1998-09-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2231362C (en) | A data maximizing serial to parallel bus interface in a data processing system and method therefor | |
| US9501964B2 (en) | Semiconductor device and data processing system selectively operating as one of a big endian or little endian system | |
| KR101507194B1 (en) | Serial interface nand | |
| US5794033A (en) | Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device | |
| US8122202B2 (en) | Reduced pin count interface | |
| KR19980033054A (en) | Programmable Memory Access | |
| US6586968B1 (en) | Programmable bit ordering for serial port | |
| EP0757316B1 (en) | External device selection unit for data processor | |
| US5923894A (en) | Adaptable input/output pin control | |
| EP0797148A1 (en) | Multi-mode cache structure | |
| US20040078500A1 (en) | Serial peripheral interface and related methods | |
| US20060284876A1 (en) | Method and apparatus for programming an input/output device over a serial bus | |
| US7600068B2 (en) | Programmable control interface device | |
| CA2026768C (en) | Extended addressing using sub-addressed segment registers | |
| US6516398B2 (en) | Program-downloadable data processing system and method for accessing memory by using a unified memory space therein | |
| KR20060130033A (en) | Method and system for direct access to a non-memory mapped device memory | |
| US7209252B2 (en) | Memory module, printer assembly, and method for storing printer code | |
| US7506133B2 (en) | Method and apparatus for high speed addressing of a memory space from a relatively small address space | |
| KR100238313B1 (en) | Apparatus and method for interfacing between cpu and peripheral device | |
| JP3959137B2 (en) | Data processor | |
| KR0147476B1 (en) | I/o configuration setting system of computer and method thereof | |
| KR100346268B1 (en) | Data bus control system | |
| KR100192776B1 (en) | A circuit for sharing a memory | |
| JPH0721143A (en) | Output selecting circuit | |
| JP2005182410A (en) | Information processing device and information processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |