CA2231636C - Self centering frequency multiplier - Google Patents
Self centering frequency multiplier Download PDFInfo
- Publication number
- CA2231636C CA2231636C CA002231636A CA2231636A CA2231636C CA 2231636 C CA2231636 C CA 2231636C CA 002231636 A CA002231636 A CA 002231636A CA 2231636 A CA2231636 A CA 2231636A CA 2231636 C CA2231636 C CA 2231636C
- Authority
- CA
- Canada
- Prior art keywords
- frequency
- circuit
- response
- vco
- control signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000002955 isolation Methods 0.000 claims description 7
- 230000003466 anti-cipated effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/02—Automatic frequency control
- H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
- H03J7/08—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using varactors, i.e. voltage variable reactive diodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
Abstract
A frequency multiplier (120) having a tunable resonant circuit (122), is anticipated for use with a frequency synthesizer (100) having a Voltage Controlled Oscillator (110). The VCO control line (116) voltage establishes the VCO (110) fundamental frequency (fo) as well as the resonant circuit (122) center frequency, such that the resonant circuit (122) frequency response will track a desired harmonic component within the multiplier output (130) even as the VCO control line (116) voltage and the fundamental frequency (fo) change in response to control line variation.
Description
SELF CENTERING FREQUENCY MULTIPLIER
TECHNICAL FIELD
This invention relates in general to frequency synthesizer eireuits and partieularly to frequency multiplier circuits used in association with frequency synthesizers. Specifically, the present invention relates to an apparatus for controlling the band center of a narrow band multiplier used in assoeiation with a Phase Loeked Loop (PLL) frequeney synthesizer.
BACKGROUND
Phase Locked Loop (PLL) frequency synthesizers are well known in the art. One of the more recognizable components of a conventional PLL frequency synthesizer is the voltage controlled oscillator (VCO). The primary function of the VCO is to provide a frequency response output as a function of voltage input signal amplitude.
One application to which a VCO controlled frequency synthesizer can be placed is that of a frequency multiplier. In such an application, the VCO output of the PLL frequency synthesizer is connected to a multiplier circuit that generates a product representation of the VCO
output. The advantages typically associated with such a multiplier is the ability to multiply the output of the VCO
such that a plurality of harmonic components of a single output can be generated simultaneously. By way of example, such an operation may be used to generate a VCO signal that is not in band with a transmitted or received signal.
Despite the advantages associated therewith, one of the remaining challenges associated with this type multiplier is the ability to maximize both the harmonic content and sub-harmonic rejection during a wide band operation when a narrow band resonant tank is employed for frequency selection. Traditional methods must either accep-t inferior performance; namely reduced noise isolation and decreased harmonic rejection, or incur the additional expense associated with complex cascade filter stage designs which are typically labor intensive, expensive, and susceptible to environmentally induced variations such as temperature, humidity, altitude, etc.
It would be extremely advantageous therefore to provide a frequency multiplier circuit for use with a PLL
or other frequency synthesizer application, which exhibits high harmonic to fundamental rejection and exceptional noise isolation all in a simple design which is cost efficient, robust, and capable of operating across a wide bandwidth of operation, such as, for example, 800-900 Megahertz (MHz).
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a Phase-Locked Loop ~PLL) circuit employing the self centering frequency multiplier circuit of the present inventioni FIG. 2 is a detailed circuit diagram of the self cente:ring frequency multiplier circuit of FIG. l;
FIG. 3 is a diagram representing the output of the self centering frequency multiplier of the present invention during operation.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures, in which like reference numerals are carried forward.
FIG. 1 is a block diagram of Phase Locked Loop ~PLL) circu-it 100 employing the self centering frequency multiplier circuit 120 of the present invention. As depicted, PLL circuit 100 employs a reference oscillator 102, reference divider 104, phase detector 106, loop filter 108, VCO 110, and loop divider 112. Such circuits are known in the art and will not, therefore, be described in great detail. The interested reader may refer to U.S.
Patent No. 4,975,650 Martin, issued December 4, 1990, and assigned to the assignee of the present application, for additional detail on circuit 100 theory, design, and operation. Suffice it to say, however, VCO output (fO) is estab:Lished by setting or programming the value N of loop divider 112. The resultant VC0 control voltage 116 will thereafter determine the frequency (fO~ of VCO 110.
During operation, VC0 output (fO) is supplied to frequency multiplier circuit 120 having a gain stage 126 which generates an output 130 comprised of the fundamental frequency (fO) and a plurality of harmonic components (2Jo~
3fo, 4fo etc.,) In order to maximize the harmonic content and sub-harmonic rejection during a wide band operation, the VC0 control line 116 voltage is communicated to a resonant tank structure 122 via noise isolation stage 124.
As will be discussed herein, the VCO control line voltage alters the reactance of a variable reactance device within the resonant tank circuit 122 to tune or adjust the band center of the resonate tank structure 122, thereby selecting a desired harmonic components (2fo~ 3fO, 4fO
etc.,) of the multiplier output to derive a desired signal 140. Because the VC0 control line operates to control both the V('0 110 and the resonant tank circuit 122, the resonant tank circuit 122 frequency response will now track a desired harmonic component even as the VCO control line voltage changes in amplitude. Herein lies the advantage of the present invention; namely, the VC0 control line 116 voltage is a control signal having an amplitude that corresponds to the VCO 110 output frequency (fO) and likewise corresponds to the desired harmonic component of the multiplier output, such as, for example, (2fo). In accordance, the self centering multiplier circuit 120 of the present invention will employ a narrow band design for better noise isolation and harmonic rejection.
FIG. 2 is a detailed circuit diagram of a preferred embodiment of the self centering frequency multiplier circuit of FIG. 1. As depicted, the circuit 120 comprises a gai:n stage 126 that receives an input from VCO 110 of FIG. 1 and amplifies the input by some value K. A resonant tank circuit 122 is coupled to the gain stage 126 and employs a variable reactance stage 200, such as a voltage variable capacitor ( WC), a varactor, or any other variable reactance device now known or later created, and capable of receiving a control signal from noise isolation circuit 124 and altering the reactance of the variable reactance stage 200 in response to control signal change, to es-tablish a response for the resonant tank circuit 122 that selects a desired harmonic frequency component, such as, for example (2fo); from among the plurality of harmonic components within gain stage output.
As will be appreciated by those skilled in the art after review hereof, the resonant tank circuit 122 provides a high impedance response at the desired harmonic frequency while providing a low impedance response at or around the fundamental frequency (fO). This can be best seen and understood with reference to FIG. 3.
FIG. 3 is a diagram representing the desired output 140 o:f the self centering frequency multiplier 120 of the present invention. As will be appreciated upon review thereof, the area denoted as 300 is the low impedance response established by resonant tank circuit elements L
and C, of FIG. 2 in order to provide fundamental frequency ( f o ) rejection. The curves designated 301, 302 and 303, represent respective desired frequency signals selected in response to changes in the VCO control line voltage that generated respective fundamental frequencies f 1, f2, and f3. Since the VC0 control line voltage operates to control both the fundamental frequency (fo ) output by the VC0 110 as well as the resonant tank circuit 122, the resonant tank circuit 122 frequency response will now track a desired harmonic component even as the VCO control line 116 voltage changes in amplitude as clearly pointed out in FIG.
3.
While the preferred embodiment of the invention has been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims. For example, the variable reactance stage 200 of FIG. 2 and control line 116 may be replaced by a device and control line arrangement that are not of the voltage control type.
Notwithstanding, it will be appreciated by those skilled in the art that the invention of the present application operates to provide a self-centering frequency multiplier that avoids the limitations of the prior art;
namely, high-cost or noise-prone frequency multiplication.
What is claimed is:
TECHNICAL FIELD
This invention relates in general to frequency synthesizer eireuits and partieularly to frequency multiplier circuits used in association with frequency synthesizers. Specifically, the present invention relates to an apparatus for controlling the band center of a narrow band multiplier used in assoeiation with a Phase Loeked Loop (PLL) frequeney synthesizer.
BACKGROUND
Phase Locked Loop (PLL) frequency synthesizers are well known in the art. One of the more recognizable components of a conventional PLL frequency synthesizer is the voltage controlled oscillator (VCO). The primary function of the VCO is to provide a frequency response output as a function of voltage input signal amplitude.
One application to which a VCO controlled frequency synthesizer can be placed is that of a frequency multiplier. In such an application, the VCO output of the PLL frequency synthesizer is connected to a multiplier circuit that generates a product representation of the VCO
output. The advantages typically associated with such a multiplier is the ability to multiply the output of the VCO
such that a plurality of harmonic components of a single output can be generated simultaneously. By way of example, such an operation may be used to generate a VCO signal that is not in band with a transmitted or received signal.
Despite the advantages associated therewith, one of the remaining challenges associated with this type multiplier is the ability to maximize both the harmonic content and sub-harmonic rejection during a wide band operation when a narrow band resonant tank is employed for frequency selection. Traditional methods must either accep-t inferior performance; namely reduced noise isolation and decreased harmonic rejection, or incur the additional expense associated with complex cascade filter stage designs which are typically labor intensive, expensive, and susceptible to environmentally induced variations such as temperature, humidity, altitude, etc.
It would be extremely advantageous therefore to provide a frequency multiplier circuit for use with a PLL
or other frequency synthesizer application, which exhibits high harmonic to fundamental rejection and exceptional noise isolation all in a simple design which is cost efficient, robust, and capable of operating across a wide bandwidth of operation, such as, for example, 800-900 Megahertz (MHz).
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a Phase-Locked Loop ~PLL) circuit employing the self centering frequency multiplier circuit of the present inventioni FIG. 2 is a detailed circuit diagram of the self cente:ring frequency multiplier circuit of FIG. l;
FIG. 3 is a diagram representing the output of the self centering frequency multiplier of the present invention during operation.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures, in which like reference numerals are carried forward.
FIG. 1 is a block diagram of Phase Locked Loop ~PLL) circu-it 100 employing the self centering frequency multiplier circuit 120 of the present invention. As depicted, PLL circuit 100 employs a reference oscillator 102, reference divider 104, phase detector 106, loop filter 108, VCO 110, and loop divider 112. Such circuits are known in the art and will not, therefore, be described in great detail. The interested reader may refer to U.S.
Patent No. 4,975,650 Martin, issued December 4, 1990, and assigned to the assignee of the present application, for additional detail on circuit 100 theory, design, and operation. Suffice it to say, however, VCO output (fO) is estab:Lished by setting or programming the value N of loop divider 112. The resultant VC0 control voltage 116 will thereafter determine the frequency (fO~ of VCO 110.
During operation, VC0 output (fO) is supplied to frequency multiplier circuit 120 having a gain stage 126 which generates an output 130 comprised of the fundamental frequency (fO) and a plurality of harmonic components (2Jo~
3fo, 4fo etc.,) In order to maximize the harmonic content and sub-harmonic rejection during a wide band operation, the VC0 control line 116 voltage is communicated to a resonant tank structure 122 via noise isolation stage 124.
As will be discussed herein, the VCO control line voltage alters the reactance of a variable reactance device within the resonant tank circuit 122 to tune or adjust the band center of the resonate tank structure 122, thereby selecting a desired harmonic components (2fo~ 3fO, 4fO
etc.,) of the multiplier output to derive a desired signal 140. Because the VC0 control line operates to control both the V('0 110 and the resonant tank circuit 122, the resonant tank circuit 122 frequency response will now track a desired harmonic component even as the VCO control line voltage changes in amplitude. Herein lies the advantage of the present invention; namely, the VC0 control line 116 voltage is a control signal having an amplitude that corresponds to the VCO 110 output frequency (fO) and likewise corresponds to the desired harmonic component of the multiplier output, such as, for example, (2fo). In accordance, the self centering multiplier circuit 120 of the present invention will employ a narrow band design for better noise isolation and harmonic rejection.
FIG. 2 is a detailed circuit diagram of a preferred embodiment of the self centering frequency multiplier circuit of FIG. 1. As depicted, the circuit 120 comprises a gai:n stage 126 that receives an input from VCO 110 of FIG. 1 and amplifies the input by some value K. A resonant tank circuit 122 is coupled to the gain stage 126 and employs a variable reactance stage 200, such as a voltage variable capacitor ( WC), a varactor, or any other variable reactance device now known or later created, and capable of receiving a control signal from noise isolation circuit 124 and altering the reactance of the variable reactance stage 200 in response to control signal change, to es-tablish a response for the resonant tank circuit 122 that selects a desired harmonic frequency component, such as, for example (2fo); from among the plurality of harmonic components within gain stage output.
As will be appreciated by those skilled in the art after review hereof, the resonant tank circuit 122 provides a high impedance response at the desired harmonic frequency while providing a low impedance response at or around the fundamental frequency (fO). This can be best seen and understood with reference to FIG. 3.
FIG. 3 is a diagram representing the desired output 140 o:f the self centering frequency multiplier 120 of the present invention. As will be appreciated upon review thereof, the area denoted as 300 is the low impedance response established by resonant tank circuit elements L
and C, of FIG. 2 in order to provide fundamental frequency ( f o ) rejection. The curves designated 301, 302 and 303, represent respective desired frequency signals selected in response to changes in the VCO control line voltage that generated respective fundamental frequencies f 1, f2, and f3. Since the VC0 control line voltage operates to control both the fundamental frequency (fo ) output by the VC0 110 as well as the resonant tank circuit 122, the resonant tank circuit 122 frequency response will now track a desired harmonic component even as the VCO control line 116 voltage changes in amplitude as clearly pointed out in FIG.
3.
While the preferred embodiment of the invention has been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims. For example, the variable reactance stage 200 of FIG. 2 and control line 116 may be replaced by a device and control line arrangement that are not of the voltage control type.
Notwithstanding, it will be appreciated by those skilled in the art that the invention of the present application operates to provide a self-centering frequency multiplier that avoids the limitations of the prior art;
namely, high-cost or noise-prone frequency multiplication.
What is claimed is:
Claims (6)
1. A self centering frequency multiplier circuit comprising:
a voltage controlled oscillator (VCO) for receiving a control signal and providing a frequency output in response thereto;
a multiplier circuit, coupled to the VCO, for receiving the frequency output and providing a product signal in response thereto, said product signal having a fundamental frequency and a plurality of harmonic components; and a resonant circuit, coupled to the multiplier circuit and having a voltage variable reactance stage, for receiving the control signal and altering a reactance of the voltage variable reactance stage in response to the control signal amplitude, to establish a frequency response for the resonant circuit that selects a desired harmonic frequency component from among the plurality of harmonic components.
a voltage controlled oscillator (VCO) for receiving a control signal and providing a frequency output in response thereto;
a multiplier circuit, coupled to the VCO, for receiving the frequency output and providing a product signal in response thereto, said product signal having a fundamental frequency and a plurality of harmonic components; and a resonant circuit, coupled to the multiplier circuit and having a voltage variable reactance stage, for receiving the control signal and altering a reactance of the voltage variable reactance stage in response to the control signal amplitude, to establish a frequency response for the resonant circuit that selects a desired harmonic frequency component from among the plurality of harmonic components.
2. The circuit of claim 1 further comprising an isolation circuit, coupled to the VCO and the multiplier, for receiving the control signal and feeding the control signal forward to the voltage variable reactance stage of the resonant circuit.
3. The circuit of claim 1 wherein the resonant circuit provides a high impedance response at the desired harmonic frequency.
4. The circuit of claim 1 wherein the resonant circuit provides a low impedance response at the fundamental frequency.
5. The circuit of claim 1 wherein the resonant circuit frequency response tracks the VCO output.
6. A communications device having a frequency synthesizer, said frequency synthesizer comprising:
a voltage controlled oscillator (VCO) for receiving a control signal and providing a frequency output in response thereto;
a multiplier circuit, coupled to the VCO for receiving the frequency output and providing a product signal in response thereto, said product signal having a fundamental frequency and a plurality of harmonic components;
a resonant circuit, coupled to the multiplier circuit, and having a variable reactance stage for receiving ,the control signal and altering a reactance of the variable reactance stage in response to control signal amplitude, to establish a response for the resonant circuit that tracks a response for desired harmonic within the product signal;
and an isolation circuit, coupled to the resonant circuit and the VCO, for receiving the control signal and feeding the control signal forward to the voltage variable reactance stage.
a voltage controlled oscillator (VCO) for receiving a control signal and providing a frequency output in response thereto;
a multiplier circuit, coupled to the VCO for receiving the frequency output and providing a product signal in response thereto, said product signal having a fundamental frequency and a plurality of harmonic components;
a resonant circuit, coupled to the multiplier circuit, and having a variable reactance stage for receiving ,the control signal and altering a reactance of the variable reactance stage in response to control signal amplitude, to establish a response for the resonant circuit that tracks a response for desired harmonic within the product signal;
and an isolation circuit, coupled to the resonant circuit and the VCO, for receiving the control signal and feeding the control signal forward to the voltage variable reactance stage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/835,372 US5903196A (en) | 1997-04-07 | 1997-04-07 | Self centering frequency multiplier |
| US08/835,372 | 1997-04-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2231636A1 CA2231636A1 (en) | 1998-10-07 |
| CA2231636C true CA2231636C (en) | 2000-10-24 |
Family
ID=25269350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002231636A Expired - Fee Related CA2231636C (en) | 1997-04-07 | 1998-03-10 | Self centering frequency multiplier |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US5903196A (en) |
| CA (1) | CA2231636C (en) |
| GB (1) | GB2324215B (en) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6150890A (en) * | 1998-03-19 | 2000-11-21 | Conexant Systems, Inc. | Dual band transmitter for a cellular phone comprising a PLL |
| US6243569B1 (en) | 1998-08-12 | 2001-06-05 | Analog Devices, Inc. | Direct conversion circuit for radio frequency signals |
| US6091940A (en) | 1998-10-21 | 2000-07-18 | Parkervision, Inc. | Method and system for frequency up-conversion |
| US6061551A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for down-converting electromagnetic signals |
| US7515896B1 (en) | 1998-10-21 | 2009-04-07 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same, and aperture relationships |
| US6694128B1 (en) | 1998-08-18 | 2004-02-17 | Parkervision, Inc. | Frequency synthesizer using universal frequency translation technology |
| US7039372B1 (en) | 1998-10-21 | 2006-05-02 | Parkervision, Inc. | Method and system for frequency up-conversion with modulation embodiments |
| US6049706A (en) | 1998-10-21 | 2000-04-11 | Parkervision, Inc. | Integrated frequency translation and selectivity |
| US6061555A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for ensuring reception of a communications signal |
| US6370371B1 (en) | 1998-10-21 | 2002-04-09 | Parkervision, Inc. | Applications of universal frequency translation |
| US6542722B1 (en) | 1998-10-21 | 2003-04-01 | Parkervision, Inc. | Method and system for frequency up-conversion with variety of transmitter configurations |
| US7236754B2 (en) | 1999-08-23 | 2007-06-26 | Parkervision, Inc. | Method and system for frequency up-conversion |
| US6560301B1 (en) | 1998-10-21 | 2003-05-06 | Parkervision, Inc. | Integrated frequency translation and selectivity with a variety of filter embodiments |
| US6813485B2 (en) | 1998-10-21 | 2004-11-02 | Parkervision, Inc. | Method and system for down-converting and up-converting an electromagnetic signal, and transforms for same |
| US6522868B1 (en) * | 1998-11-04 | 2003-02-18 | Lockheed Martin Corporation | Method and apparatus for generating a communication band signal with reduced phase noise |
| US6704549B1 (en) | 1999-03-03 | 2004-03-09 | Parkvision, Inc. | Multi-mode, multi-band communication system |
| US6704558B1 (en) | 1999-01-22 | 2004-03-09 | Parkervision, Inc. | Image-reject down-converter and embodiments thereof, such as the family radio service |
| US6879817B1 (en) | 1999-04-16 | 2005-04-12 | Parkervision, Inc. | DC offset, re-radiation, and I/Q solutions using universal frequency translation technology |
| US6853690B1 (en) | 1999-04-16 | 2005-02-08 | Parkervision, Inc. | Method, system and apparatus for balanced frequency up-conversion of a baseband signal and 4-phase receiver and transceiver embodiments |
| US6658216B1 (en) * | 1999-03-31 | 2003-12-02 | Matsushita Electric Industrial Co., Ltd. | Voltage controlled oscillator, FM signal optical transmitter, FM signal optical receiver and FM signal optical transmission system |
| US7110444B1 (en) | 1999-08-04 | 2006-09-19 | Parkervision, Inc. | Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments and circuit implementations |
| US7693230B2 (en) | 1999-04-16 | 2010-04-06 | Parkervision, Inc. | Apparatus and method of differential IQ frequency up-conversion |
| US7065162B1 (en) | 1999-04-16 | 2006-06-20 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same |
| US8295406B1 (en) | 1999-08-04 | 2012-10-23 | Parkervision, Inc. | Universal platform module for a plurality of communication protocols |
| US7010286B2 (en) | 2000-04-14 | 2006-03-07 | Parkervision, Inc. | Apparatus, system, and method for down-converting and up-converting electromagnetic signals |
| US7454453B2 (en) | 2000-11-14 | 2008-11-18 | Parkervision, Inc. | Methods, systems, and computer program products for parallel correlation and applications thereof |
| US6985702B2 (en) | 2001-02-23 | 2006-01-10 | Koninklijke Philips Electronics N.V. | Transceiver with frequency multiplier tracked to frequency generator |
| US7072427B2 (en) | 2001-11-09 | 2006-07-04 | Parkervision, Inc. | Method and apparatus for reducing DC offsets in a communication system |
| US6987424B1 (en) * | 2002-07-02 | 2006-01-17 | Silicon Laboratories Inc. | Narrow band clock multiplier unit |
| US7460584B2 (en) | 2002-07-18 | 2008-12-02 | Parkervision, Inc. | Networking methods and systems |
| US7379883B2 (en) | 2002-07-18 | 2008-05-27 | Parkervision, Inc. | Networking methods and systems |
| US7696797B1 (en) | 2005-03-31 | 2010-04-13 | Schnaitter William N | Signal generator with output frequency greater than the oscillator frequency |
| US7421252B2 (en) * | 2005-08-02 | 2008-09-02 | Freescale Semiconductor, Inc. | Center frequency control of an integrated phase rotator band-pass filter using VCO coarse trim bits |
| US7541849B2 (en) * | 2005-08-09 | 2009-06-02 | Seiko Epson Corporation | Phase locked circuit |
| US8655296B2 (en) * | 2007-12-18 | 2014-02-18 | Harris Corporation | Frequency synthesizer and related method for generating wideband signals |
| CN101931367B (en) * | 2010-10-12 | 2012-05-30 | 西安天伟电子系统工程有限公司 | 100MHz frequency tripler based on N-P-N triode |
| US10498346B2 (en) | 2017-11-09 | 2019-12-03 | Raytheon Company | Midband phase noise reducer for PLLS |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1015283A (en) * | 1961-10-02 | 1965-12-31 | Avco Corp | Frequency synthesizer for single sideband communications |
| US4433315A (en) * | 1981-11-24 | 1984-02-21 | General Electric Company | Tunable coupling network |
| JPS6359116A (en) * | 1986-08-28 | 1988-03-15 | Mitsubishi Electric Corp | Pll frequency synthesizer |
| US4888564A (en) * | 1987-11-06 | 1989-12-19 | Victor Company Of Japan, Ltd. | Phase-locked loop circuit |
| US5121015A (en) * | 1990-11-14 | 1992-06-09 | Zenith Electronics Corporation | Voltage controlled delay element |
| WO1994022224A1 (en) * | 1993-03-18 | 1994-09-29 | Kabushiki Kaisha Toshiba | Frequency synthesizer |
| US5438300A (en) * | 1994-04-01 | 1995-08-01 | National Semiconductor Corporation | Digital frequency multiplier utilizing digital controlled oscillator |
| GB2294599B (en) * | 1994-10-28 | 1999-04-14 | Marconi Instruments Ltd | A frequency synthesiser |
-
1997
- 1997-04-07 US US08/835,372 patent/US5903196A/en not_active Expired - Lifetime
-
1998
- 1998-03-10 CA CA002231636A patent/CA2231636C/en not_active Expired - Fee Related
- 1998-03-30 GB GB9806577A patent/GB2324215B/en not_active Expired - Fee Related
- 1998-11-12 US US09/190,789 patent/US5973570A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CA2231636A1 (en) | 1998-10-07 |
| US5903196A (en) | 1999-05-11 |
| US5973570A (en) | 1999-10-26 |
| GB2324215B (en) | 1999-06-16 |
| GB2324215A (en) | 1998-10-14 |
| GB9806577D0 (en) | 1998-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2231636C (en) | Self centering frequency multiplier | |
| US5146186A (en) | Programmable-step, high-resolution frequency synthesizer which substantially eliminates spurious frequencies without adversely affecting phase noise | |
| US5150078A (en) | Low noise fine frequency step synthesizer | |
| US5034703A (en) | Frequency synthesizer | |
| US4472685A (en) | Phase-locked loop frequency demodulator and frequency synthesizer | |
| US4882549A (en) | Center offset microwave frequency synthesizer | |
| US9793904B1 (en) | System and method of noise correcting PLL frequency synthesizers | |
| US4720688A (en) | Frequency synthesizer | |
| IL96670A (en) | Frequency agile microwave signal generator | |
| US4977613A (en) | Fine tuning frequency synthesizer with feedback loop for frequency control systems | |
| US4994762A (en) | Multiloop synthesizer with optimal spurious performance | |
| US4206421A (en) | Arrangement for synchronizing a free-swinging oscillator | |
| GB2250877A (en) | Shifting spurious frequencies away from signal frequency | |
| US6717484B2 (en) | Circuits for use in radio communications | |
| US6198354B1 (en) | System for limiting if variation in phase locked loops | |
| US7626464B2 (en) | Multi-frequency signal source | |
| RU2041564C1 (en) | S h f synthesizer | |
| JPH1013228A (en) | Phase-locked loop oscillation circuit | |
| JPH06224957A (en) | Radio transmitter | |
| JPH02224530A (en) | Tuner channel selection device | |
| Aupperle et al. | A precision-tuned receiver employing solid-state tuning elements | |
| JPH0730375A (en) | Aft circuit and electronic tuner using the same | |
| JPS6119236A (en) | Fm receiver | |
| KR19980054185U (en) | Tuner beat frequency prevention device | |
| JPH06125269A (en) | Variable frequency type high frequency oscillator circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20180312 |