CA2233115A1 - Semiconductor substrate and method of manufacturing the same - Google Patents

Semiconductor substrate and method of manufacturing the same

Info

Publication number
CA2233115A1
CA2233115A1 CA002233115A CA2233115A CA2233115A1 CA 2233115 A1 CA2233115 A1 CA 2233115A1 CA 002233115 A CA002233115 A CA 002233115A CA 2233115 A CA2233115 A CA 2233115A CA 2233115 A1 CA2233115 A1 CA 2233115A1
Authority
CA
Canada
Prior art keywords
layer
manufacturing
porous
same
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002233115A
Other languages
French (fr)
Other versions
CA2233115C (en
Inventor
Nobuhiko Sato
Takao Yonehara
Kiyofumi Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of CA2233115A1 publication Critical patent/CA2233115A1/en
Application granted granted Critical
Publication of CA2233115C publication Critical patent/CA2233115C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/06Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/08Preparation of the foundation plate

Abstract

To provide a manufacturing method excellent in controllability, productivity and economics of a high-quality SOI wafer, and a wafer manufactured by that method, in the wafer manufactured by bonding, after bonding, separation is made on an interface of a high porosity layer in a porous region including a low porosity layer and the high porosity layer in a surface formed on a main surface side of a first Si substrate 2 to transfer a non-porous layer onto a second substrate.
After separation at the high porosity layer, a residual low porosity thin layer is made non-porous by a smoothing process such as hydrogen annealing without using selective etching.
CA002233115A 1997-03-27 1998-03-25 Semiconductor substrate and method of manufacturing the same Expired - Fee Related CA2233115C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7554597 1997-03-27
JP9-075545 1997-03-27

Publications (2)

Publication Number Publication Date
CA2233115A1 true CA2233115A1 (en) 1998-09-27
CA2233115C CA2233115C (en) 2002-03-12

Family

ID=13579288

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002233115A Expired - Fee Related CA2233115C (en) 1997-03-27 1998-03-25 Semiconductor substrate and method of manufacturing the same

Country Status (8)

Country Link
US (1) US6143628A (en)
EP (1) EP0867922A3 (en)
KR (1) KR100260832B1 (en)
CN (1) CN1118085C (en)
AU (1) AU728331B2 (en)
CA (1) CA2233115C (en)
SG (1) SG68658A1 (en)
TW (1) TW404061B (en)

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Also Published As

Publication number Publication date
CN1118085C (en) 2003-08-13
AU5969998A (en) 1998-10-01
US6143628A (en) 2000-11-07
CN1199920A (en) 1998-11-25
EP0867922A2 (en) 1998-09-30
EP0867922A3 (en) 1999-03-17
KR100260832B1 (en) 2000-07-01
SG68658A1 (en) 1999-11-16
KR19980080778A (en) 1998-11-25
AU728331B2 (en) 2001-01-04
TW404061B (en) 2000-09-01
CA2233115C (en) 2002-03-12

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