CA2233831A1 - Digital-sigma fractional-n synthesizer - Google Patents
Digital-sigma fractional-n synthesizer Download PDFInfo
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- CA2233831A1 CA2233831A1 CA002233831A CA2233831A CA2233831A1 CA 2233831 A1 CA2233831 A1 CA 2233831A1 CA 002233831 A CA002233831 A CA 002233831A CA 2233831 A CA2233831 A CA 2233831A CA 2233831 A1 CA2233831 A1 CA 2233831A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3006—Compensating for, or preventing of, undesired influence of physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M7/3026—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
Abstract
A Delta-Sigma modulator includes a dead-zone quantizer and an error shaping digital filter clocked by a signal which is periodic at the frequency of the reference. A dead-zone quantizer provides quantization of a high resolution digital word to a low resolution digital word with three or a higher odd number of possible output levels and with an output of zero for an input near the centre of the normal input range.
Description
Delta-Sigma Fractional-N Synthesizer FIELD OF THE INVENTION loop Filter F(s) provides the signal s2 such that This invention relates to frequency the overall loop forms a stable synthesizers of the type in which a multimodulus Phase-Locked-Loop (PLL).
frequency divider is controlled by a Delta-Sigma The output frequency, fo, of such a synthesizer modulator. depends on the reference frequency, f , and the DESCRIPTION OF RELATED ART desired division ratio, N:
Fractional-N single-loop PLL synthesizers are fo = N f a well known technique for generating one In Delta-Sigma controlled synthesizers, the frequency from a range of predetermined desirable value of N can take on fractional values.
frequencies. Typically this is performed for the Typically, this is provided by a programable purpose of transmitting or receiving a radio signal divider 22, responsive to some programmed base over one chanel of many allocated to a particular value, n, and the output, b, , of a Delta-Sigma wireless service. modulator 21. A summing means 23 provides The structure of many Delta-Sigma control signal(s), c, such that the divider divides Fractional-N single-loop PLL synthesizers is by prededermined ratios n, n+l, n+2, ... n+k;
shown in Fig. 1. A VCO (Voltage Controlled where k is some predetermined integer which Oscillator) 10 provides an output signal, f , depends on the particular Delta-Sigma modulator oscillating with a frequency responsive to a used. Various other means, known to those versed control signal s2. A Fractional-N divider 20 in the art, may be provided such that the provides the signal fd such that the frequency of Delta-Sigma modulator selects one of the fd is the frequency of f divided by some desired predetermined division ratios for each cycle of the division ratio, N. A phase detector provides a divider.
signal, s 1, such that the signal, s 1, is proportional Thus, if the Delta-Sigma modulator has a to phase and/or frequency difference between fd fixed-point binary input, b~,e, integer output b~ for and an external frequency reference signal, f . A each cycle, i, of the divider, there is some time-average value for this output,In each of these three examples, bQVe, such that the stages are b; = b~,e + Q; where bQVe is the Delta-Sigma modulators desired, fractional, average output and Q; is the quantizationAlthough all Delta-Sigma modulators error for have the each cycle of the divider. Since same functional definition, some b~e is a long term Delta-Sigma average of many integers, it can modulators perform better than have a fractional others in the value and fractional-N division ability to randomize and noise can be achieved. shape the In the short term, there is often quantization error.
an non-zero quantization error. A Delta-Sigma Some specific limitations are:
modulator is defined herein by the ability to ' With a do input, any digital shape the spectral Delta-Sigma density of this quantization error.modulator becomes a finite state The noise machine. A
shaping provided by a Delta-Sigma Delta-Sigma modulator which has modulator is a longer such that the quantization error sequence length (which in turn is reduced at and produces more near to: spurs) will generally have less power in each ' dc, individual spur. The power in each of these ' the reference frequency, f , and spurs can presently limit the performance of a all multiples the reference frequency,Delta-Sigma modulator based fractional-N
f .
This error shaping allows the quantizationsynthesizer, especially when it is desireable to error to be substantially removed reduce the number of bits in the by the low pass Delta-Sigma filtering of the closed-loop PLL. modulator. This creates difficulty in designing Several fractional-N synthesizers low power synthesizers with low spurs.
incorporating Delta-Sigma modulators' Another factor which limits the have each performance of been disclosed separately for example:Delta-Sigma modulator based fractional-N
US Patent 4,609,881 (Wells-86 ) synthesizers is high frequency discloses a spurs outside the Delta-Sigma modulator based on a loop bandwidth of the PLL synthesiser.
cascade of first When order stages. these spurs are substatially larger than those US Patent 5,055,802 (Hietala-91 produced by sequence length limits, ) discloses any another Delta-Sigma modulator basednonlinearity equivalent to a phase on a detector cascade of first order stages. nonlinearity can mix these spurs to new US Patent 5,079,521 (Gasket-92) frequencies within the bandwidth discloses a of the PLL.
similar arrangement of second and/orThese cannot be filtered out by first order the loop filter.
stages.
frequency divider is controlled by a Delta-Sigma The output frequency, fo, of such a synthesizer modulator. depends on the reference frequency, f , and the DESCRIPTION OF RELATED ART desired division ratio, N:
Fractional-N single-loop PLL synthesizers are fo = N f a well known technique for generating one In Delta-Sigma controlled synthesizers, the frequency from a range of predetermined desirable value of N can take on fractional values.
frequencies. Typically this is performed for the Typically, this is provided by a programable purpose of transmitting or receiving a radio signal divider 22, responsive to some programmed base over one chanel of many allocated to a particular value, n, and the output, b, , of a Delta-Sigma wireless service. modulator 21. A summing means 23 provides The structure of many Delta-Sigma control signal(s), c, such that the divider divides Fractional-N single-loop PLL synthesizers is by prededermined ratios n, n+l, n+2, ... n+k;
shown in Fig. 1. A VCO (Voltage Controlled where k is some predetermined integer which Oscillator) 10 provides an output signal, f , depends on the particular Delta-Sigma modulator oscillating with a frequency responsive to a used. Various other means, known to those versed control signal s2. A Fractional-N divider 20 in the art, may be provided such that the provides the signal fd such that the frequency of Delta-Sigma modulator selects one of the fd is the frequency of f divided by some desired predetermined division ratios for each cycle of the division ratio, N. A phase detector provides a divider.
signal, s 1, such that the signal, s 1, is proportional Thus, if the Delta-Sigma modulator has a to phase and/or frequency difference between fd fixed-point binary input, b~,e, integer output b~ for and an external frequency reference signal, f . A each cycle, i, of the divider, there is some time-average value for this output,In each of these three examples, bQVe, such that the stages are b; = b~,e + Q; where bQVe is the Delta-Sigma modulators desired, fractional, average output and Q; is the quantizationAlthough all Delta-Sigma modulators error for have the each cycle of the divider. Since same functional definition, some b~e is a long term Delta-Sigma average of many integers, it can modulators perform better than have a fractional others in the value and fractional-N division ability to randomize and noise can be achieved. shape the In the short term, there is often quantization error.
an non-zero quantization error. A Delta-Sigma Some specific limitations are:
modulator is defined herein by the ability to ' With a do input, any digital shape the spectral Delta-Sigma density of this quantization error.modulator becomes a finite state The noise machine. A
shaping provided by a Delta-Sigma Delta-Sigma modulator which has modulator is a longer such that the quantization error sequence length (which in turn is reduced at and produces more near to: spurs) will generally have less power in each ' dc, individual spur. The power in each of these ' the reference frequency, f , and spurs can presently limit the performance of a all multiples the reference frequency,Delta-Sigma modulator based fractional-N
f .
This error shaping allows the quantizationsynthesizer, especially when it is desireable to error to be substantially removed reduce the number of bits in the by the low pass Delta-Sigma filtering of the closed-loop PLL. modulator. This creates difficulty in designing Several fractional-N synthesizers low power synthesizers with low spurs.
incorporating Delta-Sigma modulators' Another factor which limits the have each performance of been disclosed separately for example:Delta-Sigma modulator based fractional-N
US Patent 4,609,881 (Wells-86 ) synthesizers is high frequency discloses a spurs outside the Delta-Sigma modulator based on a loop bandwidth of the PLL synthesiser.
cascade of first When order stages. these spurs are substatially larger than those US Patent 5,055,802 (Hietala-91 produced by sequence length limits, ) discloses any another Delta-Sigma modulator basednonlinearity equivalent to a phase on a detector cascade of first order stages. nonlinearity can mix these spurs to new US Patent 5,079,521 (Gasket-92) frequencies within the bandwidth discloses a of the PLL.
similar arrangement of second and/orThese cannot be filtered out by first order the loop filter.
stages.
' Further, different Delta-Sigma Fig. 3 illustrates a single loop modulators feedback involve different amounts of digitalDelta-Sigma modulator with an error hardwalve. In shaping an LSI implementation, this hardwarefilter according to an optional consumes aspect of the silicon area and power, both of invention.
which are disadvantageous for low cost portableFig. 4 illustrates a an example single loop equipment. feedback second order Delta-Sigma modulator SUMMARY OF THE INVENTION according to an optional aspect of the invention.
The object of the present inventionFig. 5 illustrates a Fractional-N
is to divider with provide and employ a Delta-Sigma contiguous tuning across integer-N
modulator boundaries with increased sequence-length or according to the invention.
reduced out of band spurs. Fig. 6 illustrates a higher order Delta-Sigma The object of a optional aspect modulator according to the invention.
of the invention is, to employ an error DESCRIPTION OF THE PREFERRED
shaping filter with reduced hardware and regular layoutEMBODIMENTS
when implemented in an LSI circuit. Figure 2 illustrates a Delta-Sigma modulator These objects are realized through comprising a dead-zone quantizer the 210 and a error fractional-N synthesizer of the present invention shaping digital filter 211 clocked by a signal, clk, wherein the digital network controling the divider which is periodic at the frequency of the includes a Delta-Sigma modulator including a reference. A dead-zone quantizer provides dead-zone quantizer, and (optionallly)quantization of a high resolution a digital word, q,, Delta-Sigma modulator including to a low resolution digital word, a look-up-table b;, with 3 or a feedback filter. higher odd number of possible output levels and BRIEF DESCRIPTION OF THE DRAWINGS with an output of 0 for an input near the center of Fig.l illustrates in block diagram the normal input range. (This provides form, the different general architecture of a single-loopquantization error than a sficer Delta-Sigma or single bit Fractional-N Synthesizer. quantizer). Table 1 below illustrates the input and Fig. 2 illustrates in block diagramoutput values for a quantizer with form, the two's general form of a Delta-Sigma modulatorcompliment binary encoding of the numerical employing a dead-zone quantizer values. In this example the output according to the values are -1, 0 invention. and +1.
which are disadvantageous for low cost portableFig. 4 illustrates a an example single loop equipment. feedback second order Delta-Sigma modulator SUMMARY OF THE INVENTION according to an optional aspect of the invention.
The object of the present inventionFig. 5 illustrates a Fractional-N
is to divider with provide and employ a Delta-Sigma contiguous tuning across integer-N
modulator boundaries with increased sequence-length or according to the invention.
reduced out of band spurs. Fig. 6 illustrates a higher order Delta-Sigma The object of a optional aspect modulator according to the invention.
of the invention is, to employ an error DESCRIPTION OF THE PREFERRED
shaping filter with reduced hardware and regular layoutEMBODIMENTS
when implemented in an LSI circuit. Figure 2 illustrates a Delta-Sigma modulator These objects are realized through comprising a dead-zone quantizer the 210 and a error fractional-N synthesizer of the present invention shaping digital filter 211 clocked by a signal, clk, wherein the digital network controling the divider which is periodic at the frequency of the includes a Delta-Sigma modulator including a reference. A dead-zone quantizer provides dead-zone quantizer, and (optionallly)quantization of a high resolution a digital word, q,, Delta-Sigma modulator including to a low resolution digital word, a look-up-table b;, with 3 or a feedback filter. higher odd number of possible output levels and BRIEF DESCRIPTION OF THE DRAWINGS with an output of 0 for an input near the center of Fig.l illustrates in block diagram the normal input range. (This provides form, the different general architecture of a single-loopquantization error than a sficer Delta-Sigma or single bit Fractional-N Synthesizer. quantizer). Table 1 below illustrates the input and Fig. 2 illustrates in block diagramoutput values for a quantizer with form, the two's general form of a Delta-Sigma modulatorcompliment binary encoding of the numerical employing a dead-zone quantizer values. In this example the output according to the values are -1, 0 invention. and +1.
Table 1: Dead-Zone Quantizer responsive to both the input signal b~.e and the Quantizer Input Value Output quantizer output value b; such that the overall Value Delta-Sigma modulator provides:
Ol lxxxxxxxxx O1 ~ a low pass or substantially all pass filter from b~e to b;, and OlOxxxxxxxxx O1 l d it ' th f lt t d th t f th ra a noc i er o re uce e spec ens y o e 001 xxxxxxxxx O 1 qu~tization error at do and multiples of the OOOxxxxxxxxx 00 clock frequency.
111 xxxxxxxxx 00 As with single bit quantizers or multibit 1 l Oxxxxxxxxx 1 O qu~tizers, described in the prior art, the error shaping filter must provide negative feedback and lOlxxxxxxxxx 10 t bl db k l t l th f i i e ee ac an s a oop o contro e quant zat on 100xxxxxxxxx 10 error.
Bit positions marked with an x in the above One such error shaping digital filter is table are don't cares and hence the output value is illustrated in the example Delta-Sigma modulator a logic function of the three MSBs of the input of Fig. 3. This error shaping filter comprises value. Extra MSB's may be added as necessary by feed-back filter means, G1(z), 212 responsive to sign extending the Quantizer input value to the Delta-Sigma modulator output, b; , to provide provide sufficient dynamic range for the variations a loop stabilizing signal, b;Z , differenceing means in siganal magnitude in each of the accumulators 213 to provide a signal, e; , proportional to the (or resonators) prior to the quantizer. difference between b;Z and bQVe , and a second filter A error shaping digital filter 211 clocked at means, G2(z), 214 with substantial gain at or near the frequency of the reference, f , provides do and multiples of the reference frequency to spectral shaping of the quantization error provide the quantizer input value for the introduced by the dead-zone quantizer and a stable dead-zone quantizer.
Delta-Sigma modulator. Many stable Delta-Sigma To further clarify without reducing generality, modulators have been presented in the literature one particular example illustrated in figureXX
and are know to those versed in the art. teaches, according to an optional aspect of the Delta-Sigma data converters: theory design and invention, the feedback network G 1 (z) provides a simulation (Norsworthy et al.) is included herein Stabalizing-Zero transfer function. The by reference. The error shaping digital filter is Stabalizing-Zero transfer function is -[(1-z')P-1]K ' a lookup table to store and provide precomputed where: differences, e; , selected by the feedback function ' P is the order of the Delta-Sigma modulator and G 1 (z) and the Delta-Sigma modulator input b~.e, the number of accumulators in the feed-forward path, and ' a first accumulator comprising a digital adder ' K is 2 raised to the power of an integer number. 214a and register 214c providing an Alternatively, G1(z) may be a constant, with accumulated output, al.
the stabalizing zeros included in the feed-forward ' a second accumulator comprising a digital adder filter. 214b and register 214d providing the input to Typically, G2(z) is an all pole filter with poles the dead-zone quantizer, at dc. In this case, the feed forward filter is such that the transfer function is of the filter is provided by two or more accululators. To position -[(1-z')Z-1]K where K is as previously defined quantization error noise notches at other and z' is the delay operator.
frequencies, the feed forward filter could include a It will be clear to those versed in the art of series of resonators and/or accumulators to move digital electronics, that the resolution of the the poles of G2(z) to frequencies higher than dc. Delta-Sigma modulatorcan be increased The simplest embodiment the invention (decreased) by one or more bits by increasing provides a a feedback filter of this type, with (decreasing) the bus widths of the input and the coefficients that are all even powers of two. The accumulators in the feed forward path 214.
error shaping filter, 21 lb, of Fig. 4 teaches by It will be clear to those versed in the art of example an optional aspect of the invention which digital electronics, that other forms of digital logic is the employment of the error shaping filter 211 could replace the lookup table with equvalent which has a regular layout and minimal hardware functionality. In general, the minimal hardware when implemented in an LSI circuit. The filter and regular layout are provided by the single loop comprises: feed-back and power of two scaling factors in the ' a first storage register 212a to stare previous feed-back filter.
value of the quantizer output, b; , and provide a For higher order Delta-Sigma modulators, the delayed version of the output ,b~' , two integrators of Fig. 4 can be generalized to two ' a second storage register 212b to store , b;', and or more integrators and the two delays of the provide a twice delayed version of the quantizer output, b; , can be generalized to two or more output, b; ", delays.
Ol lxxxxxxxxx O1 ~ a low pass or substantially all pass filter from b~e to b;, and OlOxxxxxxxxx O1 l d it ' th f lt t d th t f th ra a noc i er o re uce e spec ens y o e 001 xxxxxxxxx O 1 qu~tization error at do and multiples of the OOOxxxxxxxxx 00 clock frequency.
111 xxxxxxxxx 00 As with single bit quantizers or multibit 1 l Oxxxxxxxxx 1 O qu~tizers, described in the prior art, the error shaping filter must provide negative feedback and lOlxxxxxxxxx 10 t bl db k l t l th f i i e ee ac an s a oop o contro e quant zat on 100xxxxxxxxx 10 error.
Bit positions marked with an x in the above One such error shaping digital filter is table are don't cares and hence the output value is illustrated in the example Delta-Sigma modulator a logic function of the three MSBs of the input of Fig. 3. This error shaping filter comprises value. Extra MSB's may be added as necessary by feed-back filter means, G1(z), 212 responsive to sign extending the Quantizer input value to the Delta-Sigma modulator output, b; , to provide provide sufficient dynamic range for the variations a loop stabilizing signal, b;Z , differenceing means in siganal magnitude in each of the accumulators 213 to provide a signal, e; , proportional to the (or resonators) prior to the quantizer. difference between b;Z and bQVe , and a second filter A error shaping digital filter 211 clocked at means, G2(z), 214 with substantial gain at or near the frequency of the reference, f , provides do and multiples of the reference frequency to spectral shaping of the quantization error provide the quantizer input value for the introduced by the dead-zone quantizer and a stable dead-zone quantizer.
Delta-Sigma modulator. Many stable Delta-Sigma To further clarify without reducing generality, modulators have been presented in the literature one particular example illustrated in figureXX
and are know to those versed in the art. teaches, according to an optional aspect of the Delta-Sigma data converters: theory design and invention, the feedback network G 1 (z) provides a simulation (Norsworthy et al.) is included herein Stabalizing-Zero transfer function. The by reference. The error shaping digital filter is Stabalizing-Zero transfer function is -[(1-z')P-1]K ' a lookup table to store and provide precomputed where: differences, e; , selected by the feedback function ' P is the order of the Delta-Sigma modulator and G 1 (z) and the Delta-Sigma modulator input b~.e, the number of accumulators in the feed-forward path, and ' a first accumulator comprising a digital adder ' K is 2 raised to the power of an integer number. 214a and register 214c providing an Alternatively, G1(z) may be a constant, with accumulated output, al.
the stabalizing zeros included in the feed-forward ' a second accumulator comprising a digital adder filter. 214b and register 214d providing the input to Typically, G2(z) is an all pole filter with poles the dead-zone quantizer, at dc. In this case, the feed forward filter is such that the transfer function is of the filter is provided by two or more accululators. To position -[(1-z')Z-1]K where K is as previously defined quantization error noise notches at other and z' is the delay operator.
frequencies, the feed forward filter could include a It will be clear to those versed in the art of series of resonators and/or accumulators to move digital electronics, that the resolution of the the poles of G2(z) to frequencies higher than dc. Delta-Sigma modulatorcan be increased The simplest embodiment the invention (decreased) by one or more bits by increasing provides a a feedback filter of this type, with (decreasing) the bus widths of the input and the coefficients that are all even powers of two. The accumulators in the feed forward path 214.
error shaping filter, 21 lb, of Fig. 4 teaches by It will be clear to those versed in the art of example an optional aspect of the invention which digital electronics, that other forms of digital logic is the employment of the error shaping filter 211 could replace the lookup table with equvalent which has a regular layout and minimal hardware functionality. In general, the minimal hardware when implemented in an LSI circuit. The filter and regular layout are provided by the single loop comprises: feed-back and power of two scaling factors in the ' a first storage register 212a to stare previous feed-back filter.
value of the quantizer output, b; , and provide a For higher order Delta-Sigma modulators, the delayed version of the output ,b~' , two integrators of Fig. 4 can be generalized to two ' a second storage register 212b to store , b;', and or more integrators and the two delays of the provide a twice delayed version of the quantizer output, b; , can be generalized to two or more output, b; ", delays.
In some cases it may be desireable to use the component of c to vary over a range from -0.5 to output b;' rather than b; as the Delta-Sigma +0.5.
modulator output. The output b; providdes a Figure 6 illustrates a method for compensating delayed and resynchronized output. b;' can be residual error of the dead-zone quantizer which is regarded as equivalent to b; once this delay is not completely removed by the error shaping taken into account. filter.
Figure 5 teaches by example a method for The method comprises:
obtaining contiguous tuning without' a residual error detection means, having 221, which excessively large values in the provides an error signal, r, corresponding accumulators. .A to the filter, 24, responsive to the Delta-Sigmaerror introduced by the dead-zone output, b;, quantizer, provides an output signal, c', which210, controls the divide ratio of the divider. The ' a Delta-Sigma modulation means filter provides a responsive to fixed do gain, Kfrter, greater thanthe error signal, r, and a clock 1. This gain is signal, clk, which provided such that: provides a second low resolution signal, b2, a fractional do input to the Delta-Sigmasuch that b2 represents the error signal, r, and modulator, bane, which varies over the quantization error introduced a range from by the ba"e= a to ba"e= a + llKfrre. , Delta-Sigma modulation means is reduced at or provides a coresponding fractional near do and all multiples of the do frequency of the component of the filter output, clock signal, clk, c', which varies over a range from aKfr~e, to aKrrte.' a filter means responsive to low + 1. resolution Optionally changing the integer signal b2 and clock signal, clk, component , n, providing signal then provides a frequency synthesizerfiltered low resolution signal, tuning b3, such that the range which can be contiguously transfer function providing b3 from tuned accross b2 is integer-n boundaries. (1-z')2.
In the example of Figure 5, a filter,a combining means, 224, responsive 24, which to filtered adds the present output of the Delta-Sigma low resolution signal, b3, and first Delta-Sigma modulator to the previous output of the modulator output b,, Delta-Sigma modulator provides a do gain of two.
As a result, varying the do component of b; over a range from -0.25 to +0.25 causes the do
modulator output. The output b; providdes a Figure 6 illustrates a method for compensating delayed and resynchronized output. b;' can be residual error of the dead-zone quantizer which is regarded as equivalent to b; once this delay is not completely removed by the error shaping taken into account. filter.
Figure 5 teaches by example a method for The method comprises:
obtaining contiguous tuning without' a residual error detection means, having 221, which excessively large values in the provides an error signal, r, corresponding accumulators. .A to the filter, 24, responsive to the Delta-Sigmaerror introduced by the dead-zone output, b;, quantizer, provides an output signal, c', which210, controls the divide ratio of the divider. The ' a Delta-Sigma modulation means filter provides a responsive to fixed do gain, Kfrter, greater thanthe error signal, r, and a clock 1. This gain is signal, clk, which provided such that: provides a second low resolution signal, b2, a fractional do input to the Delta-Sigmasuch that b2 represents the error signal, r, and modulator, bane, which varies over the quantization error introduced a range from by the ba"e= a to ba"e= a + llKfrre. , Delta-Sigma modulation means is reduced at or provides a coresponding fractional near do and all multiples of the do frequency of the component of the filter output, clock signal, clk, c', which varies over a range from aKfr~e, to aKrrte.' a filter means responsive to low + 1. resolution Optionally changing the integer signal b2 and clock signal, clk, component , n, providing signal then provides a frequency synthesizerfiltered low resolution signal, tuning b3, such that the range which can be contiguously transfer function providing b3 from tuned accross b2 is integer-n boundaries. (1-z')2.
In the example of Figure 5, a filter,a combining means, 224, responsive 24, which to filtered adds the present output of the Delta-Sigma low resolution signal, b3, and first Delta-Sigma modulator to the previous output of the modulator output b,, Delta-Sigma modulator provides a do gain of two.
As a result, varying the do component of b; over a range from -0.25 to +0.25 causes the do
Claims (8)
1. A Delta-Sigma modulator for use in a digital to analog converter, the Delta-Sigma modulator comprising:
an error shaping filter; and a dead zone quantizer, where the output of the dead zone quantizer is fed back to the error shaping filter.
an error shaping filter; and a dead zone quantizer, where the output of the dead zone quantizer is fed back to the error shaping filter.
2. A Delta-Sigma modulator as defined in claim 1, for use in a Delta-Sigma fractional N
synthesizer.
synthesizer.
3. A Delta-Sigma modulator as defined in claim 2, for use in a Delta-Sigma fractional N
phase locked loop synthesizer.
phase locked loop synthesizer.
4. A Delta-Sigma modulator as defined in claim 3, comprising:
an error shaping filter for receiving a clock signal, an input signal for controlling the output of the Delta-Sigma modulator, and a quantizer output value, and for providing an output; and a dead zone quantizer for receiving the output from the error shaping filter, and for providing a quantizer output value for feedback to the error shaping filter and for output.
an error shaping filter for receiving a clock signal, an input signal for controlling the output of the Delta-Sigma modulator, and a quantizer output value, and for providing an output; and a dead zone quantizer for receiving the output from the error shaping filter, and for providing a quantizer output value for feedback to the error shaping filter and for output.
5. A Delta-Sigma modulator as defined in claim 4, wherein the clock signal has a frequency equal to a reference frequency.
6. A Delta-Sigma modulator as defined in claim 5, wherein the clock signal is derived from the reference frequency.
7. A Delta-Sigma modulator as defined in claim 5, wherein the clock signal is derived from a divider output signal phase locked to the reference.
8. A Delta-Sigma modulator as defined in claim 1, wherein the filter is an error shaping digital filter.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002233831A CA2233831A1 (en) | 1998-03-31 | 1998-03-31 | Digital-sigma fractional-n synthesizer |
| CA 2267496 CA2267496C (en) | 1998-03-31 | 1999-03-30 | A fractional-n divider using a delta-sigma modulator |
| US09/281,854 US6236703B1 (en) | 1998-03-31 | 1999-03-31 | Fractional-N divider using a delta-sigma modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002233831A CA2233831A1 (en) | 1998-03-31 | 1998-03-31 | Digital-sigma fractional-n synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2233831A1 true CA2233831A1 (en) | 1999-09-30 |
Family
ID=4162281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002233831A Abandoned CA2233831A1 (en) | 1998-03-31 | 1998-03-31 | Digital-sigma fractional-n synthesizer |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6236703B1 (en) |
| CA (1) | CA2233831A1 (en) |
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| EP1254517B2 (en) † | 1999-12-14 | 2009-02-11 | Broadcom Corporation | Frequency division/multiplication with jitter minimization |
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-
1998
- 1998-03-31 CA CA002233831A patent/CA2233831A1/en not_active Abandoned
-
1999
- 1999-03-31 US US09/281,854 patent/US6236703B1/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1254517B2 (en) † | 1999-12-14 | 2009-02-11 | Broadcom Corporation | Frequency division/multiplication with jitter minimization |
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| Publication number | Publication date |
|---|---|
| US6236703B1 (en) | 2001-05-22 |
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