CA2239186A1 - Process for the prototyping of mixed signal applications and field programmable system on a chip for applying said process - Google Patents
Process for the prototyping of mixed signal applications and field programmable system on a chip for applying said process Download PDFInfo
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- CA2239186A1 CA2239186A1 CA002239186A CA2239186A CA2239186A1 CA 2239186 A1 CA2239186 A1 CA 2239186A1 CA 002239186 A CA002239186 A CA 002239186A CA 2239186 A CA2239186 A CA 2239186A CA 2239186 A1 CA2239186 A1 CA 2239186A1
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- digital
- cells
- associated hardware
- prototyping
- microprocessor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
Process for the prototyping of mixed signal applications and field programmable system on a chip for the application of said process, to be used independently in relation to a associated hardware in order to enable the user to specify, simulate, emulate and project a complete design and its prototyping,said function being integrated in a unique design setting, said process also comprising the schematic capture and simulation of mixed signals, the reading and writing of the configuration, the examination in real time of any point within the digital blocks or the analog subsystems which are part of said associated hardware, the change of data in real time within some programmable digital cells of said associated hardware, the configuration and reconfiguration of saidprogrammable digital cells, the interaction with the associated hardware, the execution of general purpose user programs, the storage of configuration context throughout the circuit with a microprocessor control and the delivery ofdata to an application specific integrated circuit (ASIC) using an ASIC library,The system comprises a microprocessor (2), at least one digital macro cell (3), a RAM memory (1), some analog cells (4) and interfaces (5,6,7,8) for the conection of said cells.
Description
JUL. 16. 1998 12:~4PM
CA 02239186 1998-0~-29 NO. 6~87 P. ~
PROCESS FOR THE PROTOlYPING OF l~lIXED SIGI~IAL APPLICATIONS
AN~ FIELD PROGRAMMABLE SYSTEM C~N A Cl IIP FOR THE
APPLICATION OF SA1D PROCESS.
5 ~e~ri~ion Object of the in-~ention The object of the present inventicn consists of a process for the 10 prototyping of mixed signal applications 0nd a field pro~rammable system on a chip for the applioati~n of said process, independently usable and adaptable to different analo~ue and/or di~ital hard~vare applications and capable to provide a direct interfac~ between hardware and sofl~are. This process shows important advantages o~er the systems currently used for this purpose.
There is a big nunlber of applications based on dynamic reconfiguration that could be identified and implemented with the digital hardware system of thepresent invention. These include communication s~itches, parallel processing applications as irna~e processing, array-based applicationsl etc.
E~ackground of the invention As t~e complexity of electronic systems grows, it becomes more di~ficult to follow a traditional desi~n methodolo~y of workin~ separately on different 25 subsystems with different design and prototyping tools, System designers havebeen searching for flexibl~ prototypin~ systems onto which they could map lar~e desi~ns to validate them bef~re manufacture, but only microprocessor ern~Jlators and digital conftgurable arrays have been available in the past. As a consequence of this need, analo~ue pro~rammable arrays have appeared 30 recently, confirming the interest that the industry sho~s for field-programm~ble devices suitable for fast prototypin~ for n~arket applicqtions.
Currently mixed-si~nal applications are typically s~lved in three domains:
di~ital hardware, analogue hard~are, and microprocessor pro~ram~ It is normal 35 for a rnedi~m complexity rnix~d ~ignal integrat~d circuit ~o include a JUL. 1~. 1998 12.2~P~ CA 02239186 1998-0~-29 NO. 6887 P 5 microprocessor core to run a user program, some ~igital hardware for control purposes and an analo~ue subsyste~ for data acquisition or analo3ue applications. In such cass, the typical designer normally follows a discrete methodolo~y an assembier compiler-debu~ger for the microprocessor program, a desi~n ent~ tool ~either schematic capture or HDL) and a digital simulator forthe digital hard~are, and an analo~ue sirnulator for the analogue su~system.
The main problem for users of this methodology is that the design is conceived and desi~n~d separately and it turns out to be difficult to control the interfaces between these three domains. The situation is also not very promisin~ about 10 prototyping: the best solution normally i5 to use a field programmable ~ate array (~PGA) for the digital hardware, some cliscrete Integrated Circuits or, recently, an analo~ue array for the analo~ue hardware, and a microprocessor entulator for the user program. Again, a completely different developrnent system has to be used for each part, and special care has ~o be taken when desi~nins the 15 different interfaces.
With the purpose to preYent the deficiencies presented by the processes for prototyping mixed si~nal applications currently in the market, it has been deveioped a ne~v process for prototyping mixed si~nal applications and field 20 pro~rammable systen~ on a chip for the application of said process, the object of the p~esent invention.
Descriptlon of the Invention In this context it is introd~Jced the process for prototypin~ mixed sl~nal applications and field pro~ramnlable system on a chip for the application of this process, the aim of the current invention, that is a new concept for system prototypin3 and programmable hardware. This system consists of a mixed-si~nal field prosramn~able device (FPD) with a standard microprocessor corel a suitable set of Computer Aided Design tools (CAD tools) to easily program it, and a set of library macros and cells ~Ivhich support a number of typical applications ~o be easily mapped onto the Field Pro~rammable Gate Array and migrsted to an ASIC ~fte~ards, if req~ired.
In particular the field progla~ ,able system on chip for the application of JUL. ~6. ~998 12 ~P~
CA 02239186 1998-0~-29 NO. 6887 P. 6 the process for the prototyping o~ mixed si~nal applio~tions includes, preferably, a microprocessor block, integrated storage media for writing and readin~ as, pr~ferably, a ~AM memory, at least one di~ital programm~ble macro cell, analogue cel1s and connection interfaces of the di~ital and analogue5 cells.
~ he interaction between each of the three domains ~di0ital hardware, analogue hardware and microprocessor programs) is as close as it can be; the microprocessor can read and ~rite the confi~uration of the analo~ue and digital 10 hard~are ~an physically inte~ce ports and the entire n~icroprocessor bus can be connscted to the routing channels of the Field Programmable Gate Array (FPGA), can examine in real time, any point within the digital blocks or analog subsystems, and can also chan3e data in real time within the flip-flops housed insi~e digital prosrammable cells WhiCh fornl on chip the field pro~rammable 15 systBm~ The microprocessor is then used to configurzte (and reconfigurate~ the programmabls cells, to interact with the actual hardware mapped onto ~hem and to run general purpose user programs.
The invention concept relies upon the fuily integrated desi~n and 20 pro~otypin~ methodology that the ~ser can follow with such a system. ~ powerful set of user-friendly CAD tools is provided, with the final target of letting the user spectfy, simulate, emulate (probe) and map the complete design on a sin~le chip usin~ one desi~n enYironment. ~his includes mixed-signal schematic capture and simulation, automatic techno10gy n apping, placement and routing 25 tools, an integrated emulation software (which allows step by step pro~ram execution and real time internal signal checking), ~nd an in~eQrsted device p~ogrammin~ package.
A lar~e ~et of library macros provides op~imised solutions to typical 30 design needs, allo~Ning the user to inlplement his own macros zt any desi~n level, frorn HDL to any manual placemsnt and routing. A parallel ASIC library is also supported lo make the migration to ASIC much ea~ier than in normal prototypin~ solutions.
Finally as an added value, two c~nfiguration context~ are stored, wl-ich JUL. ~6. 1998 12 2gPM
CA 02239186 1998-0~-29 NO. 6887 P. 7 makes it possible to change the configuration o~ the whole circuit (or part of i~) with a microprocessor command. This feature, and the close interaction between the microprocessor and the pro~rantmable di~ital cells, nlakes this Field ~ro~rai~,mable Gate Array (FPGA~ a power~l tooi for applications ~ased 5 on hardware-software interaction and dynamic reconfiguration ~ hersfore two configuration contexts are stored for every programmable feature of t~e Fisld Programmable System on chip. In fact, every confi~uration bit is a dual port 2-bit memory cell.
~0 The microprocessor can then read an~ write any of these memory locations while in operation. This allows the user to reconfigurate a context while the other one is still active, ~hen changing the active context to the ncwone. With this approach, the whole circuit can be reconfigurated just by issuing15 a microprocessor command, and the reconfiguration time would be that of a microprocessor writing cycle. In fact, as long as the n~icroprocessor can reconn~urate any single cell of the FPGA, a set of cells rather than the whole chip can be reconfig~rated "on the fly". Furthermore, the data inside the Flip-Flops is also duplicated, and can also be read and written by the 20 microproc~ssor while the application is runnin~. When the context i~ swapped,the status o~ the Flip-Flops can be maintained or stored with the rest o~ the contex~. Thi~ makes it possible to initialise the Flip-Flops in the non-active context before setting it as active, and also to sav~ the values of the circuit nodes when chan~ing the context.
This technique known as hardware swap, makes it possible to efficiently work with virtual hardware. Non-active contexts keep their configuration and data just like virtual memory that is stored into a swap file in a computer system.
A hardware swap takes place when the virtual hardware is mapped back onto 30 the actual hardw~r~ resources, just like the information inside lhe sw~p archive is restored onto the actual memory of a computer when required a~ain.
Moreover, an analo~y c~n be esta~lished betw~en virtual hardware and software procedures ~lobal variables in soft~Jvare procedures c~n be compared to dats in the Flip~Flops which are kept aner hardware swap, and procedure 35 parameters can be compared t~ data in the Flip-Flops which are saved and JUl,. Ib. 1998 12:25PM CA 02239l86 1998-05-29 NO. 6887 P 8 restored durinQ the h~rdware swap.
In this way, the design procedure can be mapped in a closed flow diagr~rn that have Ihrse source vertexes, in a such way that starting from ~ach 5 of these vertex it gets, ~irectly or indire~tly, to the simulation and/or resl time emulation, the outcome is the integrated waveform representation. These source vertexes correspond to the field pro~rammable system on ohip itself, the desi~n is m~pped onto the o~,vn chip, the H~L desi~n, the functional blocks for inte~rated source code design. From these vertexes it is possible to access, 10 directly or indirectly, to the simulation b10cks or/and the inte~rated emul~tion.
The indirect ways include ~locks that determine the chip or devi~e pro~raming from where the real tirne inte~rated emulation is accessed.
The key point of this desi~n flow is that it follows an inte~rated 15 methodolo~y. This implies integrated design specification, simulation, emutation, waveform displ~y, t~chnolo~y mapping (with placement and routin3) and d~vice progr~mmin~.
~rom the afore mentioned cl~scription it is easy to deduct the 20 advanta~es provided by the process for prototyping mixed signal applic~tions and field pro~rammable system on a chip for the application of this process. ln this way, the inte~rated methodolo~y can be carried out due lo th~ flexibllity of the configurable analo~ue and digital hardware, and Ih~ easy inter~ace between t~e digital resources. the analogue subsystem and the mic~oprocessor. In the ~5 same way, the use of a fi~ld Programmable System on a chip in the process forthe ptototyping of mixed si~nal applications provides immediate reduction of Printed Circuit Board (PCB) space, device reusability, dynamic reconfisurabilityand fast delivery to market, what altosether rnakes the chip more suita~le for prototyping, pre-series manufacture and mioroelectronics research.
Description of the fi~ures To better understand the object of the present invention we described hereinaffer a practical preferential embodiment of the process for prototyping 35 of mixed signai applications and the field proQramn able system on a chip for JUL. I6. 1998 12:25PM CA 02239186 1998-0~-29 NO. 68~7 P. 9 the application of sai~ process, according to the attached figures. These figures show 1 ) fi~ure 1 shows a field programmable system on a chip block diagram.
CA 02239186 1998-0~-29 NO. 6~87 P. ~
PROCESS FOR THE PROTOlYPING OF l~lIXED SIGI~IAL APPLICATIONS
AN~ FIELD PROGRAMMABLE SYSTEM C~N A Cl IIP FOR THE
APPLICATION OF SA1D PROCESS.
5 ~e~ri~ion Object of the in-~ention The object of the present inventicn consists of a process for the 10 prototyping of mixed signal applications 0nd a field pro~rammable system on a chip for the applioati~n of said process, independently usable and adaptable to different analo~ue and/or di~ital hard~vare applications and capable to provide a direct interfac~ between hardware and sofl~are. This process shows important advantages o~er the systems currently used for this purpose.
There is a big nunlber of applications based on dynamic reconfiguration that could be identified and implemented with the digital hardware system of thepresent invention. These include communication s~itches, parallel processing applications as irna~e processing, array-based applicationsl etc.
E~ackground of the invention As t~e complexity of electronic systems grows, it becomes more di~ficult to follow a traditional desi~n methodolo~y of workin~ separately on different 25 subsystems with different design and prototyping tools, System designers havebeen searching for flexibl~ prototypin~ systems onto which they could map lar~e desi~ns to validate them bef~re manufacture, but only microprocessor ern~Jlators and digital conftgurable arrays have been available in the past. As a consequence of this need, analo~ue pro~rammable arrays have appeared 30 recently, confirming the interest that the industry sho~s for field-programm~ble devices suitable for fast prototypin~ for n~arket applicqtions.
Currently mixed-si~nal applications are typically s~lved in three domains:
di~ital hardware, analogue hard~are, and microprocessor pro~ram~ It is normal 35 for a rnedi~m complexity rnix~d ~ignal integrat~d circuit ~o include a JUL. 1~. 1998 12.2~P~ CA 02239186 1998-0~-29 NO. 6887 P 5 microprocessor core to run a user program, some ~igital hardware for control purposes and an analo~ue subsyste~ for data acquisition or analo3ue applications. In such cass, the typical designer normally follows a discrete methodolo~y an assembier compiler-debu~ger for the microprocessor program, a desi~n ent~ tool ~either schematic capture or HDL) and a digital simulator forthe digital hard~are, and an analo~ue sirnulator for the analogue su~system.
The main problem for users of this methodology is that the design is conceived and desi~n~d separately and it turns out to be difficult to control the interfaces between these three domains. The situation is also not very promisin~ about 10 prototyping: the best solution normally i5 to use a field programmable ~ate array (~PGA) for the digital hardware, some cliscrete Integrated Circuits or, recently, an analo~ue array for the analo~ue hardware, and a microprocessor entulator for the user program. Again, a completely different developrnent system has to be used for each part, and special care has ~o be taken when desi~nins the 15 different interfaces.
With the purpose to preYent the deficiencies presented by the processes for prototyping mixed si~nal applications currently in the market, it has been deveioped a ne~v process for prototyping mixed si~nal applications and field 20 pro~rammable systen~ on a chip for the application of said process, the object of the p~esent invention.
Descriptlon of the Invention In this context it is introd~Jced the process for prototypin~ mixed sl~nal applications and field pro~ramnlable system on a chip for the application of this process, the aim of the current invention, that is a new concept for system prototypin3 and programmable hardware. This system consists of a mixed-si~nal field prosramn~able device (FPD) with a standard microprocessor corel a suitable set of Computer Aided Design tools (CAD tools) to easily program it, and a set of library macros and cells ~Ivhich support a number of typical applications ~o be easily mapped onto the Field Pro~rammable Gate Array and migrsted to an ASIC ~fte~ards, if req~ired.
In particular the field progla~ ,able system on chip for the application of JUL. ~6. ~998 12 ~P~
CA 02239186 1998-0~-29 NO. 6887 P. 6 the process for the prototyping o~ mixed si~nal applio~tions includes, preferably, a microprocessor block, integrated storage media for writing and readin~ as, pr~ferably, a ~AM memory, at least one di~ital programm~ble macro cell, analogue cel1s and connection interfaces of the di~ital and analogue5 cells.
~ he interaction between each of the three domains ~di0ital hardware, analogue hardware and microprocessor programs) is as close as it can be; the microprocessor can read and ~rite the confi~uration of the analo~ue and digital 10 hard~are ~an physically inte~ce ports and the entire n~icroprocessor bus can be connscted to the routing channels of the Field Programmable Gate Array (FPGA), can examine in real time, any point within the digital blocks or analog subsystems, and can also chan3e data in real time within the flip-flops housed insi~e digital prosrammable cells WhiCh fornl on chip the field pro~rammable 15 systBm~ The microprocessor is then used to configurzte (and reconfigurate~ the programmabls cells, to interact with the actual hardware mapped onto ~hem and to run general purpose user programs.
The invention concept relies upon the fuily integrated desi~n and 20 pro~otypin~ methodology that the ~ser can follow with such a system. ~ powerful set of user-friendly CAD tools is provided, with the final target of letting the user spectfy, simulate, emulate (probe) and map the complete design on a sin~le chip usin~ one desi~n enYironment. ~his includes mixed-signal schematic capture and simulation, automatic techno10gy n apping, placement and routing 25 tools, an integrated emulation software (which allows step by step pro~ram execution and real time internal signal checking), ~nd an in~eQrsted device p~ogrammin~ package.
A lar~e ~et of library macros provides op~imised solutions to typical 30 design needs, allo~Ning the user to inlplement his own macros zt any desi~n level, frorn HDL to any manual placemsnt and routing. A parallel ASIC library is also supported lo make the migration to ASIC much ea~ier than in normal prototypin~ solutions.
Finally as an added value, two c~nfiguration context~ are stored, wl-ich JUL. ~6. 1998 12 2gPM
CA 02239186 1998-0~-29 NO. 6887 P. 7 makes it possible to change the configuration o~ the whole circuit (or part of i~) with a microprocessor command. This feature, and the close interaction between the microprocessor and the pro~rantmable di~ital cells, nlakes this Field ~ro~rai~,mable Gate Array (FPGA~ a power~l tooi for applications ~ased 5 on hardware-software interaction and dynamic reconfiguration ~ hersfore two configuration contexts are stored for every programmable feature of t~e Fisld Programmable System on chip. In fact, every confi~uration bit is a dual port 2-bit memory cell.
~0 The microprocessor can then read an~ write any of these memory locations while in operation. This allows the user to reconfigurate a context while the other one is still active, ~hen changing the active context to the ncwone. With this approach, the whole circuit can be reconfigurated just by issuing15 a microprocessor command, and the reconfiguration time would be that of a microprocessor writing cycle. In fact, as long as the n~icroprocessor can reconn~urate any single cell of the FPGA, a set of cells rather than the whole chip can be reconfig~rated "on the fly". Furthermore, the data inside the Flip-Flops is also duplicated, and can also be read and written by the 20 microproc~ssor while the application is runnin~. When the context i~ swapped,the status o~ the Flip-Flops can be maintained or stored with the rest o~ the contex~. Thi~ makes it possible to initialise the Flip-Flops in the non-active context before setting it as active, and also to sav~ the values of the circuit nodes when chan~ing the context.
This technique known as hardware swap, makes it possible to efficiently work with virtual hardware. Non-active contexts keep their configuration and data just like virtual memory that is stored into a swap file in a computer system.
A hardware swap takes place when the virtual hardware is mapped back onto 30 the actual hardw~r~ resources, just like the information inside lhe sw~p archive is restored onto the actual memory of a computer when required a~ain.
Moreover, an analo~y c~n be esta~lished betw~en virtual hardware and software procedures ~lobal variables in soft~Jvare procedures c~n be compared to dats in the Flip~Flops which are kept aner hardware swap, and procedure 35 parameters can be compared t~ data in the Flip-Flops which are saved and JUl,. Ib. 1998 12:25PM CA 02239l86 1998-05-29 NO. 6887 P 8 restored durinQ the h~rdware swap.
In this way, the design procedure can be mapped in a closed flow diagr~rn that have Ihrse source vertexes, in a such way that starting from ~ach 5 of these vertex it gets, ~irectly or indire~tly, to the simulation and/or resl time emulation, the outcome is the integrated waveform representation. These source vertexes correspond to the field pro~rammable system on ohip itself, the desi~n is m~pped onto the o~,vn chip, the H~L desi~n, the functional blocks for inte~rated source code design. From these vertexes it is possible to access, 10 directly or indirectly, to the simulation b10cks or/and the inte~rated emul~tion.
The indirect ways include ~locks that determine the chip or devi~e pro~raming from where the real tirne inte~rated emulation is accessed.
The key point of this desi~n flow is that it follows an inte~rated 15 methodolo~y. This implies integrated design specification, simulation, emutation, waveform displ~y, t~chnolo~y mapping (with placement and routin3) and d~vice progr~mmin~.
~rom the afore mentioned cl~scription it is easy to deduct the 20 advanta~es provided by the process for prototyping mixed signal applic~tions and field pro~rammable system on a chip for the application of this process. ln this way, the inte~rated methodolo~y can be carried out due lo th~ flexibllity of the configurable analo~ue and digital hardware, and Ih~ easy inter~ace between t~e digital resources. the analogue subsystem and the mic~oprocessor. In the ~5 same way, the use of a fi~ld Programmable System on a chip in the process forthe ptototyping of mixed si~nal applications provides immediate reduction of Printed Circuit Board (PCB) space, device reusability, dynamic reconfisurabilityand fast delivery to market, what altosether rnakes the chip more suita~le for prototyping, pre-series manufacture and mioroelectronics research.
Description of the fi~ures To better understand the object of the present invention we described hereinaffer a practical preferential embodiment of the process for prototyping 35 of mixed signai applications and the field proQramn able system on a chip for JUL. I6. 1998 12:25PM CA 02239186 1998-0~-29 NO. 68~7 P. 9 the application of sai~ process, according to the attached figures. These figures show 1 ) fi~ure 1 shows a field programmable system on a chip block diagram.
2) Fisure 2 shows di~ital ma-cro cell block dia~ram. This cell is included 5 in the device sho~ed in Figure l.
3) Figure 3 shows a 2 bit dou~le port memory cell for each configuration bit,
4) figure 4 shows a general Yiew of the process for prototypin~ mixed sisnal app~ications.
Preferential embodirnent of the invention The field programmabie system on a chip, object of the present invention inch~des a RAM memory (1), a microprocessor (2), programmable digital macro 15 cell (3) and programmable analogue cells (4~. As it is seen in the Fi3ure 1, the system includes several inter~ces (S,6,7,8) needed for ths correct system function.The Digital Macro Cell (DMC) is a lar~e sranularity, LUT based (9.1, 9.2, 9.3, 9.4), synthesis targe~ed 4-bit wide pro~ramrnable cell.
~0 Each searchin~ ta~le (LUT) (9.1, 9.2, 9,3, 9.4) can implement any Boolean function of 4 inputs, and two LUTs can be combined to form a 5 input function. The four LUTs of a ~MC can be combined to perForm any 6 input Boolean function. Four flip-flops (FF)( 10.1, 10.2, 10.3, 1û.4) are available within every Digital Macro Cell (OMC), and each one can be independently 25 confi~ured as mux-type or enable and latch or FF, and with synchronous and asynchronous set or reset. Both parts (combinational and sequential) of the DMC can be used more or less independently. Ther3 also is a number of macro modes which can confi3urate the DMC as a 16x4 memory (in fact, t~No independent 1 6x~ memories), a 4 bit adder designed for a cascade 30 arrangement with in and o~t loading, a displacement recording designed for a ~oP~e arrangement with a predeterminated load value and qualifioation, and a 4 bit increase or decrease counter desisned for a cascade arran~ment with a predeterminated load value and qualification. These macro functions are especially suitable for use on synthesis programs JUL. 15. 1998 12:25PM CA 02239186 1998-05-29 N0. 6887 P. ~~
The analo~ue subsystem(4) is composed of fixed functionality blocks of coarse granularity. The analogue functions include user programrnable amplifiers, filters, analo~ue multiplexers, cornparators, volta~e refere"ces, 10-12 bits Analogue Di~ital ConvenersJ Di~ital Anatogue Converters (ADCI~ACs,)
Preferential embodirnent of the invention The field programmabie system on a chip, object of the present invention inch~des a RAM memory (1), a microprocessor (2), programmable digital macro 15 cell (3) and programmable analogue cells (4~. As it is seen in the Fi3ure 1, the system includes several inter~ces (S,6,7,8) needed for ths correct system function.The Digital Macro Cell (DMC) is a lar~e sranularity, LUT based (9.1, 9.2, 9.3, 9.4), synthesis targe~ed 4-bit wide pro~ramrnable cell.
~0 Each searchin~ ta~le (LUT) (9.1, 9.2, 9,3, 9.4) can implement any Boolean function of 4 inputs, and two LUTs can be combined to form a 5 input function. The four LUTs of a ~MC can be combined to perForm any 6 input Boolean function. Four flip-flops (FF)( 10.1, 10.2, 10.3, 1û.4) are available within every Digital Macro Cell (OMC), and each one can be independently 25 confi~ured as mux-type or enable and latch or FF, and with synchronous and asynchronous set or reset. Both parts (combinational and sequential) of the DMC can be used more or less independently. Ther3 also is a number of macro modes which can confi3urate the DMC as a 16x4 memory (in fact, t~No independent 1 6x~ memories), a 4 bit adder designed for a cascade 30 arrangement with in and o~t loading, a displacement recording designed for a ~oP~e arrangement with a predeterminated load value and qualifioation, and a 4 bit increase or decrease counter desisned for a cascade arran~ment with a predeterminated load value and qualification. These macro functions are especially suitable for use on synthesis programs JUL. 15. 1998 12:25PM CA 02239186 1998-05-29 N0. 6887 P. ~~
The analo~ue subsystem(4) is composed of fixed functionality blocks of coarse granularity. The analogue functions include user programrnable amplifiers, filters, analo~ue multiplexers, cornparators, volta~e refere"ces, 10-12 bits Analogue Di~ital ConvenersJ Di~ital Anatogue Converters (ADCI~ACs,)
5 etc Several parameters can be configurated from ths microprocessor (2), ~uch as the operating frequency of the filters, Ihe gain and offset of the amplifiers, the function of the ADC/DAC block (as a OAC or as an ADC), etc.
An optimised serial link is provided to communicate the microprocessor 10 core with the digital and analogue hardvYare. The configuration is read and written using this interface, and the actual signals at the outputs of the Digital Macro Cells (3) (DMCs) can be accessed by the microprocessor (2) too. The Analogue to Digital ConYerter (ADC) can also be triggered using this interface, so it is possible to use it from the microprocessor without wasting configurable15 hardware resources (DMCs and routins channels3 to map the ADC onto the microprocessor address space.
Figure 3 shows a 2 bit double port n,en,or~ cell for each confi~uration bit.
In ~his fi~ur~ it can be seen the flip-flops, these memory locations can be read20 and written by the microprocessor (2). While one memory is mode active, the other can be reconfi~urated later, shiftin~ the latter to active condltion, With this arrangement the design procedure is performed according to the steps shown in fi~ure 4, where a closed flow diagram corresponding to this design proceclure is shown. This design procedure include~ three source vertexes, in such way that sta~tin~ out from any of these, it ~ets, directly or indirectly, to the simulati~n and or a real time integrated emulation, so the c~rrespondin~ outcome can b~ seen in the intesrate~ ~aveform repres3ntation.
These source vertexes corresponds to the field pro~rammable system on chip 30 itself, ~here the design is mapped onto, the HDL deslgn, and ~n schematic entry tool, that determines 2 source code desi~n. Form these vertexes it is possible to access, directly or indirectly, to the simulation bi~cks or~and the integrated emulation. The indirect ways include blocks that determine the chip or device programming frorn where we have access to real tirne integrated 35 emulztion.
JUl. I~ ~998 ~2 ~6PM
CA 02239186 1998-0~-29 NO. 6881 P Il The key for the design procedure is the inte~rated process. This means that the user can prepare the desi~n specification, the simulation, the emulation, the waveform display, the technolo~y mappin~ with placement and routing and the device programmin~ in an inteyrated way The user can then connect with the system practically at every point of the design flow. For instance, the user can specify the desi~n in HDL before doing the synthesis, or at gate level before the technology mapping, or work ~rith the ~i~ltal macro cells (chip) before its placen ent and routin~, or implement 10 a manual placement and routing.
The emul~tion box allows for the emulatl~n of the microprocessor program incl~ding step by step execution, breakpoints, etc., and probing of th~
in~ernal points of the analo~ue or digital architecture. This way, the user can 15 ~-heck the sequential pro~ram correct per~orrnance and, at the same time, see the current values of actual nodes of the circLJit.
Finally, a simple seria~ interface to the chip o~nside can ~e used to power up the system from a PC, so a conlplete development system can be ~0 implemen~ed using only the Field programmable system on a chip, the Personal Computer (PC) and a RS232 interface for their interconnection.
An integrated waveform display i5 provided to understand how the entire system is interacting at a ~iven monlent on operation time or simulation time.
25 This device includes an analo~ue waveform display (in fact, when emulation i8~sed this is quite like a di3ital oscilioscope), a diQital waveform display (this is like a losic analyser) and a code execution window (where one can trace the program, set breakpoints, etc.~.
Once It has ~een described the nature of the present inverltion and one way to implen~ent it, we only have to add thst as a whole or in some parts of itit is possible to introduce some chan~es of sh~pe, materials and arran~ement, as long as these modifications do not chan~e in a s~bstantial ~ay, the main characteristics of this inYention, which are clairned in the following para~raphs.
An optimised serial link is provided to communicate the microprocessor 10 core with the digital and analogue hardvYare. The configuration is read and written using this interface, and the actual signals at the outputs of the Digital Macro Cells (3) (DMCs) can be accessed by the microprocessor (2) too. The Analogue to Digital ConYerter (ADC) can also be triggered using this interface, so it is possible to use it from the microprocessor without wasting configurable15 hardware resources (DMCs and routins channels3 to map the ADC onto the microprocessor address space.
Figure 3 shows a 2 bit double port n,en,or~ cell for each confi~uration bit.
In ~his fi~ur~ it can be seen the flip-flops, these memory locations can be read20 and written by the microprocessor (2). While one memory is mode active, the other can be reconfi~urated later, shiftin~ the latter to active condltion, With this arrangement the design procedure is performed according to the steps shown in fi~ure 4, where a closed flow diagram corresponding to this design proceclure is shown. This design procedure include~ three source vertexes, in such way that sta~tin~ out from any of these, it ~ets, directly or indirectly, to the simulati~n and or a real time integrated emulation, so the c~rrespondin~ outcome can b~ seen in the intesrate~ ~aveform repres3ntation.
These source vertexes corresponds to the field pro~rammable system on chip 30 itself, ~here the design is mapped onto, the HDL deslgn, and ~n schematic entry tool, that determines 2 source code desi~n. Form these vertexes it is possible to access, directly or indirectly, to the simulation bi~cks or~and the integrated emulation. The indirect ways include blocks that determine the chip or device programming frorn where we have access to real tirne integrated 35 emulztion.
JUl. I~ ~998 ~2 ~6PM
CA 02239186 1998-0~-29 NO. 6881 P Il The key for the design procedure is the inte~rated process. This means that the user can prepare the desi~n specification, the simulation, the emulation, the waveform display, the technolo~y mappin~ with placement and routing and the device programmin~ in an inteyrated way The user can then connect with the system practically at every point of the design flow. For instance, the user can specify the desi~n in HDL before doing the synthesis, or at gate level before the technology mapping, or work ~rith the ~i~ltal macro cells (chip) before its placen ent and routin~, or implement 10 a manual placement and routing.
The emul~tion box allows for the emulatl~n of the microprocessor program incl~ding step by step execution, breakpoints, etc., and probing of th~
in~ernal points of the analo~ue or digital architecture. This way, the user can 15 ~-heck the sequential pro~ram correct per~orrnance and, at the same time, see the current values of actual nodes of the circLJit.
Finally, a simple seria~ interface to the chip o~nside can ~e used to power up the system from a PC, so a conlplete development system can be ~0 implemen~ed using only the Field programmable system on a chip, the Personal Computer (PC) and a RS232 interface for their interconnection.
An integrated waveform display i5 provided to understand how the entire system is interacting at a ~iven monlent on operation time or simulation time.
25 This device includes an analo~ue waveform display (in fact, when emulation i8~sed this is quite like a di3ital oscilioscope), a diQital waveform display (this is like a losic analyser) and a code execution window (where one can trace the program, set breakpoints, etc.~.
Once It has ~een described the nature of the present inverltion and one way to implen~ent it, we only have to add thst as a whole or in some parts of itit is possible to introduce some chan~es of sh~pe, materials and arran~ement, as long as these modifications do not chan~e in a s~bstantial ~ay, the main characteristics of this inYention, which are clairned in the following para~raphs.
Claims (5)
1.- Process for the prototyping of mixed signal applications, usable independently in relation to a associated hardware associated in order to enable the user to specify, simulate, emulate and project a complete design and its prototyping, characterised in that the specification, the simulation, the emulation and the design projected are integrated functions in only one design environment, furthermore this process includes:
- Schematic capture and mixed- signal simulation - Reading and writing of the configuration of the associated hardware trough a microprocessor.
- To examine in real time every point within the digital blocks or analogue subsystems included in the associated hardware.
- To change data in real time within the programmable digital cells of this associated hardware.
- To configurate and reconfigurate the programmable digital cells.
- To interact with the associated hardware.
- To execute general purpose user programs -To store the configuration context that make possible the configuration context change in the whole circuit following a microprocessor command.
- To export data to an Application Specific Integrated Circuit (ASIC) using an ASIC library.
- Schematic capture and mixed- signal simulation - Reading and writing of the configuration of the associated hardware trough a microprocessor.
- To examine in real time every point within the digital blocks or analogue subsystems included in the associated hardware.
- To change data in real time within the programmable digital cells of this associated hardware.
- To configurate and reconfigurate the programmable digital cells.
- To interact with the associated hardware.
- To execute general purpose user programs -To store the configuration context that make possible the configuration context change in the whole circuit following a microprocessor command.
- To export data to an Application Specific Integrated Circuit (ASIC) using an ASIC library.
2. - Process for the prototyping of mixed signal applications, according to claim 1, characterised in that the configuration context change includes the storage of programmable cells status, giving the possibility to initialise the cells in the non active context before to be activated, also to keep the circuit node values during the context change.
3.- Field Programmable System on a chip for the application of the process according to calims 1 and 2, characterised in that the system includes:
- One microprocessor (2) - On chip RAM memory (1) - At least one digital macro cell (3) - Analogue cells (4) - Analogue (4) and digital cells (3) connection Interfaces (5,6,7,8)
- One microprocessor (2) - On chip RAM memory (1) - At least one digital macro cell (3) - Analogue cells (4) - Analogue (4) and digital cells (3) connection Interfaces (5,6,7,8)
4.- A system according to claim 3, characterised in that the digital macro cell (3) is of big granularity, comprising several LUTs (searching tables) (9.1,9.2, 9.3, 9.4), to implement boolean functions in an independent way or combined to each other. Every searching table has a 4-bit wide.
5.- A system, according to claim 4, characterised in that each digital macro cell (3) includes 4 flip-flops (10.1, 10.2, 10.3, 10.4). Each flip-flop can be configurated in an independent way.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ES9602168 | 1996-10-10 | ||
| ESP9602168 | 1996-10-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2239186A1 true CA2239186A1 (en) | 1998-04-16 |
Family
ID=8296353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002239186A Abandoned CA2239186A1 (en) | 1996-10-10 | 1996-12-30 | Process for the prototyping of mixed signal applications and field programmable system on a chip for applying said process |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6460172B1 (en) |
| EP (1) | EP0871223A1 (en) |
| JP (1) | JPH11507478A (en) |
| KR (1) | KR19990071991A (en) |
| AU (1) | AU1546797A (en) |
| CA (1) | CA2239186A1 (en) |
| WO (1) | WO1998015976A1 (en) |
Families Citing this family (121)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6152612A (en) * | 1997-06-09 | 2000-11-28 | Synopsys, Inc. | System and method for system level and circuit level modeling and design simulation using C++ |
| GB9827183D0 (en) | 1998-12-11 | 1999-02-03 | Mitel Semiconductor Ltd | Integration of externally developed logic in a memory mapped system |
| US6701340B1 (en) | 1999-09-22 | 2004-03-02 | Lattice Semiconductor Corp. | Double differential comparator and programmable analog block architecture using same |
| US6362684B1 (en) | 2000-02-17 | 2002-03-26 | Lattice Semiconductor Corporation | Amplifier having an adjust resistor network |
| US6424209B1 (en) | 2000-02-18 | 2002-07-23 | Lattice Semiconductor Corporation | Integrated programmable continuous time filter with programmable capacitor arrays |
| US6331770B1 (en) * | 2000-04-12 | 2001-12-18 | Advantest Corp. | Application specific event based semiconductor test system |
| US6587995B1 (en) * | 2000-04-19 | 2003-07-01 | Koninklijke Philips Electronics N.V. | Enhanced programmable core model with integrated graphical debugging functionality |
| US6947883B1 (en) * | 2000-07-19 | 2005-09-20 | Vikram Gupta | Method for designing mixed signal integrated circuits and configurable synchronous digital noise emulator circuit |
| US7188063B1 (en) | 2000-10-26 | 2007-03-06 | Cypress Semiconductor Corporation | Capturing test/emulation and enabling real-time debugging using an FPGA for in-circuit emulation |
| US7149316B1 (en) * | 2000-10-26 | 2006-12-12 | Cypress Semiconductor Corporation | Microcontroller having an on-chip high gain amplifier |
| US7765095B1 (en) | 2000-10-26 | 2010-07-27 | Cypress Semiconductor Corporation | Conditional branching in an in-circuit emulation system |
| US7092980B1 (en) | 2000-10-26 | 2006-08-15 | Cypress Semiconductor Corporation | Programming architecture for a programmable analog system |
| US8160864B1 (en) | 2000-10-26 | 2012-04-17 | Cypress Semiconductor Corporation | In-circuit emulator and pod synchronized boot |
| US7185162B1 (en) | 2000-10-26 | 2007-02-27 | Cypress Semiconductor Corporation | Method and apparatus for programming a flash memory |
| US7127630B1 (en) | 2000-10-26 | 2006-10-24 | Cypress Semiconductor Corp. | Method for entering circuit test mode |
| US6724220B1 (en) | 2000-10-26 | 2004-04-20 | Cyress Semiconductor Corporation | Programmable microcontroller architecture (mixed analog/digital) |
| US7206733B1 (en) | 2000-10-26 | 2007-04-17 | Cypress Semiconductor Corporation | Host to FPGA interface in an in-circuit emulation system |
| US7076420B1 (en) | 2000-10-26 | 2006-07-11 | Cypress Semiconductor Corp. | Emulator chip/board architecture and interface |
| US8176296B2 (en) | 2000-10-26 | 2012-05-08 | Cypress Semiconductor Corporation | Programmable microcontroller architecture |
| US8103496B1 (en) | 2000-10-26 | 2012-01-24 | Cypress Semicondutor Corporation | Breakpoint control in an in-circuit emulation system |
| US8149048B1 (en) | 2000-10-26 | 2012-04-03 | Cypress Semiconductor Corporation | Apparatus and method for programmable power management in a programmable analog circuit block |
| US6605962B2 (en) | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
| US7076595B1 (en) | 2001-05-18 | 2006-07-11 | Xilinx, Inc. | Programmable logic device including programmable interface core and central processing unit |
| US6583652B1 (en) | 2001-06-01 | 2003-06-24 | Lattice Semiconductor Corporation | Highly linear programmable transconductor with large input-signal range |
| US6806771B1 (en) | 2001-06-01 | 2004-10-19 | Lattice Semiconductor Corp. | Multimode output stage converting differential to single-ended signals using current-mode input signals |
| US6717451B1 (en) | 2001-06-01 | 2004-04-06 | Lattice Semiconductor Corporation | Precision analog level shifter with programmable options |
| US7051308B2 (en) * | 2001-06-01 | 2006-05-23 | Virtual Silicon Technology, Inc. | Method and apparatus for integrated circuit design with library cells |
| US6976239B1 (en) * | 2001-06-12 | 2005-12-13 | Altera Corporation | Methods and apparatus for implementing parameterizable processors and peripherals |
| US7363609B2 (en) * | 2001-07-26 | 2008-04-22 | International Business Machines Corporation | Method of logic circuit synthesis and design using a dynamic circuit library |
| US6781407B2 (en) | 2002-01-09 | 2004-08-24 | Xilinx, Inc. | FPGA and embedded circuitry initialization and processing |
| US7420392B2 (en) * | 2001-09-28 | 2008-09-02 | Xilinx, Inc. | Programmable gate array and embedded circuitry initialization and processing |
| US6798239B2 (en) * | 2001-09-28 | 2004-09-28 | Xilinx, Inc. | Programmable gate array having interconnecting logic to support embedded fixed logic circuitry |
| US7406674B1 (en) | 2001-10-24 | 2008-07-29 | Cypress Semiconductor Corporation | Method and apparatus for generating microcontroller configuration information |
| US8078970B1 (en) | 2001-11-09 | 2011-12-13 | Cypress Semiconductor Corporation | Graphical user interface with user-selectable list-box |
| US8042093B1 (en) * | 2001-11-15 | 2011-10-18 | Cypress Semiconductor Corporation | System providing automatic source code generation for personalization and parameterization of user modules |
| US6983405B1 (en) | 2001-11-16 | 2006-01-03 | Xilinx, Inc., | Method and apparatus for testing circuitry embedded within a field programmable gate array |
| US6996758B1 (en) | 2001-11-16 | 2006-02-07 | Xilinx, Inc. | Apparatus for testing an interconnecting logic fabric |
| US7010773B1 (en) * | 2001-11-19 | 2006-03-07 | Cypress Semiconductor Corp. | Method for designing a circuit for programmable microcontrollers |
| US6637015B1 (en) * | 2001-11-19 | 2003-10-21 | Cypress Semiconductor Corporation | System and method for decoupling and iterating resources associated with a module |
| US6886092B1 (en) | 2001-11-19 | 2005-04-26 | Xilinx, Inc. | Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion |
| US7770113B1 (en) | 2001-11-19 | 2010-08-03 | Cypress Semiconductor Corporation | System and method for dynamically generating a configuration datasheet |
| US7337407B1 (en) | 2001-11-19 | 2008-02-26 | Cypress Semiconductor Corporation | Automatic application programming interface (API) generation for functional blocks |
| US7844437B1 (en) | 2001-11-19 | 2010-11-30 | Cypress Semiconductor Corporation | System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit |
| US6966039B1 (en) * | 2001-11-19 | 2005-11-15 | Cypress Semiconductor Corp. | Method for facilitating microcontroller programming |
| US6971004B1 (en) * | 2001-11-19 | 2005-11-29 | Cypress Semiconductor Corp. | System and method of dynamically reconfiguring a programmable integrated circuit |
| US8069405B1 (en) * | 2001-11-19 | 2011-11-29 | Cypress Semiconductor Corporation | User interface for efficiently browsing an electronic document using data-driven tabs |
| US7774190B1 (en) | 2001-11-19 | 2010-08-10 | Cypress Semiconductor Corporation | Sleep and stall in an in-circuit emulation system |
| US6820248B1 (en) | 2002-02-14 | 2004-11-16 | Xilinx, Inc. | Method and apparatus for routing interconnects to devices with dissimilar pitches |
| US6976160B1 (en) | 2002-02-22 | 2005-12-13 | Xilinx, Inc. | Method and system for controlling default values of flip-flops in PGA/ASIC-based designs |
| US6754882B1 (en) * | 2002-02-22 | 2004-06-22 | Xilinx, Inc. | Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) |
| US6941538B2 (en) * | 2002-02-22 | 2005-09-06 | Xilinx, Inc. | Method and system for integrating cores in FPGA-based system-on-chip (SoC) |
| US6934922B1 (en) | 2002-02-27 | 2005-08-23 | Xilinx, Inc. | Timing performance analysis |
| US7007121B1 (en) | 2002-02-27 | 2006-02-28 | Xilinx, Inc. | Method and apparatus for synchronized buses |
| US7111217B1 (en) | 2002-02-28 | 2006-09-19 | Xilinx, Inc. | Method and system for flexibly nesting JTAG TAP controllers for FPGA-based system-on-chip (SoC) |
| US6839874B1 (en) | 2002-02-28 | 2005-01-04 | Xilinx, Inc. | Method and apparatus for testing an embedded device |
| US7187709B1 (en) | 2002-03-01 | 2007-03-06 | Xilinx, Inc. | High speed configurable transceiver architecture |
| US7111220B1 (en) | 2002-03-01 | 2006-09-19 | Xilinx, Inc. | Network physical layer with embedded multi-standard CRC generator |
| US7088767B1 (en) | 2002-03-01 | 2006-08-08 | Xilinx, Inc. | Method and apparatus for operating a transceiver in different data rates |
| US6961919B1 (en) | 2002-03-04 | 2005-11-01 | Xilinx, Inc. | Method of designing integrated circuit having both configurable and fixed logic circuitry |
| US8103497B1 (en) | 2002-03-28 | 2012-01-24 | Cypress Semiconductor Corporation | External interface for event architecture |
| US7099818B1 (en) | 2002-03-29 | 2006-08-29 | Cypress Semiconductor Corporation | System and method for automatically matching components in a debugging system |
| US7308608B1 (en) * | 2002-05-01 | 2007-12-11 | Cypress Semiconductor Corporation | Reconfigurable testing system and method |
| US6661724B1 (en) | 2002-06-13 | 2003-12-09 | Cypress Semiconductor Corporation | Method and system for programming a memory device |
| US6772405B1 (en) | 2002-06-13 | 2004-08-03 | Xilinx, Inc. | Insertable block tile for interconnecting to a device embedded in an integrated circuit |
| US7085973B1 (en) | 2002-07-09 | 2006-08-01 | Xilinx, Inc. | Testing address lines of a memory controller |
| US7099426B1 (en) | 2002-09-03 | 2006-08-29 | Xilinx, Inc. | Flexible channel bonding and clock correction operations on a multi-block data path |
| US7761845B1 (en) | 2002-09-09 | 2010-07-20 | Cypress Semiconductor Corporation | Method for parameterizing a user module |
| US7092865B1 (en) | 2002-09-10 | 2006-08-15 | Xilinx, Inc. | Method and apparatus for timing modeling |
| US6944836B1 (en) | 2002-11-15 | 2005-09-13 | Xilinx, Inc. | Structures and methods for testing programmable logic devices having mixed-fabric architectures |
| US7299307B1 (en) | 2002-12-24 | 2007-11-20 | Cypress Semiconductor Corporation | Analog I/O with digital signal processor array |
| US7068068B2 (en) * | 2003-03-18 | 2006-06-27 | Innovel Technology, Inc. | Re-configurable mixed-mode integrated circuit architecture |
| US6943621B1 (en) | 2003-05-21 | 2005-09-13 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Auto-routable, configurable, daisy chainable data acquisition system |
| US7603542B2 (en) | 2003-06-25 | 2009-10-13 | Nec Corporation | Reconfigurable electric computer, semiconductor integrated circuit and control method, program generation method, and program for creating a logic circuit from an application program |
| US7149996B1 (en) * | 2003-07-11 | 2006-12-12 | Xilinx, Inc. | Reconfigurable multi-stage crossbar |
| US7170315B2 (en) | 2003-07-31 | 2007-01-30 | Actel Corporation | Programmable system on a chip |
| US7421014B2 (en) * | 2003-09-11 | 2008-09-02 | Xilinx, Inc. | Channel bonding of a plurality of multi-gigabit transceivers |
| CN100340970C (en) * | 2004-02-11 | 2007-10-03 | 复旦大学 | Programmable digital-analog mixer member arrangement |
| US7295049B1 (en) | 2004-03-25 | 2007-11-13 | Cypress Semiconductor Corporation | Method and circuit for rapid alignment of signals |
| US8069436B2 (en) | 2004-08-13 | 2011-11-29 | Cypress Semiconductor Corporation | Providing hardware independence to automate code generation of processing device firmware |
| US8286125B2 (en) | 2004-08-13 | 2012-10-09 | Cypress Semiconductor Corporation | Model for a hardware device-independent method of defining embedded firmware for programmable systems |
| US8082531B2 (en) | 2004-08-13 | 2011-12-20 | Cypress Semiconductor Corporation | Method and an apparatus to design a processing system using a graphical user interface |
| DE102004059673B4 (en) * | 2004-12-10 | 2011-02-03 | Infineon Technologies Ag | System on chip, exposure mask arrangement and corresponding manufacturing method |
| US7332976B1 (en) | 2005-02-04 | 2008-02-19 | Cypress Semiconductor Corporation | Poly-phase frequency synthesis oscillator |
| US7340693B2 (en) * | 2005-02-24 | 2008-03-04 | Nick Martin | System for designing re-programmable digital hardware platforms |
| US7400183B1 (en) | 2005-05-05 | 2008-07-15 | Cypress Semiconductor Corporation | Voltage controlled oscillator delay cell and method |
| US8089461B2 (en) | 2005-06-23 | 2012-01-03 | Cypress Semiconductor Corporation | Touch wake for electronic devices |
| JP2007149031A (en) * | 2005-11-30 | 2007-06-14 | Fujitsu Ltd | Circuit evaluation method and device |
| US8085067B1 (en) | 2005-12-21 | 2011-12-27 | Cypress Semiconductor Corporation | Differential-to-single ended signal converter circuit and method |
| US8067948B2 (en) | 2006-03-27 | 2011-11-29 | Cypress Semiconductor Corporation | Input/output multiplexer bus |
| US8091064B2 (en) * | 2006-04-14 | 2012-01-03 | Panasonic Corporation | Supporting system, design supporting method, and computer-readable recording medium recorded with design supporting program |
| US8130025B2 (en) | 2007-04-17 | 2012-03-06 | Cypress Semiconductor Corporation | Numerical band gap |
| US9564902B2 (en) | 2007-04-17 | 2017-02-07 | Cypress Semiconductor Corporation | Dynamically configurable and re-configurable data path |
| US8516025B2 (en) | 2007-04-17 | 2013-08-20 | Cypress Semiconductor Corporation | Clock driven dynamic datapath chaining |
| US8040266B2 (en) | 2007-04-17 | 2011-10-18 | Cypress Semiconductor Corporation | Programmable sigma-delta analog-to-digital converter |
| US7737724B2 (en) | 2007-04-17 | 2010-06-15 | Cypress Semiconductor Corporation | Universal digital block interconnection and channel routing |
| US8092083B2 (en) * | 2007-04-17 | 2012-01-10 | Cypress Semiconductor Corporation | Temperature sensor with digital bandgap |
| US8026739B2 (en) | 2007-04-17 | 2011-09-27 | Cypress Semiconductor Corporation | System level interconnect with programmable switching |
| US8266575B1 (en) | 2007-04-25 | 2012-09-11 | Cypress Semiconductor Corporation | Systems and methods for dynamically reconfiguring a programmable system on a chip |
| US9720805B1 (en) * | 2007-04-25 | 2017-08-01 | Cypress Semiconductor Corporation | System and method for controlling a target device |
| US8065653B1 (en) | 2007-04-25 | 2011-11-22 | Cypress Semiconductor Corporation | Configuration of programmable IC design elements |
| US8788959B1 (en) | 2007-04-25 | 2014-07-22 | Cypress Semiconductor Corporation | System and method for monitoring a target device |
| US7937683B1 (en) | 2007-04-30 | 2011-05-03 | Innovations Holdings, L.L.C. | Method and apparatus for configurable systems |
| US8049569B1 (en) | 2007-09-05 | 2011-11-01 | Cypress Semiconductor Corporation | Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes |
| US8441298B1 (en) | 2008-07-01 | 2013-05-14 | Cypress Semiconductor Corporation | Analog bus sharing using transmission gates |
| US8201137B1 (en) * | 2009-03-06 | 2012-06-12 | Cadence Design Systems, Inc. | Method and apparatus for AMS simulation of integrated circuit design |
| US20100275170A1 (en) * | 2009-04-27 | 2010-10-28 | Mosys, Inc. | Porting Analog Circuit Designs |
| US9448964B2 (en) | 2009-05-04 | 2016-09-20 | Cypress Semiconductor Corporation | Autonomous control in a programmable system |
| US8179161B1 (en) | 2009-05-05 | 2012-05-15 | Cypress Semiconductor Corporation | Programmable input/output circuit |
| US8487655B1 (en) | 2009-05-05 | 2013-07-16 | Cypress Semiconductor Corporation | Combined analog architecture and functionality in a mixed-signal array |
| US9612987B2 (en) | 2009-05-09 | 2017-04-04 | Cypress Semiconductor Corporation | Dynamically reconfigurable analog routing circuits and methods for system on a chip |
| US8981754B1 (en) | 2009-05-10 | 2015-03-17 | Cypress Semiconductor Corporation | Programmable reference signal selection |
| US7969186B2 (en) * | 2009-06-02 | 2011-06-28 | Mips Technologies | Apparatus and method for forming a mixed signal circuit with fully customizable analog cells and programmable interconnect |
| US8472278B2 (en) | 2010-04-09 | 2013-06-25 | Qualcomm Incorporated | Circuits, systems and methods for adjusting clock signals based on measured performance characteristics |
| US20120268162A1 (en) * | 2011-04-21 | 2012-10-25 | Microchip Technology Incorporated | Configurable logic cells |
| US9450585B2 (en) | 2011-04-20 | 2016-09-20 | Microchip Technology Incorporated | Selecting four signals from sixteen inputs |
| US8804399B2 (en) | 2012-03-23 | 2014-08-12 | Micron Technology, Inc. | Multi-function resistance change memory cells and apparatuses including the same |
| CN103729490A (en) | 2012-10-15 | 2014-04-16 | 飞思卡尔半导体公司 | Mixed signal IP core prototype design system |
| US9076275B2 (en) * | 2013-03-13 | 2015-07-07 | Bosch Automotive Service Solutions Inc. | Vehicle measurement apparatus having a system-on-a-chip device and a sensor |
| CN103345162B (en) * | 2013-07-08 | 2016-01-20 | 国家电网公司 | A kind of power level digital-analog hybrid simulation system |
| CN103837776A (en) * | 2014-03-17 | 2014-06-04 | 国家电网公司 | Experimental system for voltage stability testing of AC/DC parallel power network |
| CN114397834A (en) * | 2021-12-06 | 2022-04-26 | 埃夫特智能装备股份有限公司 | Simulation FPGA system based on virtual robot controller and use method thereof |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4402044A (en) * | 1980-11-24 | 1983-08-30 | Texas Instruments Incorporated | Microprocessor with strip layout of busses, ALU and registers |
| US5197016A (en) * | 1988-01-13 | 1993-03-23 | International Chip Corporation | Integrated silicon-software compiler |
| US5402358A (en) * | 1990-05-14 | 1995-03-28 | Vlsi Technology, Inc. | Method and structure for the automated design of analog integrated circuits |
| WO1993016433A1 (en) * | 1992-02-07 | 1993-08-19 | Seiko Epson Corporation | Hardware emulation accelerator and method |
| JP2746502B2 (en) * | 1992-08-20 | 1998-05-06 | 三菱電機株式会社 | Apparatus and method for manufacturing semiconductor integrated circuit device and electronic circuit device |
| US5425036A (en) * | 1992-09-18 | 1995-06-13 | Quickturn Design Systems, Inc. | Method and apparatus for debugging reconfigurable emulation systems |
| US5361373A (en) * | 1992-12-11 | 1994-11-01 | Gilson Kent L | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor |
| US5438681A (en) * | 1993-08-24 | 1995-08-01 | Mensch, Jr.; William D. | Topography for CMOS microcomputer |
| US5959871A (en) * | 1993-12-23 | 1999-09-28 | Analogix/Portland State University | Programmable analog array circuit |
| US5894565A (en) * | 1996-05-20 | 1999-04-13 | Atmel Corporation | Field programmable gate array with distributed RAM and increased cell utilization |
| US6006022A (en) * | 1996-11-15 | 1999-12-21 | Microsystem Synthesis, Inc. | Cross-linked development and deployment apparatus and method |
-
1996
- 1996-12-30 KR KR1019980704282A patent/KR19990071991A/en not_active Application Discontinuation
- 1996-12-30 EP EP96945365A patent/EP0871223A1/en not_active Withdrawn
- 1996-12-30 AU AU15467/97A patent/AU1546797A/en not_active Abandoned
- 1996-12-30 CA CA002239186A patent/CA2239186A1/en not_active Abandoned
- 1996-12-30 JP JP10517204A patent/JPH11507478A/en active Pending
- 1996-12-30 WO PCT/ES1996/000253 patent/WO1998015976A1/en not_active Application Discontinuation
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2000
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|---|---|
| JPH11507478A (en) | 1999-06-29 |
| US6460172B1 (en) | 2002-10-01 |
| EP0871223A1 (en) | 1998-10-14 |
| KR19990071991A (en) | 1999-09-27 |
| WO1998015976A1 (en) | 1998-04-16 |
| AU1546797A (en) | 1998-05-05 |
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