CA2244683C - Pipelined sample and hold circuit with correlated double sampling - Google Patents
Pipelined sample and hold circuit with correlated double sampling Download PDFInfo
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- CA2244683C CA2244683C CA002244683A CA2244683A CA2244683C CA 2244683 C CA2244683 C CA 2244683C CA 002244683 A CA002244683 A CA 002244683A CA 2244683 A CA2244683 A CA 2244683A CA 2244683 C CA2244683 C CA 2244683C
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
- G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
Abstract
A signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a time multiplexed integrating amplifier circuit in which the output circuit is a pipelined sample and hold circuit which provides time multiplexed input signal samples and the feedback integration capacitor is discharged between samples.
At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.
At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.
Description
CA 02244683 l998-07-28 W 098/24092 PCTrUS97/21164 PIPELINED SAMPLE AND EOLD CIRCUIT
WITEI CORl~LATED DOUBLE SAMPLlNG
FIELD OF T~E TNVI~NTION
The present invention relates to sample and hold circuits, and in particular, to pipelined sample and hold circuits with correlated double sampling.
5 BACKGROUND OF Tl~E TNVENT~ON
Sample and hold circuits play an important role in data acquisition systems, particularly in those systems in which the signals con~ining the data of interest are ~h~nging faster than the system can acquire and appropriately process the data.
For example, in large area, flat panel im~ging systems, such as im:~ging systems for medical - 10 and document im~ging applications based upon amorphous silicon, the image sensor is typically arranged as an array of pixels, each of which consists of a photosensitive element and a thin film transistor (TFT). In order to achieve im~ging frame rates suitable for video processing and display, all gate and data line connections for the sensor are brought out to the edge of the array for connection to an off-array control circuit cont~ining row selection and charge sensing circuitry.
15 For a high resolution array, many pixels are used for each data line, with the result being a high data readout rate in order to sample each of the pixels within the time constraints of the real time video display. Accordingly, while the data for each pixel must be sampled accurately, it must also be sampled quickly and held available for a sufficient period of time to allow the pixel data to be appropriately processed, stored, etc.
However, such image data signals, due to the manner in which they are generated, include, in addition to the image component, a noise component which is generated as a result of the image array sc~nning process. For example, the circuitry used to acquire the image data information from each pixel typically includes a charge sensitive pre-amplifier which must be reset between each pixel. This resetting of the charge sensitive pre-amplifier immediately prior to reading out the 25 charge from each pixel generates a significant, and undesirable, noise component which, if not ~limin~ted during the sample and hold process, will significantly distort and obscure the true image information corresponding to that pixel.
Accordingly, it would be desirable to have a sample and hold circuit which is capable of çlimin~ting the noise component from the signal to be sampled.
W O 98/~4092 PCT/US97/21164 . 2 SUMMARY OF T~E INVENTION
In accordance with the present invention, correlated double sampling (CDS) is provided in a pipelined sample and hold circuit arr.hitectl-re. Such a circuit can be used advantageously in multiple çh~nnel, charge sensitive readout circuits in which multiple data ch~nn~lc of a sensor are 5 each connected to a charge sensitive pre-amplifier. In such an application, the CDS elirninates the noise associated with resetting the charge sensitive pre-amplifier, while the sample and hold circuitry allows the data from a previous channel to be read out during sampling of the present channel. By using a pipelined sample and hold architecture, maxirnum data s~mpling tirne, or "line time," is available for reading out the sampled data. Hence, only a very small portion of each pixel 10 period is required for data transfer, leaving a significantly larger portion of the pixel period available for the charge sensitive pre-amplifier to acquire new data.
~ dditionally, multiple pipelined sample and hold circuits with correlated double sampling in accordance with the present invention can be interconnected via an array of switches for purposes of combining, or "binning," data from multiple charge sensitive pre-amplifiers, while providing the 15 CDS fùnction for the resulting composite data signal from the interconnected pre-amplifiers.
More specifically, in accordance with one embodiment of the present invention, a signal sampling circuit for performing correlated double sampling (~DS) of an input signal with a pipelined sample and hold architecture includes a capacitive input circuit, a differential amplifier, a pipelined sample and hold circuit and a capacitive feedback circuit. The capacitive input circuit 20 is configured to receive an input signal, which includes a desired signal component and an undesired signal component, and in accordance therewith provide a capacitively coupled input signal The differential amplifier is coupled to the capacitive input circuit, includes first and second input terminals and an output terminal, and is configured to receive the capacitively coupled input signal and a reference voltage via the first and second input terminals, respectively, and in accordance 25 therewith provide an amplified input signal via the output terminal. The pipelined sample and hold circuit is coupled to the difIèl en~ial arnplifier output terrninal and is configured to receive a plurality ~ of sarnpling control signals and in accordance therewith receive, sample and hold the amplified input signal and in accordance therewith provide first and second pluralities of time multiplexed input signal samples. Respective temporally ?1~cçnt ones of the first and second pluralities of time=
30 multiplexed input signal samples and temporally coincident ones of the first and second pluralities of time multiplexed input signal samples repl esell~ temporally ~ cPnt samples of the input signal.
W O 98/24092 PCT~US97121164 The capacitive fee~lharl~ circuit is coupled between the pipelined sample and hold circuit and the first di~e;lelllial amplifier input terminal and is configured to receive a feedback control signal and in accordance lh~lewiL}I receive the f~rst plurality oftime multiplexed input signal samples. The first and second pluralities of time multiplexed input signal samples include the desired signal component S and exclude the undesired signal component.
In accordance with another embodiment of the present invention, a signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a capacitive input circuit, a differential amplifier, a pipelined sample and hold circuit and a capacitive feedback circuit. The capacltive input circuit is configured to receive an 10 input signal, which includes a desired signal component and an undesired signal component, and in accordance therewith provide a capacitively coupled input signal. The differential amplifier is ~ coupled to the capacitive input circuit, includes first and second input terminals and an output terminal, and is configured to receive the capacitively coupled input signal and a reference voltage via the first and second input terminals, respectively, and in accordance therewith provide an 15 amplified input signal via the output terminal. The pipelined sample and hold circuit is coupled to the differential amplifier output terminal and is configured to receive one or more sampling control signals and in accordance therewith receive, sample and hold the amplified input signal and in accordance therewith provide a plurality of input signal samples and to time multiplex the plurality of input signal samples and in accordance therewith provide a first plurality of time multiplexed 20 input signal samples. Temporally coincident ones of the plurality of input signal samples and temporally adjacent ones of the first plurality of time multiplexed input signal samples represent temporally adjacent samples of the input signal. The capacitive switching feedback circuit is coupled between the pipelined sample and hold circuit and the first di~er~nlial amplifier input terminal and is configured to receive a plurality of feedb~rk control signals and the plurality of input 25 signal samples and in accordance therewith time multiplex the plurality of input signal samples and in accordance therewith provide a second plurality of time multiplexed input signal samples and to charge and discharge in accordance lhelewilh The first and second pluralities oftime mllltiplP.~d input signal samples include the desired signal component and exclude the undesired signal component.
These and other features and advantages of the present invention will be understood upon consideration ofthe following detailed description ofthe invention and the ~ccol,.p~.lying drawings.
-2 PCTrUS97/21164 ~RTEF DESCRIPTION OF T}l~ l~RAWINGS
Figure 1 is a schcrn~ti~ diagram of a pipelined sample and hold circuit with correlated double sampling in accordance with one embodiment of the present invention.
Figure 2 is a signal timing diagram for the switch control sigrlals of Figure 1.Figure 3 illustrates the relative timing of the input signals being sampled and held and outputted by the circuit of Figure 1.
Figure 4 illustrates how multiple pipelined sample and hold circuits with correlated double sampling can be interconnected for combining, or "binning," data from multiple charge sensitive pre-amplifiers.
DETAll,ED DESCRl~PTION O~ TE~E INVENTION
Referring to Figure 1, a pipelined sample and hold circuit with correlated double sarnpling in accordance with one embodiment of the present invention includes a dif~erential amplifier DA, a number of switches SWl-SW7, two shunt capacitors CHI, CH2, two buffer amplifiers ~1, A2 and a feedback integration capacitor Cc2, interconnected substantially as shown. The noninverting input of the diffèrential amplifier DA is tied to a dc reference voltage VREF, while the inverting input receives a signal which is the sum of the data input signal rNPUT received via a series coupling capacitor Cc~ and a feedback signal received via the feedback capacitor Cc2.
The input data signal INE~UT originates from a charge sensitive pre-amplifier (not shown) which receives pixel data which is read out from an array in serial forrn. Such pre-amplifier is reset between each pixel, thereby generating, in addition to the desired image inforrnation component, a noise component due to resetting of the pre-arnplifier immediately prior to the generating of each pixel signal. During such resetting of the pre-amplifier, switch SW7 is closed in accordance with a clamp control signal CLAMP to discharge the feedback capacitor CQ. ThiS results in the fee~lbacl~ loop between the output and inverting input of the differential amplifier DA to be closed, thereby creating a voltage follower circuit. This causes the output of the difrel elllial amplifier DA
to be equal to the input reference voltage VREF.
Following the resetting of the pre-amplifier, clamping switch SW7 is opened, thereby causing the reset noise to be captured on the input coupling r~paritor Ccl while allowing the output voltage W 098124092 PCT~US97/2116~
of the dirre~ lLial amplifier DA to follow the input signal at its inverting input Additionally, any offset associated with the resetting operation of the pre-amplifier has now also been removed.
In accordance with switch control signals s 1 -s4, one of the two sample and hold signal paths SH1, SH2 is selected for ~mpling the output of the differential amplifier DA, while the other path 5 is selected for holding the previously sampled signal level for buffering by its respective buffer amplifier Al/A2 and outputting viaits respective output switch SW3/SW4. For example, when sample and hold signal path SHl is sÇlecte~, switches SW2 and SW4 are closed and switches SW1 and SW3 are opened and the voltage across hold capacitor Cl~, tracks the output of the differential amplif er DA. At the end of the tracking time for sample and hold signal path SH1, s~vitches SW2 10 and SW4 are opened and switches SW1 and SW3 are closed, preferably in that order. At this point, the last value of the output of the differential amplifier DA, minus the pre-amplifier reset noise, is now stored on hold capacitor Cl~, for buffering by its buffer arnplifier Al and outputting via switch SW3. Meanwhile, the feedback loop through switches SW1 and SW5 is now closed, thereby allowing the voltage across hold capacitor C~2 to track the output of the differential amplifier DA.
The above-described clamping, tracking and sampling operation is repeated for the second sampling and hold signal path SH2. Hence, with the exception of those brief periods of time when the feedback capacitor Cc2 is discharged and the signal switches SWl-SW6 are transitioning bet~,veen their respective open and closed states, one of the hold capacitors Cll" C~l2 is tracking the input signal (minus its associated reset noise) while the other hold capacitor is providing the 20 immediately preceding sampled pixel inforrnation as the output signal OUTPUT. Accordingly, ma~cimum time is available for signal acquisition.
Referring to Figure 2, the relative timing of the above-discussed reset, clamp and s~vitch control signals can be better understood. As discussed above, during a reset of the pre-amplifier (interval tb-tC), the CLAMP signal is asserted to close switch SW7 (interval tb-td) to discharge the 25 feeclba~ ~ integration capacitor Cc2. Irnmediately preceding this (at time t"), switch control signal sl is de-asserted while, coincid~nt~lly with assertion of the CLAMP signal (time tb), switch control signals s2 and s4 are asserted and switch control signal s3 is de-asserted. Accordingly, switches SW2, SW4 and SW6 are closed and switches SW1, SW3 and SW5 are opened.
Subsequently, and immediately preceding the next reset of the pre-amplifier (time te), switch 30 control signal S2 is de-asserted and, coincidentally with the next resetting of the pre-amplifier, switch control signals S 1 and S3 are asserted and switch control signal S4 is de-asserted. E~ence, W O 98/24092 PCT~US97/21164 in accordance with the foregoing c~i~c~7e~ n~ sample and hold signal path SHl is used for tracking the input signal ~interval td-te) while sample and hold signal path SH2 provides the output signal (interval tb-tf). lmm~ tely thereafter (following time tf), the second sample and hold signal path SH2 follows the input signal, while the first sample and hold signal path SHl provides the output 5 signal.
Referring to Figure 3, the above-~ c l~.c~ sim--lt~neous sampling and holding by the multiple chzlnnel~ of the pipelined sample and hold circuit can be better understood. For example, during the time interval that the first sample and hold signal path SHl is sampling the input signal INPUT
(interval tb-t~), the second sample and hold signal path SH2 is in its hold mode and is providing the 10 output signal OUTPUT. Subsequently, during the time interval that the second sample and hold signal path SH2 is sampling the input signal INPUT (interval t~t,), the first sample and hold signal - path SHl is in its hold mode and is providing the output signal OUTPUT. Accordingly, temporally aclj~f nt signals within the multiplexed output signal OUTPUT represent temporally adjacent samples of the inp~t signal INPUT. Similarly, temporally coincident signals from the sample and 15 hold signal paths SHl, SE~2 also represent temporally adjacent samples ofthe input signal INPUT.
Switches SWl-SW7 have been represented in Figure I as single pole, single throw (SPST) switches. In a preferred embodiment, each ofthe switches SWl-SW7 is implemented in the form of a tr~n.cmi~ion gate, which consists of two pass transistors (a P-MOSFET and an N-MOSFET) with common drain terminal and common source terminal connections. However, it should be 20 understood that switches SWl-SW6 can be implemented in other than SPST form. For example, switches SWl and SW2 together can be implemented as a single pole, double throw (SPDT) switch with the pole connected to the output of the differential amplifier DA and one throw connected to each of the hold capacitors CHI, C~.
Similarly, switches SW3 and SW4 together can be implemented as a SPDT switch with the 25 pole connected to the output and each throw connected to an output of one of the buffering amplifiers Al, A2. Further similarly, switches SW5 and SW6 can be implemented as a SPDT
s~,vitch with the pole connected to c~pacitQr Cc2 and switch SW7 and each throw connected to an output of one ofthe buffer amplifiers Al, A2. Alternatively, with a~pl~,pliate timing ~ s~m~nt~
for their respective switch control signals SWl-SW4, each of these switch pairs SW1/SW2, 30 SW3/SW4, SWS/SW6 can also be impl~.m~nted in the form of a multiplexor.
_ CA 02244683 1998-07-28 W 098/24092 PCT~US97/21164 Referring to Figure 4, a number of pipelined sample and hold signals with correlated double circuits in accordance with the present invention can be interconnected via a network of switches SWA, SWB, SWC ... and SWAB, SWBC, SWCD ... to provide for combining, or "binning," of input signals A, B, C... from multiple pre-amplifiers. The serial input switches SW~, SWB, 5 SWC ... are used for disconnecting those sampling circuits which are to be disabled during the "binning" mode, while the sh~lnting input switches SWAB, SWBC, SWCD... are used for selectively interconnecting the input channels A, B, ... to the sampling circuit to be used in the binning mode. C~nr"~ tion of the pre-amplifier reset noise occurs as discussed above, but through one sampling circuit instead of multiple sampling circuits.
Accordingly, for example, for birming signals from two channels (A and B), switches SWA, SWB and SWAB would be closed and input signals A and B would be coupied into sampling circuit A via their respective input coupling capacitors Ccl~ and CClb, while switches SWB, SWC, SWBC and SWCD would be open. As should be evident, this binning technique can be extended to any number of channels.
Various other modifications and alterations in the structure and method of operation of this invention wiii be apparent to those skiiied in the art wit'nout depariing from the scope and spi' ,t of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly lirnited to such specific embodiments. It is intended that the following claims define the scope of the 20 present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.
WITEI CORl~LATED DOUBLE SAMPLlNG
FIELD OF T~E TNVI~NTION
The present invention relates to sample and hold circuits, and in particular, to pipelined sample and hold circuits with correlated double sampling.
5 BACKGROUND OF Tl~E TNVENT~ON
Sample and hold circuits play an important role in data acquisition systems, particularly in those systems in which the signals con~ining the data of interest are ~h~nging faster than the system can acquire and appropriately process the data.
For example, in large area, flat panel im~ging systems, such as im:~ging systems for medical - 10 and document im~ging applications based upon amorphous silicon, the image sensor is typically arranged as an array of pixels, each of which consists of a photosensitive element and a thin film transistor (TFT). In order to achieve im~ging frame rates suitable for video processing and display, all gate and data line connections for the sensor are brought out to the edge of the array for connection to an off-array control circuit cont~ining row selection and charge sensing circuitry.
15 For a high resolution array, many pixels are used for each data line, with the result being a high data readout rate in order to sample each of the pixels within the time constraints of the real time video display. Accordingly, while the data for each pixel must be sampled accurately, it must also be sampled quickly and held available for a sufficient period of time to allow the pixel data to be appropriately processed, stored, etc.
However, such image data signals, due to the manner in which they are generated, include, in addition to the image component, a noise component which is generated as a result of the image array sc~nning process. For example, the circuitry used to acquire the image data information from each pixel typically includes a charge sensitive pre-amplifier which must be reset between each pixel. This resetting of the charge sensitive pre-amplifier immediately prior to reading out the 25 charge from each pixel generates a significant, and undesirable, noise component which, if not ~limin~ted during the sample and hold process, will significantly distort and obscure the true image information corresponding to that pixel.
Accordingly, it would be desirable to have a sample and hold circuit which is capable of çlimin~ting the noise component from the signal to be sampled.
W O 98/~4092 PCT/US97/21164 . 2 SUMMARY OF T~E INVENTION
In accordance with the present invention, correlated double sampling (CDS) is provided in a pipelined sample and hold circuit arr.hitectl-re. Such a circuit can be used advantageously in multiple çh~nnel, charge sensitive readout circuits in which multiple data ch~nn~lc of a sensor are 5 each connected to a charge sensitive pre-amplifier. In such an application, the CDS elirninates the noise associated with resetting the charge sensitive pre-amplifier, while the sample and hold circuitry allows the data from a previous channel to be read out during sampling of the present channel. By using a pipelined sample and hold architecture, maxirnum data s~mpling tirne, or "line time," is available for reading out the sampled data. Hence, only a very small portion of each pixel 10 period is required for data transfer, leaving a significantly larger portion of the pixel period available for the charge sensitive pre-amplifier to acquire new data.
~ dditionally, multiple pipelined sample and hold circuits with correlated double sampling in accordance with the present invention can be interconnected via an array of switches for purposes of combining, or "binning," data from multiple charge sensitive pre-amplifiers, while providing the 15 CDS fùnction for the resulting composite data signal from the interconnected pre-amplifiers.
More specifically, in accordance with one embodiment of the present invention, a signal sampling circuit for performing correlated double sampling (~DS) of an input signal with a pipelined sample and hold architecture includes a capacitive input circuit, a differential amplifier, a pipelined sample and hold circuit and a capacitive feedback circuit. The capacitive input circuit 20 is configured to receive an input signal, which includes a desired signal component and an undesired signal component, and in accordance therewith provide a capacitively coupled input signal The differential amplifier is coupled to the capacitive input circuit, includes first and second input terminals and an output terminal, and is configured to receive the capacitively coupled input signal and a reference voltage via the first and second input terminals, respectively, and in accordance 25 therewith provide an amplified input signal via the output terminal. The pipelined sample and hold circuit is coupled to the difIèl en~ial arnplifier output terrninal and is configured to receive a plurality ~ of sarnpling control signals and in accordance therewith receive, sample and hold the amplified input signal and in accordance therewith provide first and second pluralities of time multiplexed input signal samples. Respective temporally ?1~cçnt ones of the first and second pluralities of time=
30 multiplexed input signal samples and temporally coincident ones of the first and second pluralities of time multiplexed input signal samples repl esell~ temporally ~ cPnt samples of the input signal.
W O 98/24092 PCT~US97121164 The capacitive fee~lharl~ circuit is coupled between the pipelined sample and hold circuit and the first di~e;lelllial amplifier input terminal and is configured to receive a feedback control signal and in accordance lh~lewiL}I receive the f~rst plurality oftime multiplexed input signal samples. The first and second pluralities of time multiplexed input signal samples include the desired signal component S and exclude the undesired signal component.
In accordance with another embodiment of the present invention, a signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a capacitive input circuit, a differential amplifier, a pipelined sample and hold circuit and a capacitive feedback circuit. The capacltive input circuit is configured to receive an 10 input signal, which includes a desired signal component and an undesired signal component, and in accordance therewith provide a capacitively coupled input signal. The differential amplifier is ~ coupled to the capacitive input circuit, includes first and second input terminals and an output terminal, and is configured to receive the capacitively coupled input signal and a reference voltage via the first and second input terminals, respectively, and in accordance therewith provide an 15 amplified input signal via the output terminal. The pipelined sample and hold circuit is coupled to the differential amplifier output terminal and is configured to receive one or more sampling control signals and in accordance therewith receive, sample and hold the amplified input signal and in accordance therewith provide a plurality of input signal samples and to time multiplex the plurality of input signal samples and in accordance therewith provide a first plurality of time multiplexed 20 input signal samples. Temporally coincident ones of the plurality of input signal samples and temporally adjacent ones of the first plurality of time multiplexed input signal samples represent temporally adjacent samples of the input signal. The capacitive switching feedback circuit is coupled between the pipelined sample and hold circuit and the first di~er~nlial amplifier input terminal and is configured to receive a plurality of feedb~rk control signals and the plurality of input 25 signal samples and in accordance therewith time multiplex the plurality of input signal samples and in accordance therewith provide a second plurality of time multiplexed input signal samples and to charge and discharge in accordance lhelewilh The first and second pluralities oftime mllltiplP.~d input signal samples include the desired signal component and exclude the undesired signal component.
These and other features and advantages of the present invention will be understood upon consideration ofthe following detailed description ofthe invention and the ~ccol,.p~.lying drawings.
-2 PCTrUS97/21164 ~RTEF DESCRIPTION OF T}l~ l~RAWINGS
Figure 1 is a schcrn~ti~ diagram of a pipelined sample and hold circuit with correlated double sampling in accordance with one embodiment of the present invention.
Figure 2 is a signal timing diagram for the switch control sigrlals of Figure 1.Figure 3 illustrates the relative timing of the input signals being sampled and held and outputted by the circuit of Figure 1.
Figure 4 illustrates how multiple pipelined sample and hold circuits with correlated double sampling can be interconnected for combining, or "binning," data from multiple charge sensitive pre-amplifiers.
DETAll,ED DESCRl~PTION O~ TE~E INVENTION
Referring to Figure 1, a pipelined sample and hold circuit with correlated double sarnpling in accordance with one embodiment of the present invention includes a dif~erential amplifier DA, a number of switches SWl-SW7, two shunt capacitors CHI, CH2, two buffer amplifiers ~1, A2 and a feedback integration capacitor Cc2, interconnected substantially as shown. The noninverting input of the diffèrential amplifier DA is tied to a dc reference voltage VREF, while the inverting input receives a signal which is the sum of the data input signal rNPUT received via a series coupling capacitor Cc~ and a feedback signal received via the feedback capacitor Cc2.
The input data signal INE~UT originates from a charge sensitive pre-amplifier (not shown) which receives pixel data which is read out from an array in serial forrn. Such pre-amplifier is reset between each pixel, thereby generating, in addition to the desired image inforrnation component, a noise component due to resetting of the pre-arnplifier immediately prior to the generating of each pixel signal. During such resetting of the pre-amplifier, switch SW7 is closed in accordance with a clamp control signal CLAMP to discharge the feedback capacitor CQ. ThiS results in the fee~lbacl~ loop between the output and inverting input of the differential amplifier DA to be closed, thereby creating a voltage follower circuit. This causes the output of the difrel elllial amplifier DA
to be equal to the input reference voltage VREF.
Following the resetting of the pre-amplifier, clamping switch SW7 is opened, thereby causing the reset noise to be captured on the input coupling r~paritor Ccl while allowing the output voltage W 098124092 PCT~US97/2116~
of the dirre~ lLial amplifier DA to follow the input signal at its inverting input Additionally, any offset associated with the resetting operation of the pre-amplifier has now also been removed.
In accordance with switch control signals s 1 -s4, one of the two sample and hold signal paths SH1, SH2 is selected for ~mpling the output of the differential amplifier DA, while the other path 5 is selected for holding the previously sampled signal level for buffering by its respective buffer amplifier Al/A2 and outputting viaits respective output switch SW3/SW4. For example, when sample and hold signal path SHl is sÇlecte~, switches SW2 and SW4 are closed and switches SW1 and SW3 are opened and the voltage across hold capacitor Cl~, tracks the output of the differential amplif er DA. At the end of the tracking time for sample and hold signal path SH1, s~vitches SW2 10 and SW4 are opened and switches SW1 and SW3 are closed, preferably in that order. At this point, the last value of the output of the differential amplifier DA, minus the pre-amplifier reset noise, is now stored on hold capacitor Cl~, for buffering by its buffer arnplifier Al and outputting via switch SW3. Meanwhile, the feedback loop through switches SW1 and SW5 is now closed, thereby allowing the voltage across hold capacitor C~2 to track the output of the differential amplifier DA.
The above-described clamping, tracking and sampling operation is repeated for the second sampling and hold signal path SH2. Hence, with the exception of those brief periods of time when the feedback capacitor Cc2 is discharged and the signal switches SWl-SW6 are transitioning bet~,veen their respective open and closed states, one of the hold capacitors Cll" C~l2 is tracking the input signal (minus its associated reset noise) while the other hold capacitor is providing the 20 immediately preceding sampled pixel inforrnation as the output signal OUTPUT. Accordingly, ma~cimum time is available for signal acquisition.
Referring to Figure 2, the relative timing of the above-discussed reset, clamp and s~vitch control signals can be better understood. As discussed above, during a reset of the pre-amplifier (interval tb-tC), the CLAMP signal is asserted to close switch SW7 (interval tb-td) to discharge the 25 feeclba~ ~ integration capacitor Cc2. Irnmediately preceding this (at time t"), switch control signal sl is de-asserted while, coincid~nt~lly with assertion of the CLAMP signal (time tb), switch control signals s2 and s4 are asserted and switch control signal s3 is de-asserted. Accordingly, switches SW2, SW4 and SW6 are closed and switches SW1, SW3 and SW5 are opened.
Subsequently, and immediately preceding the next reset of the pre-amplifier (time te), switch 30 control signal S2 is de-asserted and, coincidentally with the next resetting of the pre-amplifier, switch control signals S 1 and S3 are asserted and switch control signal S4 is de-asserted. E~ence, W O 98/24092 PCT~US97/21164 in accordance with the foregoing c~i~c~7e~ n~ sample and hold signal path SHl is used for tracking the input signal ~interval td-te) while sample and hold signal path SH2 provides the output signal (interval tb-tf). lmm~ tely thereafter (following time tf), the second sample and hold signal path SH2 follows the input signal, while the first sample and hold signal path SHl provides the output 5 signal.
Referring to Figure 3, the above-~ c l~.c~ sim--lt~neous sampling and holding by the multiple chzlnnel~ of the pipelined sample and hold circuit can be better understood. For example, during the time interval that the first sample and hold signal path SHl is sampling the input signal INPUT
(interval tb-t~), the second sample and hold signal path SH2 is in its hold mode and is providing the 10 output signal OUTPUT. Subsequently, during the time interval that the second sample and hold signal path SH2 is sampling the input signal INPUT (interval t~t,), the first sample and hold signal - path SHl is in its hold mode and is providing the output signal OUTPUT. Accordingly, temporally aclj~f nt signals within the multiplexed output signal OUTPUT represent temporally adjacent samples of the inp~t signal INPUT. Similarly, temporally coincident signals from the sample and 15 hold signal paths SHl, SE~2 also represent temporally adjacent samples ofthe input signal INPUT.
Switches SWl-SW7 have been represented in Figure I as single pole, single throw (SPST) switches. In a preferred embodiment, each ofthe switches SWl-SW7 is implemented in the form of a tr~n.cmi~ion gate, which consists of two pass transistors (a P-MOSFET and an N-MOSFET) with common drain terminal and common source terminal connections. However, it should be 20 understood that switches SWl-SW6 can be implemented in other than SPST form. For example, switches SWl and SW2 together can be implemented as a single pole, double throw (SPDT) switch with the pole connected to the output of the differential amplifier DA and one throw connected to each of the hold capacitors CHI, C~.
Similarly, switches SW3 and SW4 together can be implemented as a SPDT switch with the 25 pole connected to the output and each throw connected to an output of one of the buffering amplifiers Al, A2. Further similarly, switches SW5 and SW6 can be implemented as a SPDT
s~,vitch with the pole connected to c~pacitQr Cc2 and switch SW7 and each throw connected to an output of one ofthe buffer amplifiers Al, A2. Alternatively, with a~pl~,pliate timing ~ s~m~nt~
for their respective switch control signals SWl-SW4, each of these switch pairs SW1/SW2, 30 SW3/SW4, SWS/SW6 can also be impl~.m~nted in the form of a multiplexor.
_ CA 02244683 1998-07-28 W 098/24092 PCT~US97/21164 Referring to Figure 4, a number of pipelined sample and hold signals with correlated double circuits in accordance with the present invention can be interconnected via a network of switches SWA, SWB, SWC ... and SWAB, SWBC, SWCD ... to provide for combining, or "binning," of input signals A, B, C... from multiple pre-amplifiers. The serial input switches SW~, SWB, 5 SWC ... are used for disconnecting those sampling circuits which are to be disabled during the "binning" mode, while the sh~lnting input switches SWAB, SWBC, SWCD... are used for selectively interconnecting the input channels A, B, ... to the sampling circuit to be used in the binning mode. C~nr"~ tion of the pre-amplifier reset noise occurs as discussed above, but through one sampling circuit instead of multiple sampling circuits.
Accordingly, for example, for birming signals from two channels (A and B), switches SWA, SWB and SWAB would be closed and input signals A and B would be coupied into sampling circuit A via their respective input coupling capacitors Ccl~ and CClb, while switches SWB, SWC, SWBC and SWCD would be open. As should be evident, this binning technique can be extended to any number of channels.
Various other modifications and alterations in the structure and method of operation of this invention wiii be apparent to those skiiied in the art wit'nout depariing from the scope and spi' ,t of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly lirnited to such specific embodiments. It is intended that the following claims define the scope of the 20 present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.
Claims (20)
1. An apparatus including a signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture, said signal sampling circuit comprising:
a capacitive input circuit configured to receive an input signal an ~n accordance therewith provide a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
a differential amplifier, coupled to said capacitive input circuit and including first and second input terminals and an output terminal, configured to receive said capacitively coupled input signal and a reference voltage via said first and second differential amplifier input terminals, respectively, and in accordance therewith provide an amplified input signal via said differential amplifier output terminal;
a pipelined sample and hold circuit, coupled to said differential amplifier output terminal, configured to receive a plurality of sampling control signals and in accordance therewith receive, sample and hold said amplified input signal and in accordance therewith provide first and second pluralities of time multiplexed input signal samples, wherein respective temporally adjacent ones of said first and second pluralities of time multiplexed input signal samples and temporally coincident ones of said first and second pluralities of time multiplexed input signal samples represent temporally adjacent samples of said input signal;
and a capacitive feedback circuit, coupled between said pipelined sample and hold circuit and said first differential amplifier input terminal, configured to receive a feedback control signal and in accordance therewith receive said first plurality of time multiplexed input signal samples, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
a capacitive input circuit configured to receive an input signal an ~n accordance therewith provide a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
a differential amplifier, coupled to said capacitive input circuit and including first and second input terminals and an output terminal, configured to receive said capacitively coupled input signal and a reference voltage via said first and second differential amplifier input terminals, respectively, and in accordance therewith provide an amplified input signal via said differential amplifier output terminal;
a pipelined sample and hold circuit, coupled to said differential amplifier output terminal, configured to receive a plurality of sampling control signals and in accordance therewith receive, sample and hold said amplified input signal and in accordance therewith provide first and second pluralities of time multiplexed input signal samples, wherein respective temporally adjacent ones of said first and second pluralities of time multiplexed input signal samples and temporally coincident ones of said first and second pluralities of time multiplexed input signal samples represent temporally adjacent samples of said input signal;
and a capacitive feedback circuit, coupled between said pipelined sample and hold circuit and said first differential amplifier input terminal, configured to receive a feedback control signal and in accordance therewith receive said first plurality of time multiplexed input signal samples, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
2. The apparatus of claim 1, wherein:
said first and second input terminals of said differential amplifier comprise inverting and noninverting input terminals of said differential amplifier, respectively; and said differential amplifier, said pipelined sample and hold circuit and said capacitive feedback circuit together comprise a time multiplexed integrating amplifier circuit.
said first and second input terminals of said differential amplifier comprise inverting and noninverting input terminals of said differential amplifier, respectively; and said differential amplifier, said pipelined sample and hold circuit and said capacitive feedback circuit together comprise a time multiplexed integrating amplifier circuit.
3. The apparatus of claim 1, wherein said pipelined sample and hold circuit comprises:
a first signal selector circuit configured to receive a first portion of said plurality of sampling control signals and in accordance therewith receive and sample said amplified input signal and in accordance therewith provide a plurality of time multiplexed samples of said amplified input signal;
a plurality of shunt capacitors, coupled to said first signal selector circuit, configured to receive said plurality of time multiplexed samples of said amplified input signal and in accordance therewith provide a plurality of held samples of said amplified input signal; and a second signal selector circuit, coupled to said plurality of shunt capacitors, configured to receive a second portion of said plurality of sampling control signals and in accordance therewith receive and select among said held samples of said amplified input signal and in accordance therewith provide said first and second pluralities of time multiplexed input signal samples.
a first signal selector circuit configured to receive a first portion of said plurality of sampling control signals and in accordance therewith receive and sample said amplified input signal and in accordance therewith provide a plurality of time multiplexed samples of said amplified input signal;
a plurality of shunt capacitors, coupled to said first signal selector circuit, configured to receive said plurality of time multiplexed samples of said amplified input signal and in accordance therewith provide a plurality of held samples of said amplified input signal; and a second signal selector circuit, coupled to said plurality of shunt capacitors, configured to receive a second portion of said plurality of sampling control signals and in accordance therewith receive and select among said held samples of said amplified input signal and in accordance therewith provide said first and second pluralities of time multiplexed input signal samples.
4. The apparatus of claim 3, wherein said first and second signal selector circuits comprise first and second pluralities of pass transistors.
5. The apparatus of claim 1, wherein said capacitive feedback circuit comprises:a capacitor configured to alternately charge and discharge, wherein said capacitor charging is in accordance with said first plurality of time multiplexed input signal samples; and a switch, coupled across said capacitor, configured to receive said feedback control signal and in accordance therewith alternately allow said charging and cause said discharging of said capacitor.
6. An apparatus including a signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture, said signal sampling circuit comprising:
a capacitive input circuit configured to receive an input signal and in accordance therewith provide a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
a differential amplifier, coupled to said capacitive input circuit and including first and second input terminals and an output terminal, configured to receive said capacitively coupled input signal and a reference voltage via said first and second differential amplifier input terminals, respectively, and in accordance therewith provide an amplified input signal via said differential amplifier output terminal;
a pipelined sample and hold circuit, coupled to said differential amplifier output terminal, configured to receive one or more sampling control signals and in accordance therewith receive, sample and hold said amplified input signal and in accordance therewith provide a plurality of input signal samples and to time multiplex said plurality of input signal samples and in accordance therewith provide a first plurality of time multiplexed input signal samples, wherein temporally coincident ones of said plurality of input signal samples and temporally adjacent ones of said first plurality of time multiplexed input signal samples represent temporally adjacent samples of said input signal; and a capacitive switching feedback circuit, coupled between said pipelined sample and hold circuit and said first differential amplifier input terminal, configured to receive a plurality of feedback control signals and said plurality of input signal samples and in accordance therewith time multiplex said plurality of input signal samples and in accordance therewith provide a second plurality of time multiplexed input signal samples and to charge and discharge in accordance therewith, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
a capacitive input circuit configured to receive an input signal and in accordance therewith provide a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
a differential amplifier, coupled to said capacitive input circuit and including first and second input terminals and an output terminal, configured to receive said capacitively coupled input signal and a reference voltage via said first and second differential amplifier input terminals, respectively, and in accordance therewith provide an amplified input signal via said differential amplifier output terminal;
a pipelined sample and hold circuit, coupled to said differential amplifier output terminal, configured to receive one or more sampling control signals and in accordance therewith receive, sample and hold said amplified input signal and in accordance therewith provide a plurality of input signal samples and to time multiplex said plurality of input signal samples and in accordance therewith provide a first plurality of time multiplexed input signal samples, wherein temporally coincident ones of said plurality of input signal samples and temporally adjacent ones of said first plurality of time multiplexed input signal samples represent temporally adjacent samples of said input signal; and a capacitive switching feedback circuit, coupled between said pipelined sample and hold circuit and said first differential amplifier input terminal, configured to receive a plurality of feedback control signals and said plurality of input signal samples and in accordance therewith time multiplex said plurality of input signal samples and in accordance therewith provide a second plurality of time multiplexed input signal samples and to charge and discharge in accordance therewith, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
7. The apparatus of claim 6, wherein:
said first and second input terminals of said differential amplifier comprise inverting and noninverting input terminals of said differential amplifier, respectively; and said differential amplifier, said pipelined sample and hold circuit and said capacitive switching feedback circuit together comprise a time multiplexed integrating amplifier circuit.
said first and second input terminals of said differential amplifier comprise inverting and noninverting input terminals of said differential amplifier, respectively; and said differential amplifier, said pipelined sample and hold circuit and said capacitive switching feedback circuit together comprise a time multiplexed integrating amplifier circuit.
8. The apparatus of claim 6, wherein said pipelined sample and hold circuit comprises:
a first signal selector circuit configured to receive a first portion of said one or more sampling control signals and in accordance therewith receive and sample said amplified input signal and in accordance therewith provide a plurality of time multiplexed samples of said amplified input signal;
a plurality of shunt capacitors, coupled to said first signal selector circuit, configured to receive said plurality of time multiplexed samples of said amplified input signal and in accordance therewith provide a plurality of held samples of said amplified input signal; and a second signal selector circuit, coupled to said plurality of shunt capacitors, configured to receive a second portion of said one or more sampling control signals and in accordance therewith receive and select among said held samples of said amplified input signal and in accordance therewith provide said first plurality of time multiplexed input signal samples.
a first signal selector circuit configured to receive a first portion of said one or more sampling control signals and in accordance therewith receive and sample said amplified input signal and in accordance therewith provide a plurality of time multiplexed samples of said amplified input signal;
a plurality of shunt capacitors, coupled to said first signal selector circuit, configured to receive said plurality of time multiplexed samples of said amplified input signal and in accordance therewith provide a plurality of held samples of said amplified input signal; and a second signal selector circuit, coupled to said plurality of shunt capacitors, configured to receive a second portion of said one or more sampling control signals and in accordance therewith receive and select among said held samples of said amplified input signal and in accordance therewith provide said first plurality of time multiplexed input signal samples.
9. The apparatus of claim 8, wherein said first and second signal selector circuits comprise first and second pluralities of pass transistors.
10. The apparatus of claim 6, wherein said capacitive switching feedback circuit comprises:
a third signal selector circuit configured to receive a first portion of said plurality of feedback control signals and in accordance therewith receive and time multiplex said plurality of input signal samples and in accordance therewith provide said second plurality of time multiplexed input signal samples;
a capacitor, coupled to said third signal selector circuit, configured to receive said second plurality of time multiplexed input signal samples and alternately charge and discharge, wherein said capacitor charging is in accordance with said second plurality of time multiplexed input signal samples; and a switch, coupled across said capacitor, configured to receive a second portion of said plurality of feedback control signals and in accordance therewith alternately allow said charging and cause said discharging of said capacitor.
a third signal selector circuit configured to receive a first portion of said plurality of feedback control signals and in accordance therewith receive and time multiplex said plurality of input signal samples and in accordance therewith provide said second plurality of time multiplexed input signal samples;
a capacitor, coupled to said third signal selector circuit, configured to receive said second plurality of time multiplexed input signal samples and alternately charge and discharge, wherein said capacitor charging is in accordance with said second plurality of time multiplexed input signal samples; and a switch, coupled across said capacitor, configured to receive a second portion of said plurality of feedback control signals and in accordance therewith alternately allow said charging and cause said discharging of said capacitor.
11. The method of claim 10, wherein said third signal selector circuit comprises a plurality of pass transistors.
12. A method of performing correlated double sampling (CDS) of an input signal with pipelined sampling and holding, said method comprising the steps of:
(a) receiving and capacitively coupling an input signal and in accordance therewith generating a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
(b) receiving said capacitively coupled input signal and a reference voltage via first and second input terminals, respectively, of a differential amplifier and in accordance therewith generating an amplified input signal via an output terminal of said differential amplifier;
(c) receiving a plurality of sampling control signals and in accordance therewith sampling and holding said amplified input signal and in accordance therewith generating first and second pluralities of time multiplexed input signal samples, wherein respective temporally adjacent ones of said first and second pluralities of time multiplexed input signal samples and temporally coincident ones of said first and second pluralities of time multiplexed input signal samples represent temporally adjacent samples of said input signal; and (d) receiving a feedback control signal and in accordance therewith capacitively coupling said first plurality of time multiplexed input signal samples to said first differential amplifier input terminal, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
(a) receiving and capacitively coupling an input signal and in accordance therewith generating a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
(b) receiving said capacitively coupled input signal and a reference voltage via first and second input terminals, respectively, of a differential amplifier and in accordance therewith generating an amplified input signal via an output terminal of said differential amplifier;
(c) receiving a plurality of sampling control signals and in accordance therewith sampling and holding said amplified input signal and in accordance therewith generating first and second pluralities of time multiplexed input signal samples, wherein respective temporally adjacent ones of said first and second pluralities of time multiplexed input signal samples and temporally coincident ones of said first and second pluralities of time multiplexed input signal samples represent temporally adjacent samples of said input signal; and (d) receiving a feedback control signal and in accordance therewith capacitively coupling said first plurality of time multiplexed input signal samples to said first differential amplifier input terminal, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
13. The method claim 12, wherein said steps (b), (c) and (d) together comprise a method of performing a time multiplexed integration of said input signal.
14. The method of claim 12, wherein said step (c) comprises:
receiving a first portion of said plurality of sampling control signals and in accordance therewith sampling said amplified input signal and in accordance therewith generating a plurality of time multiplexed samples of said amplified input signal;
capacitively holding said plurality of time multiplexed samples of said amplified input signal and in accordance therewith generating a plurality of held samples of said amplified input signal; and receiving a second portion of said plurality of sampling control signals and in accordance therewith selecting among said held samples of said amplified input signal and in accordance therewith generating said first and second pluralities of time multiplexed input signal samples.
receiving a first portion of said plurality of sampling control signals and in accordance therewith sampling said amplified input signal and in accordance therewith generating a plurality of time multiplexed samples of said amplified input signal;
capacitively holding said plurality of time multiplexed samples of said amplified input signal and in accordance therewith generating a plurality of held samples of said amplified input signal; and receiving a second portion of said plurality of sampling control signals and in accordance therewith selecting among said held samples of said amplified input signal and in accordance therewith generating said first and second pluralities of time multiplexed input signal samples.
15. The method of claim 12, wherein said step (d) comprises:
charging a capacitor in accordance with said first plurality of time multiplexed input signal samples; and discharging said capacitor in accordance with said feedback control signal.
charging a capacitor in accordance with said first plurality of time multiplexed input signal samples; and discharging said capacitor in accordance with said feedback control signal.
16. A method of performing correlated double sampling (CDS) of an input signal with pipelined sampling and holding, said method comprising the steps of:
(a) receiving and capacitively coupling an input signal and in accordance therewith generating a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
(b) receiving said capacitively coupled input signal and a reference voltage via first and second input terminals, respectively, of a differential amplifier and in accordance therewith generating an amplified input signal via an output terminal of said differential amplifier;
(c) receiving one or more sampling control signals and in accordance therewith sampling and holding said amplified input signal and in accordance therewith generating a plurality of input signal samples, wherein temporally coincident ones of said plurality of input signal samples represent temporally adjacent samples of said input signal;
(d) time multiplexing said plurality of input signal samples and in accordance therewith generating a first plurality of time multiplexed input signal samples, wherein temporally adjacent ones of said first plurality of time multiplexed input signal samples represent temporally adjacent samples of said input signal; and (e) receiving a first portion of a plurality of feedback control signals and in accordance therewith time multiplexing said plurality of input signal samples and in accordance therewith generating a second plurality of time multiplexed input signal samples; and (f) receiving a second portion of said plurality of feedback control signals and in accordance therewith capacitively coupling said second plurality of time multiplexed input signal samples to said first differential amplifier input terminal, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
(a) receiving and capacitively coupling an input signal and in accordance therewith generating a capacitively coupled input signal, wherein said input signal includes a desired signal component and an undesired signal component;
(b) receiving said capacitively coupled input signal and a reference voltage via first and second input terminals, respectively, of a differential amplifier and in accordance therewith generating an amplified input signal via an output terminal of said differential amplifier;
(c) receiving one or more sampling control signals and in accordance therewith sampling and holding said amplified input signal and in accordance therewith generating a plurality of input signal samples, wherein temporally coincident ones of said plurality of input signal samples represent temporally adjacent samples of said input signal;
(d) time multiplexing said plurality of input signal samples and in accordance therewith generating a first plurality of time multiplexed input signal samples, wherein temporally adjacent ones of said first plurality of time multiplexed input signal samples represent temporally adjacent samples of said input signal; and (e) receiving a first portion of a plurality of feedback control signals and in accordance therewith time multiplexing said plurality of input signal samples and in accordance therewith generating a second plurality of time multiplexed input signal samples; and (f) receiving a second portion of said plurality of feedback control signals and in accordance therewith capacitively coupling said second plurality of time multiplexed input signal samples to said first differential amplifier input terminal, wherein said first and second pluralities of time multiplexed input signal samples include said desired signal component and exclude said undesired signal component.
17. The method of claim 16, wherein said steps (b), (c), (d), (e) and (f) together comprise a method of performing a time multiplexed integration of said input signal
18. The method of claim 16, wherein said step (c) comprises:
receiving a first portion of said one or more sampling control signals and in accordance therewith sampling said amplified input signal and in accordance therewith generating a plurality of time multiplexed samples of said amplified input signal; and capacitively holding said plurality of time multiplexed samples of said amplified input signal and in accordance therewith generating a plurality of held samples of said amplified input signal.
receiving a first portion of said one or more sampling control signals and in accordance therewith sampling said amplified input signal and in accordance therewith generating a plurality of time multiplexed samples of said amplified input signal; and capacitively holding said plurality of time multiplexed samples of said amplified input signal and in accordance therewith generating a plurality of held samples of said amplified input signal.
19. The method of claim 18, wherein said step (d) comprises:
receiving a second portion of said one or more sampling control signals and in accordance therewith selecting among said held samples of said amplified input signal and in accordance therewith generating said first plurality of time multiplexed input signal samples.
receiving a second portion of said one or more sampling control signals and in accordance therewith selecting among said held samples of said amplified input signal and in accordance therewith generating said first plurality of time multiplexed input signal samples.
20. The method of claim 16, wherein said step (f) comprises:
charging a capacitor in accordance with said second plurality of time multiplexed input signal samples; and discharging said capacitor in accordance with said second portion of said plurality of feedback control signals.
charging a capacitor in accordance with said second plurality of time multiplexed input signal samples; and discharging said capacitor in accordance with said second portion of said plurality of feedback control signals.
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| US08/758,536 US5872470A (en) | 1996-11-29 | 1996-11-29 | Pipelined sample and hold circuit with correlated double sampling |
| US08/758,536 | 1996-11-29 | ||
| PCT/US1997/021164 WO1998024092A1 (en) | 1996-11-29 | 1997-11-19 | Pipelined sample and hold circuit with correlated double sampling |
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| CA2244683C true CA2244683C (en) | 2002-04-02 |
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| US6744912B2 (en) | 1996-11-29 | 2004-06-01 | Varian Medical Systems Technologies, Inc. | Multiple mode digital X-ray imaging system |
| US5970115A (en) | 1996-11-29 | 1999-10-19 | Varian Medical Systems, Inc. | Multiple mode digital X-ray imaging system |
| EP0928103A3 (en) * | 1997-12-31 | 2000-08-02 | Texas Instruments Incorporated | CMOS imaging sensors |
| US6847399B1 (en) | 1998-03-23 | 2005-01-25 | Micron Technology, Inc. | Increasing readout speed in CMOS APS sensors through block readout |
| US6069502A (en) * | 1998-04-06 | 2000-05-30 | Intersil Corporation | Sample-and-hold circuit having reduced subthreshold conduction effects and related methods |
| US6163204A (en) * | 1998-12-01 | 2000-12-19 | Peco Ii, Inc. | Fast AC sensor for detecting power outages |
| JP3762604B2 (en) | 1999-03-30 | 2006-04-05 | シャープ株式会社 | Amplification type solid-state imaging device |
| US6433632B1 (en) * | 1999-06-11 | 2002-08-13 | Analog Devices, Inc. | Correlated double sampling circuit with op amp |
| CA2350416A1 (en) * | 2000-12-20 | 2002-06-20 | Symagery Microsystems Inc. | Image sensor with correlated double sampling technique using switched-capacitor technology |
| US6529049B2 (en) * | 2001-05-10 | 2003-03-04 | National Semiconductor Corporation | Pre-charged sample and hold |
| US6486808B1 (en) | 2001-10-16 | 2002-11-26 | Varian Medical Systems | Data signal amplifier with automatically controllable dynamic signal range |
| DE10219327A1 (en) * | 2002-04-30 | 2003-11-20 | Infineon Technologies Ag | Integrated circuit with a sample and hold device |
| US7170041B2 (en) * | 2002-07-17 | 2007-01-30 | Xerox Corporation | Pixel circuitry for imaging system |
| US7196577B2 (en) * | 2003-10-14 | 2007-03-27 | Analog Devices, Inc. | Amplifier with capacitor selection |
| US7095028B2 (en) * | 2003-10-15 | 2006-08-22 | Varian Medical Systems | Multi-slice flat panel computed tomography |
| US7589326B2 (en) * | 2003-10-15 | 2009-09-15 | Varian Medical Systems Technologies, Inc. | Systems and methods for image acquisition |
| US7113116B2 (en) * | 2005-01-26 | 2006-09-26 | Analog Devices, Inc. | Sample and hold apparatus |
| CN100433197C (en) * | 2005-03-17 | 2008-11-12 | 北京思比科微电子技术有限公司 | Low noisc relative double-sampling circuit |
| TWI379515B (en) * | 2008-11-06 | 2012-12-11 | Novatek Microelectronics Corp | Correlated double sampling circuit |
| DE102010035811B4 (en) | 2010-08-30 | 2024-01-25 | Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg | Image sensor and method for reading an image sensor |
| US8378717B1 (en) * | 2011-11-14 | 2013-02-19 | National Taipei University Of Technology | High-speed BiCMOS double sampling track-and-hold amplifier circuit |
| DE102011120099A1 (en) | 2011-12-02 | 2013-06-06 | Arnold & Richter Cine Technik Gmbh & Co. Betriebs Kg | Image sensor and method for reading an image sensor |
| EP2841892B1 (en) | 2012-04-24 | 2020-07-08 | Siemens Healthcare Diagnostics Inc. | Multi-channel light measurement methods, systems, and apparatus having reduced signal-to-noise ratio |
| TWI646782B (en) * | 2014-04-11 | 2019-01-01 | 日商半導體能源研究所股份有限公司 | Holding circuit, driving method of holding circuit, and semiconductor device including holding circuit |
| US10809792B2 (en) * | 2018-08-16 | 2020-10-20 | Analog Devices, Inc. | Correlated double sampling amplifier for low power |
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| US4585956A (en) * | 1982-09-29 | 1986-04-29 | At&T Bell Laboratories | Switched capacitor feedback sample-and-hold circuit |
| JPS6276099A (en) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | Sample-and-hold circuit |
| US4804863A (en) * | 1986-11-12 | 1989-02-14 | Crystal Semiconductor Corporation | Method and circuitry for generating reference voltages |
| US5159341A (en) * | 1991-03-12 | 1992-10-27 | Analog Devices, Inc. | Two phase sampling for a delta sigma modulator |
| US5363055A (en) * | 1993-03-15 | 1994-11-08 | General Electric Company | Photodiode preamplifier with programmable gain amplification |
| US5331222A (en) * | 1993-04-29 | 1994-07-19 | University Of Maryland | Cochlear filter bank with switched-capacitor circuits |
| JP2561040B2 (en) * | 1994-11-28 | 1996-12-04 | 日本電気株式会社 | Capacitance sensor capacitance change detection circuit and detection method thereof |
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- 1997-11-19 EP EP97949488A patent/EP0882295B1/en not_active Expired - Lifetime
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| CA2244683A1 (en) | 1998-06-04 |
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| JP2000505229A (en) | 2000-04-25 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |