CA2252407C - Flexible integrated circuit package - Google Patents

Flexible integrated circuit package Download PDF

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Publication number
CA2252407C
CA2252407C CA002252407A CA2252407A CA2252407C CA 2252407 C CA2252407 C CA 2252407C CA 002252407 A CA002252407 A CA 002252407A CA 2252407 A CA2252407 A CA 2252407A CA 2252407 C CA2252407 C CA 2252407C
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Canada
Prior art keywords
integrated circuit
molded body
circuit package
tape film
package according
Prior art date
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Expired - Lifetime
Application number
CA002252407A
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French (fr)
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CA2252407A1 (en
Inventor
Bill Tempest Davies
Mark Roy Harris
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Breconridge Ltd
Original Assignee
BRECONRIDGE MANUFACTURING SOLUTIONS Corp
Nortel Networks Corp
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Publication of CA2252407A1 publication Critical patent/CA2252407A1/en
Application granted granted Critical
Publication of CA2252407C publication Critical patent/CA2252407C/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

A flexible integrated circuit package for mounting on a substrate is disclosed. The package consists of a tape film having layers of dielectric and conductive material, a semiconductor die and an array of conductive leads. A molded body covers the die, and absorbs the majority of the pressure applied when compressing the package between a heatsink and a printed-circuit board (PCB). Rigid removable support material surrounds the molded body to keep the package flat while it is being mounted to the PCB. The support material is removed after soldering of the package to the PCB. The invention permits the package to be tightly compressed between a heatsink and a substrate without causing degradation of the conductive connections. Reliability of the connections is further increased since the tape film is flexible enough to accommodate bending of the substrate to which the package is connected.

Description

FLEXIBLE INTEGRATED CIRCUIT PACKAGE
Field of the Invention This invention relates to integrated circuit packages in general, and specifically to integrated circuit packages designed to be clamped between a heatsink and a substrate such as a printed circuit board.
Background of the Invention In the manufacture of semiconductor devices, an important aspect is the production of integrated circuit (IC) packages so that heat generated by the package can be dissipated efficiently. Another important aspect is the ability to mount a large number of conductive leads onto the package without decreasing its reliability.
A package will generally have an upper part which dissipates a majority of the heat generated and a lower part consisting of an array of conductive leads for connection to a substrate such as a printed circuit board (PCB), usually of larger area. A conventional approach in assisting the efficient dissipation of heat is to lay a piece of thermally conductive material, known in the art as a heatsink, onto the upper part of the package and clamp it to the substrate underneath the package. The efficiency with which heat is removed from the package, known as the thermal performance, is directly proportional to the pressure applied at the heatsink-package interface, and therefore a desirable arrangement will require the application of substantial pressure at this interface. Since the package is compressed between the heatsink and the substrate, pressure will also be applied to the interface where the package and substrate meet.
Generally, the heatsink and the upper part of the package are made of robust material such that a substantially large amount of pressure may be applied without causing damage to the interfacing components. However, despite any robustness in the substrate material, the conductive leads at the package-substrate junction cannot withstand a highly compressive load without degrading the connection between the leads and the substrate. The conductive leads of a more rigid, conventional package also wear out due to twisting and bending of the printed circuit board substrate during handling and operation.
Among the relevant prior art is a so-called Area Array Tape Automated Bonding, or ATAB, package developed by IBM
Corporation. It consists of a semiconductor die mounted on a tape film comprising several layers each of conductive (copper) and polyimide dielectric (UpilexTM) material. Circular electrical vias are mechanically punched in the tape film.
Electrical continuity is maintained by a copper circuit through the conductive layers and the electrical vias. The lower part of the package comprises an array of tin-lead alloy solder balls to be soldered onto a printed circuit board.
Stiffener material is attached onto the tape film surrounding the die and is flush with it. Due to the presence of the stiffener, the package lends itself well to enhancement of thermal performance. With the plane of the stiffener and die being the same, a heatsink can be bonded directly to the top of the die. However, the allowable compressive load on the ATAB package is determined by the long term load that the package-substrate interface (i.e. the solder ball interconnects) can support; therefore the amount of heat that can be removed from the package is significantly limited.
Furthermore, the ATAB package is rigid in all three axes, thereby limiting the number of interconnects that can reliably connect the package to a substrate.
Summary of the Invention It is an object of the present invention to provide an improved integrated circuit package and method of connecting an integrated circuit package to a substrate in which one or more of the disadvantages of the prior art is obviated or mitigated.
Therefore, the invention may be summarized according to a first broad aspect as an integrated circuit package for mounting on a substrate, comprising a flexible tape film consisting of at least one layer of dielectric material and at least one layer of conductive material, the tape film having a top surface and a bottom surface; a semiconductor die mounted either on or adjacent the top surface or on or adjacent the bottom surface of the tape film for connection to the substrate; a plurality of conductive leads of finite thickness mounted on the bottom surface of the tape film, the conductive leads being electrically connected through the at least one layer of conductive material to the semiconductor die; a molded body divided by the tape film into an upper molded body and a lower molded body, one of which covers the semiconductor die;
and rigid removable support material surrounding the upper molded body and bonded to the top surface of the tape film.
In the preferred embodiment, the package further comprises a heat spreader mounted either on or adjacent the top surface of the tape film, or on or adjacent the semiconductor die. The preferred embodiment of the package also comprises at least one clearance hole punched in the tape film, permitting the package to be easily clamped between a heatsink and a substrate. The package may comprise thermal vias that conduct heat from the upper or lower molded body covering the semiconductor die to the upper or lower molded body not covering the semiconductor die. Electrical vias through the tape film connect pairs of conductive layers.
The invention may be summarized according to a second broad aspect as a method of connecting an integrated circuit package to a substrate, the package comprising a flexible tape film consisting of at least one layer of dielectric material and at least one layer of conductive material, the tape film having a top surface and a bottom surface; a semiconductor die mounted either on or adjacent the top surface or on or adjacent the bottom surface of the tape film for connection to the substrate; a plurality of conductive leads of finite thickness mounted on the bottom surface of the tape film, the conductive leads being electrically connected through the at least one layer of conductive material to the semiconductor die; a molded body divided by the tape film into an upper molded body and a lower molded body, one of which covers the semiconductor die;
and rigid removable support material surrounding the upper molded body and bonded to the top surface of the tape film, the method comprising soldering the conductive leads to the substrate; removing the support material; and laying a heatsink onto the upper molded body.
An advantage of this invention is that it permits the package to be very tightly compressed between a heatsink and a substrate without causing degradation of the connection between the leads and the substrate. A further advantage of the present invention is that bending of the substrate to which the package finds itself connected will not cause the connection to wear out, as the tape film is flexible enough to accommodate contortions that may be applied to the conductive leads underneath. Consequently, a large number of conductive leads may be mounted to the tape film without reducing the reliability of the package.
Brief Descr~otion of the Drawings A preferred embodiment of the invention will now be described with reference to the attached drawings in which:
FIGURE 1 is a perspective view of an integrated circuit package prior to connection with a substrate, in accordance with the preferred embodiment of the present invention;
FIGURE 2 is a cross-sectional view of the package of FIGURE 1;
FIGURE 3 is a cross-sectional view of the package of FIGURE 1 after having been clamped between a heatsink and a printed circuit board, and after the support material has been removed; and FIGURES 4 to 9 are detailed cross-sectional views of an integrated circuit package according to alternate embodiments of the present invention.
Detailed Description of the Preferred Embodiment FIGURES 1 and 2 depict a package 10 which includes a flexible tape film 14 consisting of one or more layers 15 of flexible polyimide dielectric material such as UpilexTM or KaptonTM and two conductive layers 68 made of a material such as copper. The conductive layers 68 need not span the entire tape film 14, but may be arranged in conductive paths or traces (64, shown in FIGURE 1) electrically connected to each other on either side of the tape film 14 by conductive electrical vias (66, shown in FIGURE 2). In the preferred embodiment, two clearance holes 46 (only one shown in FIGURE 1), strategically located so as not to interfere with the conductive paths 64, are punched in the tape film 14 to allow easy installation of a clamping mechanism once the package 10 is connected to a substrate. It is understood that the invention will work equally well with more than two clearance holes, with only one clearance hole, or without clearance holes altogether.
The tape film 14 is identified as having a top S surface 32 and a bottom surface 34. As shown in FIGURE 2, a semiconductor die 12 is attached at a central location to the top surface 32. Any of a number of suitable methods used in the art, e.g. flip-chip, tape automated bonding (TAB) or wire bonding can be used to connect the semiconductor die 12 to the tape film 14. In fact, the semiconductor die 12 could similarly be attached to the bottom surface 34, as will become apparent when discussing alternate embodiments of the present invention in FIGURES 4 to 9. Preferably, a heat spreader 18 for removing excess heat from the package 10 is laid upon the semiconductor die 12. Again, alternate embodiments exist in which the heat spreader is placed differently, or in which the heat spreader 18 is not required.
Still referring to FIGURES 1 and 2, the package further comprises a molded body 20, preferably made of epoxy resin, which is split by the tape film 14 into an upper molded body 22 with a flat top and a lower molded body 24 with a flat bottom. The upper molded body 22 and lower molded body 24 are respectively sealed to the top surface 32 and bottom surface 34 of the tape film 14. Advantageous compliant properties of the polyimide dielectric allow the molded body 20 to be molded onto either surface of the tape film 14 by a conventional transfer molding process and without damaging the conductive paths 64.
Furthermore, prior to assembly of the package, the tape film 14 may comprise injection holes (not shown) which would cause both the upper and lower molded bodies 22,24 to form one integral piece of epoxy resin once molding is complete.
The upper molded body 22 surrounds the semiconductor die 12 and heat spreader 18. The flat bottom of the lower molded body 24 is generally in a same plane 90 as an array of conductive leads 16, arranged as an array of solder balls, for eventual connection of the package 10 to a substrate such as a PCB. The conductive leads 16 are joined electrically to the semiconductor die 12 by the conductive paths 64 etched in the conductive layers 68. Other interconnect styles as known in the art may be used in place of the array of solder balls; for example, perimeter leads used in gull wing surface mount technology.
A layer of rigid support material 26 is bonded with an adhesive (not shown) onto the top surface 32 of the tape film 14, without adversely affecting the conductive paths 64.
In the preferred embodiment, the support material 26 will surround the upper molded body 22 so as to support and keep the tape film 14 flat during soldering of the solder balls 16 to a substrate. Without a "window frame" of support material, the package would not be flat enough during assembly and some leads might not solder to the substrate.
Ideally, the support material 26 is made of a soluble organic compound, such as Water Extendible Vinyl Ester Resin (WEVERTM) manufactured by Dow Chemical Inc., that can be dissolved by rinsing the package in water following connection to a substrate. Support materials which are soluble in liquids other than water are also contemplated. Alternatively, the compound can be made of an arbitrary rigid material, connected to the tape film by an ultraviolet-sensitive glue whose adhesive properties are altered upon exposure to ultraviolet light, and which can thus be made to shed the support material 26 after installation. Still other embodiments may comprise support material adhering to the top surface of the tape film by means of a soluble glue which can similarly cause the package to shed the support material upon immersion in or rinsing with a solvent such as water.
In FIGURE 3, the package 10 is shown connected to a printed circuit board (PCB) 40. A heatsink 42 with a flat bottom is laid on top of the upper molded body 22. The support material (26, shown in FIGURES 1 and 2) has been removed as per one of the previously discussed methods. A heatsink-package interface 48 and a package-substrate interface 50 can be identified. The heatsink-package interface is defined between the flat top of the upper molded body 22 and the flat bottom of the heatsink 42 while the package-substrate interface is defined partly between the flat bottom of the lower molded body and the PCB 40 and partly between the solder balls 16 and the PCB 40. A clamping mechanism 44 known per se and illustrated schematically protrudes through clearance holes (46, shown in phantom), extending into the PCB 40 at one end and through the heatsink 42 at the other. Screws, bolts, springs, or any of a variety of suitable mechanical fasteners are used to tighten the clamping mechanism and compress the package 10 between the heatsink 42 and the PCB 40.
In operation, it is desired to press heatsink 42 to the upper molded body 22 with enough pressure to achieve efficient heat dissipation. With the clamping mechanism of FIGURE 3, this will result in large amounts of pressure being applied to the heatsink-package interface 48 and to the package-substrate interface 50.
As discussed previously, neither the upper part of the package nor the substrate is usually a source of failure under high pressure in traditional packages. It is at a point on the package-substrate interface, i.e. at the conductive leads, that a failure will often occur. In this inventive package, pressure on the conductive leads 16 is countered by a flex in the tape film 14, so that pressure applied to the package-substrate interface is absorbed mostly by the lower molded body 24. The effect is that efficient dissipation of heat is achieved without degrading the reliability of the conductive connection. The presence of a heat spreader 18 near the heatsink 42 assists in providing the illustrated embodiment with excellent thermal properties.
Although it is preferred that the lower molded body 24 be substantially the same thickness as the conductive leads 16 such that the flat bottom is substantially coplanar with the undersides of the leads 16, slight deviation in either direction can be accommodated by flexure of the tape film.
Furthermore, the compliant nature of the tape reduces the need for the top and bottom surfaces to be parallel to each other.
The slight sideways force generated during clamping will be absorbed in the tape layer in the same fashion that twisting a board does. The low modulus and thickness of the tape film result in a structure that, once the support material has been removed, is very compliant in all three axes.
Alternate embodiments of the present invention are now described with reference to FIGURES 4 through 9. All of the following embodiments share the presence of a flexible tape film having one layer of polyimide dielectric; a window frame of rigid support material; an array of solder balls; and upper and lower molded bodies respectively molded to the top and bottom surfaces of the tape film. As previously discussed, the lower molded body is preferably substantially the same thickness as the array of conductive leads but slight deviations in either sense can be accommodated without undermining the value or functionality of the present invention. It is also understood that two or more layers each of polyimide dielectric and conductive material may be required to form more complex conductive paths leading from each conductive lead to the semiconductor die.
In FIGURE 4 is shown a flip-chip setup, with the semiconductor die 12 mounted to the top surface 32 of tape film 14 by a set of flip-chip solder balls 80. The conductive layers 68 are joined by conductive electrical vias 66 and electrically connect the flip-chip solder balls 80 to the conductive leads 16. A thermal spreader 18 is mounted atop the semiconductor die 12 within the upper moulded body 22, resulting in a package with high thermal performance.
FIGURE 5 shows another flip-chip arrangement wherein only one conductive layer 68 and no electrical vias are required. In this version, however, the semiconductor die 12 is mounted to the bottom surface of tape film 14 and is surrounded by the lower molded body 24. The thermal dissipation properties of this package would be poor if not for a heat spreader 18, mounted onto the top surface of tape film 14, rendering thermal performance moderate.
In FIGURE 6, the semiconductor die 12 is attached upside-down onto the top surface of the tape film 14. Flip-chip solder balls have been replaced by wire bonds 82 electrically connecting the semiconductor die 12 (through electrical vial 66) to conductive paths on a single conductive layer 68 adjacent the bottom surface of tape film 14. No heat spreader is present, resulting in relatively poor thermal performance .
FIGURE 7 depicts another wire bonded setup, this time with the semiconductor die mounted upside-down to the bottom surface of tape film 14. A heat spreader 18 is mounted to the top surface of tape film 14, and is thermally connected to the semiconductor die 12 by thermal vias 84 penetrating the tape S film, resulting in moderate thermal performance of the integrated circuit package. It is noted that the package requires no more than one conductive layer 68; furthermore, no electrical vias are necessary.
FIGURE 8 illustrates a similar arrangement to the one in FIGURE 5, except that an access window 86 is carved in the tape film 14 thereby allowing the semiconductor die 12 to be provided with TAB bonds 88. As will be apparent to one skilled in the art, thermal performance of this package will be poor due to the semiconductor die 12 being located underneath the tape film 14 and lack of a heat spreader.
In contrast, FIGURE 9 provides a TAB-mounted package offering high thermal performance, similar in many respects to the flip-chip arrangement in FIGURE 4. In this variant of the present invention, two electrical vias 66 join conductive paths on each of two conductive layers 68.
While the preferred embodiment, in addition to several alternate forms, of the invention has been described and illustrated it will be apparent to one skilled in the art that further variations in the design may be made. The scope of the invention, therefore, is only to be limited by the claims appended hereto.

Claims (29)

1. An integrated circuit package for mounting on a substrate comprising:
a flexible tape film consisting of at least one layer of dielectric material and at least one layer of conductive material, the tape film having a top surface and a bottom surf ace ;
a semiconductor die mounted either on or adjacent the top surface or on or adjacent the bottom surface of the tape film for connection to the substrate;
a plurality of conductive leads of finite thickness mounted on the bottom surface of the tape film, the conductive leads being electrically connected through the at least one layer of conductive material to the semiconductor die;
a molded body divided by the tape film into an upper molded body and a lower molded body, one of which covers the semiconductor die; and rigid removable support material surrounding the upper molded body and bonded to the top surface of the tape film.
2. An integrated circuit package according to claim 1, wherein the package further comprises a heat spreader mounted on or adjacent the top surface of the tape film.
3. An integrated circuit package according to claim 1, wherein the package further comprises a heat spreader mounted on or adjacent the semiconductor die.
4. An integrated circuit package according to claim 1, wherein the tape film further comprises at least one clearance hole.
5. An integrated circuit package according to claim 1, wherein the support material is soluble in liquid solvent.
6. An integrated circuit package according to claim 1, wherein the support material is water soluble.
7. An integrated circuit package according to claim 1, wherein the support material is connected to the tape film by an ultraviolet-sensitive glue.
8. An integrated circuit package according to claim 1, wherein the support material is connected to the tape film by a soluble glue.
9. An integrated circuit package according to claim 1, wherein the conductive leads form an array of solder balls.
10. An integrated circuit package according to claim 1, wherein the conductive leads form an array of gull wings.
11. An integrated circuit package according to claim 1, the tape film further comprising thermal vias that conduct heat from the upper or lower molded body covering the semiconductor die through to the upper or lower molded body not covering the semiconductor die.
12. An integrated circuit package according to claim 1, wherein there are at least two conductive layers which are
13 electrically connected by electrical vial through the tape film.

13. An integrated circuit package according to claim 1, wherein the upper molded body has a flat top and the lower molded body has a flat bottom.
14. An integrated circuit package according to claim 12, wherein the lower molded body has a thickness substantially equal to the thickness of the conductive leads.
15. An integrated circuit package according to claim 5, wherein the upper molded body has a flat top and the lower molded body has a flat bottom.
16. An integrated circuit package according to claim 6, wherein the upper molded body has a flat top and the lower molded body has a flat bottom.
17. An integrated circuit package according to claim 7, wherein the upper molded body has a flat top and the lower molded body has a flat bottom.
18. An integrated circuit package according to claim 8, wherein the upper molded body has a flat top and the lower molded body has a flat bottom.
19. An integrated circuit package according to claim 1, wherein the lower molded body has a thickness substantially equal to the thickness of the conductive leads.
20. An integrated circuit package according to claim 15, wherein the lower molded body has a thickness substantially equal to the thickness of the conductive leads.
21. An integrated circuit package according to claim 16, wherein the lower molded body has a thickness substantially equal to the thickness of the conductive leads.
22. An integrated circuit package according to claim 17, wherein the lower molded body has a thickness substantially equal to the thickness of the conductive leads.
23. An integrated circuit package according to claim 18, wherein the lower molded body has a thickness substantially equal to the thickness of the conductive leads.
24. A method of connecting an integrated circuit package to a substrate, the package comprising a flexible tape film consisting of at least one layer of dielectric material and at least one layer of conductive material, the tape film having a top surface and a bottom surface; a semiconductor die mounted either on or adjacent the top surface or on or adjacent the bottom surface of the tape film for connection to the substrate; a plurality of conductive leads of finite thickness mounted on the bottom surface of the tape film, the conductive leads being electrically connected through the at least one layer of conductive material to the semiconductor die; a molded body divided by the tape film into an upper molded body and a lower molded body, one of which covers the semiconductor die;
and rigid removable support material surrounding the upper molded body and bonded to the top surface of the tape film, the method comprising:
soldering the conductive leads to the substrate;
removing the support material; and laying a heatsink onto the upper molded body.
25, A method of connecting an integrated circuit package to a substrate according to claim 24, wherein the support material is water soluble and removal of the support material is achieved by rinsing the package with water.
26. A method of connecting an integrated circuit package to a substrate according to claim 24, wherein the support material is connected to the tape film by an ultraviolet-sensitive glue and removal of the support material is achieved by exposing the package to ultraviolet light.
27. A method of connecting an integrated circuit package to a substrate according to claim 24, wherein the support material is connected to the tape film by a soluble glue and removal of the support material is achieved by immersing the package in a solvent.
28. A method of connecting an integrated circuit package to a substrate according to claim 24, the method further comprising compressing the package between the heatsink and the substrate by a clamping mechanism.
29. A method of connecting an integrated circuit package to a substrate according to claim 28, wherein the tape film further comprises clearance holes for attachment of the clamping mechanism.
CA002252407A 1997-12-02 1998-11-03 Flexible integrated circuit package Expired - Lifetime CA2252407C (en)

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US08/982,506 1997-12-02
US08/982,506 US5901041A (en) 1997-12-02 1997-12-02 Flexible integrated circuit package

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Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6734545B1 (en) * 1995-11-29 2004-05-11 Hitachi, Ltd. BGA type semiconductor device and electronic equipment using the same
JPH10294418A (en) * 1997-04-21 1998-11-04 Oki Electric Ind Co Ltd Semiconductor device
US5953108A (en) * 1997-05-28 1999-09-14 Laser Alignment, Inc. Laser beam projector power and communication system
US5969947A (en) 1997-12-17 1999-10-19 International Business Machines Corporation Integral design features for heatsink attach for electronic packages
US6057174A (en) * 1998-01-07 2000-05-02 Seiko Epson Corporation Semiconductor device, method of fabricating the same, and electronic apparatus
WO1999035683A1 (en) * 1998-01-12 1999-07-15 Seiko Epson Corporation Semiconductor device, manufacture thereof, and electronic device
US6194782B1 (en) * 1998-06-24 2001-02-27 Nortel Networks Limited Mechanically-stabilized area-array device package
JP3876088B2 (en) * 1999-01-29 2007-01-31 ローム株式会社 Semiconductor chip and multi-chip type semiconductor device
US6355199B1 (en) * 1999-02-12 2002-03-12 St. Assembly Test Services Pte Ltd Method of molding flexible circuit with molded stiffener
US6376769B1 (en) 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
US6717819B1 (en) 1999-06-01 2004-04-06 Amerasia International Technology, Inc. Solderable flexible adhesive interposer as for an electronic package, and method for making same
US6208519B1 (en) 1999-08-31 2001-03-27 Micron Technology, Inc. Thermally enhanced semiconductor package
US6425179B1 (en) * 1999-10-12 2002-07-30 Lsi Logic Corporation Method for assembling tape ball grid arrays
US6377219B2 (en) 2000-01-11 2002-04-23 Cool Options, Inc. Composite molded antenna assembly
US6680015B2 (en) 2000-02-01 2004-01-20 Cool Options, Inc. Method of manufacturing a heat sink assembly with overmolded carbon matrix
US6678167B1 (en) * 2000-02-04 2004-01-13 Agere Systems Inc High performance multi-chip IC package
US6580031B2 (en) 2000-03-14 2003-06-17 Amerasia International Technology, Inc. Method for making a flexible circuit interposer having high-aspect ratio conductors
US6489571B1 (en) * 2000-10-31 2002-12-03 Lsi Logic Corporation Molded tape ball grid array package
EP1346411A2 (en) * 2000-12-01 2003-09-24 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US6906414B2 (en) * 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
US7161239B2 (en) * 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US7132744B2 (en) 2000-12-22 2006-11-07 Broadcom Corporation Enhanced die-up ball grid array packages and method for making the same
US20020079572A1 (en) * 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US6853070B2 (en) 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
DE10111759A1 (en) * 2001-03-12 2002-10-02 Infineon Technologies Ag Casing structure for use with semiconductor microchips has a floating semiconductor microchip cased by an injection-molded plastic sealing or covering compound.
US6529115B2 (en) * 2001-03-16 2003-03-04 Vishay Israel Ltd. Surface mounted resistor
US7259448B2 (en) * 2001-05-07 2007-08-21 Broadcom Corporation Die-up ball grid array package with a heat spreader and method for making the same
US6541856B2 (en) * 2001-06-06 2003-04-01 Micron Technology, Inc. Thermally enhanced high density semiconductor package
US20030048624A1 (en) * 2001-08-22 2003-03-13 Tessera, Inc. Low-height multi-component assemblies
EP1313214B1 (en) * 2001-11-16 2020-02-26 SnapTrack, Inc. Packaging substrate and manufacturing method thereof, integrated circuit device and manufacturing method thereof, and saw device
US6879039B2 (en) 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US6631078B2 (en) * 2002-01-10 2003-10-07 International Business Machines Corporation Electronic package with thermally conductive standoff
US7245500B2 (en) * 2002-02-01 2007-07-17 Broadcom Corporation Ball grid array package with stepped stiffener layer
US6861750B2 (en) * 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
US7550845B2 (en) 2002-02-01 2009-06-23 Broadcom Corporation Ball grid array package with separated stiffener layer
US6825108B2 (en) * 2002-02-01 2004-11-30 Broadcom Corporation Ball grid array package fabrication with IC die support structures
US6876553B2 (en) 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US7196415B2 (en) 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
US6696748B1 (en) * 2002-08-23 2004-02-24 Micron Technology, Inc. Stress balanced semiconductor packages, method of fabrication and modified mold segment
US20040104463A1 (en) * 2002-09-27 2004-06-03 Gorrell Robin E. Crack resistant interconnect module
JP2004311768A (en) * 2003-04-08 2004-11-04 Shinko Electric Ind Co Ltd Manufacturing method of substrate, substrate for semiconductor devices and semiconductor device
US20050093175A1 (en) * 2003-11-03 2005-05-05 Martin Reiss Arrangement for improving the reliability of semiconductor modules
US20050161806A1 (en) * 2004-01-22 2005-07-28 Divakar Mysore P. Area array packages with overmolded pin-fin heat sinks
US7432586B2 (en) 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US7411281B2 (en) * 2004-06-21 2008-08-12 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US7482686B2 (en) 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US7786591B2 (en) * 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
JP4014591B2 (en) * 2004-10-05 2007-11-28 シャープ株式会社 Semiconductor device and electronic equipment
US7405474B1 (en) * 2004-10-12 2008-07-29 Cypress Semiconductor Corporation Low cost thermally enhanced semiconductor package
KR100697980B1 (en) * 2005-09-12 2007-03-23 삼성전기주식회사 Manufacturing method of printed circuit board having electronic components within
US8183680B2 (en) * 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
EP2191701B1 (en) 2007-09-28 2013-03-20 Tri-Star Laminates, Inc. Entry sheet, method of manufacturing thereof and methods for drilling holes in printed circuit boards
WO2009075770A1 (en) * 2007-12-07 2009-06-18 Integral Technology, Inc. Improved insulating layer for rigid printed circuit boards
JP4697243B2 (en) * 2008-02-22 2011-06-08 セイコーエプソン株式会社 Bonded body and bonding method
JP5236377B2 (en) * 2008-07-16 2013-07-17 シャープ株式会社 Semiconductor device and display device
TWM397596U (en) * 2010-03-22 2011-02-01 Mao Bang Electronic Co Ltd Integrated circuit chip card
JP2012033559A (en) * 2010-07-28 2012-02-16 J Devices:Kk Semiconductor device
US8691626B2 (en) * 2010-09-09 2014-04-08 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US9142530B2 (en) * 2013-03-21 2015-09-22 Stats Chippac Ltd. Coreless integrated circuit packaging system and method of manufacture thereof
US9613845B2 (en) * 2014-01-17 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion de-taping
JP6381004B2 (en) * 2014-03-27 2018-08-29 インテル・コーポレーション Process integration of multi-device flexible electronics system on chip (SOC)
CN106920779B (en) 2017-03-09 2019-09-06 三星半导体(中国)研究开发有限公司 The composite structure and its transportation resources of flexible semiconductor packaging part
US10636749B2 (en) * 2017-11-14 2020-04-28 Intel Corporation Semiconductor package substrate support structures for ball-grid array cavities, and methods of assembling same
US10529693B2 (en) 2017-11-29 2020-01-07 Advanced Micro Devices, Inc. 3D stacked dies with disparate interconnect footprints
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771330A (en) * 1987-05-13 1988-09-13 Lsi Logic Corporation Wire bonds and electrical contacts of an integrated circuit device
AU8034087A (en) * 1987-02-20 1988-09-14 Lsi Logic Corporation Integrated circuit package assembly
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5045921A (en) * 1989-12-26 1991-09-03 Motorola, Inc. Pad array carrier IC device using flexible tape
US5222014A (en) * 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
KR940008335A (en) * 1992-09-03 1994-04-29 백중영 Auto-redialing method
JPH08508611A (en) * 1993-03-31 1996-09-10 ユニシス・コーポレイション Liquid metal heat conducting member and integrated circuit package incorporating the same
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
JP3098392B2 (en) * 1995-03-03 2000-10-16 シャープ株式会社 Mounting substrate and liquid crystal module using the same
JP3004578B2 (en) * 1995-05-12 2000-01-31 財団法人工業技術研究院 Integrated Circuit Package Consisting of Multi-Heat Conductors for Enhanced Heat Dissipation and Caps Around the Edge for Improved Package Integrity and Reliability
JP3229786B2 (en) * 1995-09-12 2001-11-19 シャープ株式会社 Tape carrier package and storage method thereof
JPH10163386A (en) * 1996-12-03 1998-06-19 Toshiba Corp Semiconductor device, semiconductor package and mounting circuit device
JPH10247702A (en) * 1997-03-05 1998-09-14 Sumitomo Kinzoku Electro Device:Kk Ball grid array package and printed board

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KR19990062684A (en) 1999-07-26
US5901041A (en) 1999-05-04
JP3337129B2 (en) 2002-10-21
JPH11265909A (en) 1999-09-28
KR100576657B1 (en) 2006-07-25
CA2252407A1 (en) 1999-06-02

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