CA2260054C - Method and apparatus for transmitting lan data over a synchronous wide area network - Google Patents

Abstract

A packet of data is received from a LAN and transmitted over a WAN, by retaining the native LAN frame format of the packet during transmission across the WAN. Thus, LAN data may be transmitted over a SONET
point-to-point link within a WAN network without the interim steps of creating ATM cells or other WAN transport packaging protocols. Instead, the LAN data may be transmitted directly over the SONET link as raw data, and reconstructed directly at the receiving end of the SONET link. A first buffer stores data from the LAN
so that a corresponding packet size may be determined, and a second buffer stores data from the WAN to account for any speed difference between the LAN circuitry and WAN circuitry.

Description

METHOD AND APPARATUS FOR TRANSMITTING LAN DATA OVER A
SYNCRHONOUS WIDE AREA NETWORK
Background of the Invention Field of the Invention This invention relates generally to computer networking systems and more particularly to transmitting data from a local area network over a wide area network.
Discussion of the Related Art Computer networks are widely used to provide increased computing power, sharing of resources, and communications between users. Local area networks (LANs) may include a number of computer devices within a room, building, or site that are connected by high speed data links such as token ring, ethernet, or the like. LANs have traditionally been interconnected by bridges, hubs, and switches. A Wide Area Network (WAN) may link together different LANs. A
WAN typically includes packet switches, microwave links, and satellite links.
Thus, a network may include several hundred or more interconnected devices (nodes), distributed across several geographical locations, and belonging to several organizations.
LANs are typically used for high speed communications with relatively few nodes, while WANs are used for connecting a vast number of nodes, but generally at a slower speed. Therefore, LAN transport mechanisms and protocols are typically not appropriate for use on a WAN.
Fig. 1 shows an example of an arrangement in which a WAN couples together several LANs. In particular, Fig. 1 shows WAN 10 connecting LAN A, LAN B and LAN C. A LAN/WAN interface 12 provides translation, data formatting, and/or other protocol-related functions so that source and destination computers on LAN A may interface with source and destination computers on LAN B and LAN C.
Similarly, LAN/WAN interface 14 allows LAN B to be coupled to WAN 10, and LAN/WAN interface 16 allows LAN C to be coupled to WAN 10.

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_7_ One method of interfacing a LAN to a WAN is to provide a router-specific intert~ace which substitutes a WAN physical link layer and a proprietary data link layer in each LAN
data message, and rate-converts the LAN messages to WAN compatible speeds.
Then the messages may be transmitted across the WAN. A drawback to such an approach is that many s of the high-capacity networks that provide high-speed communications within the WAN are inflexible and expensive. Additionally, there is very limited network management and maintenance support capabilities, and very little, if any, spare signal capacity within frame structures, in the WAN protocol. Thus, this technique is generally very expensive and slow.
SONET (Synchronous Optical Network) is a standard for a high-capacity optical o telecommunications network. It is a synchronous digital transport system intended to pr9vide a more simple, economical and flexible network infrastructure. The phase 1 SONET standard issued in March 1988, and is defined in ''American National Standard for Telecommunications - Synchronous Optical Network (SONET) Payload Mappings", ANSI
T 1,105.02-I 993 draft.
~s SONET may also be defined as an octet-synchronous multiplex scheme that defines a family of standard rates and formats. Despite the name, SONET is not limited to optical links. Electrical specifications have been defined for single-mode fiber, mufti-mode fiber, and CATV 75 ohm coaxial cable. The transmission rates are integral multiples of ~
1.840 Mbps, which may be used to carry T3/E3 bit-synchronous signals. The allowed multiples are 2o currently specified as:
2s STS-1 51.840 STS-18 933.120 STS-3 155.520 STS-24 1,244.160 STS-9 466.560 STS-36 1,866.240 STS-12 622.080 STS-48 2,488.320 The CCITT Synchronous Digital Hierarchy (SDH) defines a subset of SONET
transmission rates, beginning at 155.520 Mbps, as set forth below:
3o SONET SDH equivalent STS-3c STM-1 STS-12c STM-4 STS-48c STM-16 ,4ME1'IDED SHEET

As defined, SONET can be used in loop carrier, local network, and long haul network application areas.
Fig. 2 is a block diagram of SONET elements coupled together in a direct synchronous multiplexing mode. SONET line signals 21 are transmitted across the SONET
digital cross-connect system 20. SONET terminal multiplexers 22, 24 receive tributary signals 23, for example from source and destination computers, and provide the SONET line signals.
One advantage of the SONET standard is that individual tributary signals may be accessed within the structure of the multiplexed SONET line signal. For example, SONET add-drop multiplexers 26 and 28 may each provide data from their respective tributary signals 25 0 onto the SONET digital cross-connect system 20.
The building block of the SONET protocol is a synchronous transport frame 30, shown in Fig. 3. Frame 30 includes transport overhead 34, and synchronous payload envelope (SPE) 32. Although data is transported serially, the frame 30 is typically represented by a two-dimensional map with N rows and M columns; a byte is provided at each row/column t 5 intersection. The signal bits are transmitted starting with the byte in the upper left hand corner of the frame 30, followed by the second byte in the top row, etc., until all of the bytes of the first top row are transmitted. The second and subsequent rows follow transmission of the first row in the same manner.
The SPE 32 includes individual tributary signals, and is designed to traverse a SONET
20 network from end to end. The SPE 32 is assembled and disassembled only once, even though it may be transferred from one transport system to another (i.e., between several SONET network nodes) many times on its route through the SONET network.
Some signal capacity is allowed in each frame 30 for transport overhead 34 to provide support and maintenance facilities, such as alarm monitoring, bit-error monitoring, and data 25 communications channels. Transport overhead 34 typically pertains only to an individual transport system and is not transferred when the SPE 32 is transferred between different transport systems.
One method of interfacing a LAN with a WAN, such as SONET, is to use the Asynchronous Transfer Mode (ATM) standard defined by the ATM Forum in the "LJNI 4.0"
3o specification. Each ATM cell has an overhead of 5/48 or 10.4%. This is a relatively large amount of overhead, when compared to a typical LAN packet. Fig. 4 shows an ATM
cell 40, in r:l.~ . tmv.~.n 1 ~u m.w.m.,: m, ,..- tm-.~.CA 02260054 1999-O1-06~ ~_~~ _m m-- ~.~ ;,:~ _.,:r,mm~,:,: n ., which 4$ bytes of ATM data 44 are transmitted with a 5-byte ATM header 42. In accordance ~~
with the ATM standard, an A'TM cell always has 53 bytes.
Fig. 5 shows a SONET synchronous transport frame 49 that includes ATM cells_ The synchronous transport frame 49 includes SPE 53 and a transport overhead 48 which includes s section overhead 50, pointer 52 and line overhead 51, Tlie pointer 52 is a reference which indexes the starting point of the SPE 53. SPE ~3 includes path overhead 54, ATM cells SSA, 55B, 55C, 55D, and 55E, and other data. During times for which there are no ATM cells to transmit, an idle space is provided (see for example idle space Sf between rivo ATM cells 55b and 55E). In addition, because an integer number of ATM cells may not fit within a given SPE, o there may be some empty space 57 {see Fig. 5) following the last ATM cell, or otherwise dispersed within the SPE.
Fig. 6 depicts a known process for converting LAN data to ATM cells for transport over a SONET network. In step 58, a LAN packet is received from a fast LAN. The LAN
packet is divided into 48-byte segments {step 59) in accordance with the fixed ATM cell size. An ATM 5-~ s byte header is added to each of the 4$-byte segnents {step 60) to create a number of ATM cells.
The ATM cells are packed into a SONET SfE (step 61). The appropriate SONET
transpoz~t overhead is then added to the SPE (step 62) to create a synchronous transport frame. The frame may then be transmitted orrer the SO~'ET-compatible ncawork tstep 63).
At another SONET rnultiplexer, the synchronous trastsport frame is received (step 64).
z0 The SONET transport overhead is removed (sip 65) to yield the SPE. It is then necessary to unpack the ATM cells from the SPE ir. order to provide ATM cells {step 66).
The ATM header is removed from each of the ATM cells (step 67). Only then may the LAN packet datz be reconstructed fi-vxn the ATM cell data (step 6S). The reconstructed LA,.'~i packet may they be iranslnitted onto a second LAN {step 69).
25 As is evident from Figs. 4-6, there is a signif cant amount of overhead which is reduired to transmit reconstn.lcted LAN data over a SUNET network using the ATM
standard. This overhead includes not only signal bandwidth, for example the 5-byte ATM header added for each 48 bytes of data, but also significant pzacessing time in order to divide the LAN packet, construct the ATM cells, and ultizr:ately reeonstnrct the LAN packet.
AMENDED SHEE?

Summary of The Invention In a preferred embodiment of the present invention, a method and apparatus are provided for transmitting a packet of LAN data over a WAN, by retaining a native LAN
frame format of the packet across the WAN. Thus, data received from a LAN may be transmitted over a SONET
point-to-point link without the interim steps of creating ATM cells or other reformatted message units. Instead, the LAN data may be transmitted directly over the SONET link as "raw data"
(native LAN frame format) within SONET transport frames, and reconstructed directly at the receiving end of the SONET link.
In one embodiment, an interface is provided between a first network and a second network, including a first interface device, a second interface device, an input buffer, and a control circuit. The first interface device is capable of communicating across the first network in accordance with a protocol of the first network, and the second interface device is capable of communicating across the second network in accordance with a protocol of the second network.
An input buffer receives and stores a packet from the first interface device.
A control circuit is ~ 5 coupled between the first interface device and the second interface device, and is coupled with the input buffer. The control circuit determines a length of the packet and provides the packet and an indication of the length of the packet to the second interface device.
The second interface device transmits the packet and the indication of the length of the packet across the second network.
2o Another embodiment of the invention is directed to a method for transmitting data from a first network to a second network, comprising the steps of receiving a data packet from a source on the first network, buffering the packet to provide buffered data, determining a length of the packet from the buffered data, and transmitting the packet and an indication of the length of the packet across a third network which is coupled between the first network and the second 25 network, so that the packet is received at the second network.
Yet another embodiment is directed to an apparatus for transmitting data from a first network to a second network, comprising means for receiving a data packet from a source on the first network, means for buffering the packet to provide buffered data, means for determining a length of the packet from the buffered data, and means for transmitting the packet and an 3o indication of the length of the packet across a third network which is coupled between the first network and the second network.

In any of the above embodiments, a receive buffer may store data to account for rate differences between the first and second networks. Additionally, a preamble may be transmitted along with the data, and a fill pattern may be transmitted when there are no packets to be transmitted. The first network may be a local area network, and the packet may be transmitted as a contiguous data stream in a frame format which is native to the local area network. The packet may be transmitted by an interface device operating in a "raw data" mode that does not require additional formatting or encapsulation, other than that required to comply with a protocol of the network over which the packet is transmitted.
These and other features and advantages of the present invention shall appear from the o following detailed description and drawings.
Brief Description of The Drawings Fig. 1 is a schematic illustration of a wide area network (WAN) connecting several local area networks (LANs);
Fig. 2 is a block diagram showing elements of a SONET network;
Fig. 3 depicts the contents of a synchronous transport frame, which is transmitted across a SONET network such as that shown in Fig. 2;
Fig. 4 depicts the contents of an ATM cell;
Fig. 5 illustrates an approach to packing ATM cells into a synchronous payload envelope (SPE) within a synchronous transport frame such as that shown in Fig. 3;
Fig. 6 is a flow diagram showing the known process steps required to transmit reformatted LAN data over a SONET network using the ATM standard;
Fig. 7 is a high-level block diagram of an embodiment of the invention, in which a SONET network provides communications between two LANs;
Fig. 8 is a block diagram of a SONET/LAN interface, such as that shown in Fig.
7;
Fig. 9 is a flow diagram of process steps for transmitting a LAN packet from one LAN
network to another LAN network across a SONET network, which may be performed by the elements of the block diagram of Fig. 8;
Fig. 10 illustrates more detail of one of the steps of Fig. 9, in which the LAN packet is packed directly into a SONET synchronous payload envelope (SPE) along with a packet length field;

_7_ Fig. 11 illustrates more detail of the one step of Fig. 9, in which a LAN
packet is unpacked from the SPE using information regarding the length of the LAN
packet;
Fig. 12 shows a SONET frame in accordance with an embodiment of the present invention;
Fig. 13 shows a mapping of LAN packets onto SONET SPEs according to the invention;
Fig. 14 is a detailed schematic diagram of one apparatus for implementing the invention;
Fig. 15 is a flow process diagram of steps performed by the Transmit FIFO
Write Control Logic ( 1402) of Fig. 14;
Fig. 16 is a flow process diagram of steps performed by the Transmit FIFO Read Control t o Logic ( 1410) of Fig. 14;
Fig. 17 is a flow process diagram of steps performed by the Receive FIFO Write Control Logic ( 1420) of Fig. 14;
Fig. 18 is a flow process diagram of steps performed by the Receive FIFO Read Control Logic (1430) of Fig. 14;
Fig. 19 is a block diagram of another embodiment of the invention;
Fig. 20 is a flow process diagram of steps performed by the apparatus illustrated in Fig.
19 when transmitting data to a SONET WAN;
Fig. 21 is a flow process diagram of steps performed by the apparatus illustrated in Fig.
19 when receiving data from a SONET WAN; and 2o Fig. 22 is a detailed schematic diagram of one embodiment of the invention as shown in Fig. 19.
Detailed Description There are many businesses or organizations having two or more geographically-separated LANs between which much data is transmitted. Fig. 7 shows an example in which LAN A is in a first location 71, such as a first building or campus, and LANs B and C are in a second location 72, such as a second building or campus. WAN 70 provides communications among these and several other LANs. for example LAN D and LAN E. In this example, LAN A is coupled to WAN 70 by SONET/LAN interface 73A, and LAN B is coupled to WAN 70 by SONET/LAN
interface 73B. LAN B is also coupled to LAN C by bridge 74. LAN/WAN interface provides communications between LAN D and WAN 70, and LAN/WAN interface 77 provides #~l.v. Wv n.t'v w i. .~W..~. ,n~ . ,,' t" ''CA 02260054 1999-O1-~U6' ,.'~ -,., , _ r,;, ;5;1 _ v.:,..s ,,.:.:" ., -$_ communications between LAN $ and WAN 70. Suitable LAN/WAN interfaces 7fi, 77 are known in the art.
The fast SONET/LAN interface 73A, second SONETlLAN interFace 73B, and WA,N 70 provide a point-to-point communications path 75 between LAN A and LAN B. In essence, the SONET/LAN interfaces 73A, 73H provide a bridge function between LAN A and LAN
B, and also au effective interface between LAN A and LAN C. The 50NET/LAN interfaces 73A, 73B
transmit and receive data between LAN A and LAN B without formatting the packet data into separate cells; such as ATM cells. 'The point-to-point liak 75 may be a SONET
Link within the WA.'~ 70, which is rxeated and maintained by a communications provider.
r o Fig. $ depicts more detail of the S4NETILAN interface 73. A SONET line transceiver 80 provides a physical interface with the SONET network. Coupled to tl:e transceiver 80 is a SONET framer/deframer with raw data capability 82. The "raw data" capability, also referred to as "native frame format" capability, means that data can be transmitted across the SONET
network without adding additional overhead to the data other than the overhead which is required 1 s by SONET. Examples of overhead required by SONET include uansport overhead including payload pointers, path over: _d including section overhead and line overhead, and rzrtual transport overhead including virtual payload pointers and virtual path overhead. In at least one SONET implementation, line overhead includes payload pointers, automatic protection switching, parity check, alarm infozmation, and section overhead includes frame alignment 2o pattern, STS identification and parity check.
When a data packet is transported in its native frame format, this means that the data packet is still recognizable (arranged) as it was when transported across a LAN. Typically, this also means that there is no additional overhead interspersed within the data packet. In one embodiment, an interface device having ATM cell processing capability may be operated in a zS mode which "bypasses" the ATM cell processing capability, such that the raw data is provided by the interface device. For example, the raw data capability may be invoked by selecting a test or diagnostic mode of the SONET frazrier/deframer 82 (bypassing the ATM
processing).
A data formatter 84 is coupled between the framer/deframer $2 and LAN media access controller 86. The controller 86 provides an interface to the appropriate LAN, fvr example L AN
30 A or LAN B shown in Fig. 7.
Fig. 9 shows the process steps by which a LAN packet is transmitted from a first LAN to a second LAN. In step 90, the LAN packet is received from the i'-~rst LAN. In step 91, the length AMENDS p SHEET

of the LAN packet is determined, so that ultimately the LAN packet may be unpacked on the receiving end. Such packet length may be defined as a number of eight-bit bytes, but may also be defined as a number of bits, or a number of 16-bit words. The LAN packet may be one from an ethernet, FDDI, token ring, or other protocol. In step 92, the LAN packet and a packet length field are packed directly into a SONET synchronous payload envelope (SPE). In step 93, SONET transport overhead is appended to the SONET SPE to create a synchronous transport frame. By using a packet length field, it is not necessary to include delimiters indicative of the end of packet and beginning of packet, which would typically be included if the packet were encapsulated within another format, such as the HDLG format. HDLC
encapsulation would 1o require significantly more overhead.
In step 95, the synchronous transport frame is transmitted over a SONET-compatible network. The synchronous transport frame is received, and the SONET transport overhead is then removed (step 96) to yield the synchronous payload envelope SPE (step 97). Because the SPE includes a packet length field, the bytes of the LAN packet may be unpacked from the SPE
by unpacking the appropriate number of bytes as determined by the packet length field (step 98).
The unpacked LAN packet is then transmitted onto the second LAN (step 99).
As can be seen from a comparison of Fig. 9 and Fig. 6, there is much less overhead and many less steps in the present invention, as compared with the ATM approach.
Because there is no fragmentation of the original packet, except perhaps between successive SPEs, higher transfer 2o rates are achievable while using less computer resources and costs. Thus, transmitting a LAN
data packet as a contiguous data stream contributes to more efficient communications.
Fig. 10 shows more detail of an exemplary embodiment of step 92 of Fig. 9, in which the LAN packet is packed directly into a synchronous payload envelope. In step 100, a SONET
framer/deframer is controlled to communicate in a raw data mode. In step I O
1, the native preamble for a first LAN packet is packed into a SPE, followed by a packet length field for the first packet (step 102). Then, the data for the first LAN packet is packed (step 103). If there are no more LAN packets available at this time, a fill pattern is packed into the SPE and subsequent SPEs, until a next LAN packet is available (step 104). The fill pattern may be selected to be easily distinguishable from a LAN preamble, as will be discussed in more detail below. Once a 3o next LAN packet is available, the preamble is packed (step 105), the packet length field is packed (step 106), and the next LAN packet data is packed (step 107).

Fig. 11 is an exemplary embodiment of step 98 of Fig. 9, in which a LAN packet is unpacked from a synchronous payload envelope using information regarding the packet length.
Because the SONET framer/deframer is operating in a raw data mode, there may not be a specific signal indicating that a new packet is being received. Therefore, in one embodiment of the invention, a native preamble is detected within the raw data that is received from the SONET
framer/deframer (step 108). This preamble detection is usually performed by a device that is external to the SONET framer/deframer, so that the SONET framer/deframer is free to continue receiving the stream of raw data. Generally, a native (LAN) preamble includes alternating ones and zeros transmitted serially, but it is possible to use other sequences.
After the preamble has to been detected, the packet length field is provided from the SONET
framer/deframer.
Accordingly, in step 109, the packet length field is checked to determine the number of bytes in the LAN packet. Once the number of bytes in the LAN packet is known, the bytes may be provided to a LAN interface device (step 110). If a subsequent LAN packet is not transmitted immediately after a previous LAN packet, then a fill pattern may be received from the SONET
framer/deframer until a next preamble is detected (step 111 ).
Fig. 12 shows one approach to formatting a variable length LAN packet into a modified form for direct transmission as raw data over a SONET network. The modified packet 115 includes a LAN preamble 116, packet length field 117, and variable length LAN
data packet 118.
In one embodiment, the preamble includes 8 bytes, the packet length field includes 2 bytes, and 2o the variable length LAN data packet may include any number of bytes as determined by the packet length field 117.
Fig. 13 shows an example of how several modified LAN packets may be transmitted across a SONET network using a number of SPEs. For example, the SONET data stream may include a first synchronous transport frame 120, that includes a first SPE
121. The first SPE 121 includes path overhead 122 and data 123; data 123 is a combination of LAN data and fill data.
For example, the first SPE 12I may include a first modified LAN packet 130, which is followed by fill data 131. This is an example of a case in which there was no data to transmit from a first LAN to a second LAN from the time that the first LAN packet 130 was sent until a second LAN
packet is received. Following the fill data 131 is a second modified LAN
packet 132, which is 3o immediately followed by third modified LAN packet 133. In this example, because the third modified LAN packet 133 does not fit within the space still available in the SPE 121, only a first portion 133A of the third modified LAN packet is included within SPE 121.

Following the first synchronous transport frame 120 is a second synchronous transport frame 124, which includes a SPE 125 having path overhead 126 and data 127. The second SPE
125 includes a second portion 133B of the third modified LAN packet 133. No additional overhead is required to define this split between the first portion 133A and the second portion 133B because in the beginning of each modified LAN packet is the packet length field 117, which determines the length of the variable length LAN packet to follow. Thus, when the raw data is provided from the SONET framer/deframer, all that is required is to count the appropriate number of bytes to follow, even if these bytes are overlaid on two different synchronous payload envelopes, as shown in the example depicted in Fig. 13. Following the third modified LAN
1o packet 133 is a fourth modified LAN packet 134.
Fig. 14 is a detailed illustration of a SONET/LAN interface 73. In this embodiment, a "LAN to Raw Data/Framer" (LRDFRMR) 140 provides an interface between a "Switched LAN
Media Access Controller" (SLMAC) 142 and a "Raw Data to SONET Framer"
(RDSFRMR) 143. The RDSFRMR 143 is further coupled to a "Para11e11Serial and Serial/Parallel Converter with Clock Synthesizer" 145, which is further coupled to "Fiber Optic Transceiver" 146 and "Reference Clock" 147. The transceiver 146 interfaces with a SONET network 138, while the SLMAC 142 interfaces with a LAN 139. Additionally, "Host Processor" 144 provides control functions to coordinate the functionality of several of the elements of Fig.
14.
In this embodiment, the RDSFRMR 143 is a 622 Mbits/sec SONET Framer, Part No.
2o PM5355, available from PMC-Sierra, Burnaby, British Columbia, Canada; the LRDFRMR is a 20K field programmable gate array, Part No. A32200BX, available from Actel, Sunnyvale, California, USA; the Converter 145 is Part No. VCS8110, available from Vitesse, Camarillo, California, USA; and the Fiber Optic Transceiver 146 is Part No. HFBR5207, available from Hewlett-Packard, Burlington, Massachusetts, USA. The Host Processor 144 may be any general purpose processor, and the SLMAC 142 may be any device which provides appropriate interface with a LAN.
The LRDFRMR 140 may also be implemented as a processor, any combination of firmware or software, or may be embodied as an ASIC or combination of discrete elements. The components of the LRDFRMR 140 depicted in Fig. 14 are described below.
3o The Transmit FIFO Write Control Logic 1402 provides an interface with SLMAC

when data has been received from the LAN 139 by SLMAC 142. In particular, Transmit FIFO
Write Control Logic 1402 interfaces with a Transmit Packet Size Counter 1404 and a Transmit kl:\.W'W.I:I';'v \lll.\IIIL:, ut~ L:>-lay-:Ii CA 02260054 1999-O1-06 ~_n _'.I.II~ +1:l 23J '=:3:J:J-Ilt~i:il r _IZ_ FIFO 140ti. The Transmit FIFO Write Control Logic 1402 utilizes a clock emanating from a Clock Buffer 1408, wluch receives clock signals from SLM.4C 142.
The Transmit FIFO Read Control Logic 1410 provides data, that has been previously processed by the Transmit FIFO Write Control Logic 1402, to the RDSFRMR 143.
Such data may be pa~~-ticularly provided by Transmit Register 1412. Multiplexer 1414 selects specific data from the Transmit FIFO 1406, and Multiplexez 1416 selects either data from the Transmit FIFO
1406 or fill pattern data from the Fill Pattern Data Generator 1418.
The Receive FIFO Write Control Logic 1420 provides control when data is received from the SONLT network via the RDSFRMR 143. In particular, the Receive FIFO Write Control t o Logic 1420 controls the Preamble Detect Logic 1422, the Receive FIFO 1424, and the Receivo )?acket Size Counter 1426.
The Receive FIFO Read Control Logic 1430 then conuols the Receive FIFO 1424, and the Receive Register 1432, to provide the received data to SL~1AC 142.
Exemplary alteration of the structure depicted in Fig. 14 will be explained with respect to t s operation. of each of the Control Logic Elements I 402, 1410, 1420, and 1430. In particular, Fig.
is a flow process diagram of steps performed by the Transmit FIFO Write Control Logic 1402. The process begins by waiting for the SLMAC 142 to start a data transfer (step 1S0). T'nis rnay be determined as an initial state, by providing a reset signal. Upon receipt of a Transmit Lnable Signal (TXEN) from the SLMAC 142, the Transmit F1FO Write Control Logic 2o begins to load the data received from the LAN into the Transmit FIFO 140b, Step 151. In one embodiment, the SLMAC I42 also provides an indication ofthe packet size of the LAN packet.
Accordingly, in step LS2, the packet size word received from the SLMAC 142 is loaded into the Transmit Packet Size Counter 1404. Alternatively, the packet length of a LAN
packet may also be determined within the LRDFRMR 140.
In step 153, the Transmit Packet Size Counter 1404 is decremented while data is written to the Transmit FIFO 1406. Such operation would typically continue until the packet count reaches zero, indicated by PKT CNT = 0. However, if there is a war~stnit error, or if the Transnut FIFO becomes full, the process may proceed to step 154 in which an Error Latch is set. Then, if the Transmit FIFO is full, step 155 shows that data is written even though the Transmit FIFO
~0 1406 is full. In one embodiment, the data is actually discarded in step 155. Fzom step 155, if the Transmit FIFO 1406 is not still f..ul, then the process can proceed to step I53 again.
f1I'J~~i'1 ~F(, >I~F~r het. tc>v:U,l'\ vIi ~::,W11::~ m~ : I:;-tv--:WCA 02260054 1999-O1-06 ~-'~ ~VI
t-- +y:s rs:s '_; s:s:H (t:::~l ;i _I3, Alternatively, if the packet count reaches zero prior to the 'Transmit FIFO
1406 becoming full, than the process proceeds to step 156.
In step 156, the Transmit Enror Latch (TXER) is accessed to determine whether there was a transrrtit error. If there was no error, then in step I57, two bits of the Transmit FIFO may be set to indicate that the data transfer was successful. Alternatively, if there was a transmit error, then two bits from the Transmit FIFO may be set to indicate that an error occurred, Step 158. At3er either step 157 or step 158, the process returns to step 150, in which the system awaits new data from the LAN via the SLMAC 142.
Fig. 16 depicts steps of a process performed by an embodin~Ient of the Transmit FIFO
io Read Canirol Logic I4I0. rollowing a reset, or upon initialization, a periodic traasmit pulse is provided to the RDSFRMR 143 in step 160. The assertion of the periodic transmit pulse may be initiated in response to a timer signal such as Transmit Period (XMITPPD). If theze is no LAN
data to send, then the X11 pattern from Fill Pattern Generator 1418 is provided to the RI7SFRIIrIR
143 via the Transmit Register 1412. This will cause the R.DSFRN1R 143 to provide a fill pattern ~ s in each successive SPE, as described previously. During step I61, the Transmit FIFO 1406 is monitored to determine whether it is full, as indicated by an assertion by signal TXFFNEFI.
f Transmit FIFO Not F ulI). During this time, the periodic transmit pulse is continually asserted, by returning the process to step 160. I:Cthe Transmit FIFO 1446 is not full, then the process continues to step 162, where the data within the Transmit FTFO 1406 is transferred to the 2o RDSFRIvIR I43 via the MuItiplexers 1414, 141d, and Transmit Register 1412.
During step 162, status bits of the Transmit FIFO 1406 are monitored to determine the end of the packet as indicated by signal END~FPKT. Additionally, during step I
62, the periodic tTanSnlft pulse is also generated, Step 163, to maintain the RDSFRMR 143 running in the raw data mode. At tha end of the packet, the Transmit FIFO Read Control Logic 1410 checks to see 25 if any transmit errors occurred (step 164), If no errors occurred, then the last word of the data packet is sent to the RDSFRUfR (step 165). If there is an error, the fill pattern from the Fill Pattern Generator 1418 is sent to the RDSFRMR 143, as shown in step 166. After the final word is written in either step 165 or 166, then the process returns to step I61 which provides a fill pattern to the RDSFRMR I43.
3o Fig. 17 illustrates the process steps performed by the Receive FIFO Write Control Logic 1420, to receive data from the SO1V'ET network via RDSFRMR I43. The process begins when the RDSFRMR 143 provides an indication that it has data. For example, this may be indicated AMENDED SHEET

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_'.~.1I-' +.I;l ti:1 _:t:17111~;;:II :l ,_ by tile assertion of a Receive FIt~ O Nat Empty Flag Signal (RFFNempL). At this point, as shown in step 170, data is read from the RDSFRMR 143. In step 171, the Preamble Detect Logic 1422 monitors the sequence of data being read to determine whether there is a preamble.
If a preamble is not detected, then data may simply br discarded as shown in step I72. If, s however, there is a preamble detected, thw the process proceeds to step 173 in which the preamble is loaded into the Receive FIFO 1424. Additionally, the packet size word, previously referred to as Packet Length Field I I7, is loaded into the Receive FIFO 1424, as well as the Packet Size Counter 1426, Step 174.
In siep Z75, the words of the data received from the RDSFRIVRt 143 are loaded into the Io Receive FIFO 1424 while decrementing the contents ofthe Packet Size Counter 1426 and monitoring if it has expired to a count of zero, which, indicates the end of the packet has been reached. In this example, the data is received from the RDSFRMR 143 as 16-bit words. Various error indications may also be rzionitored during step 175. ror example, any error flags provided by the RDSFRMR may be monitored. Additionally, the Receive FIFO Empty Flag of the t 5 RpSFR.wlR may be monitored (RFFNe:npL), as well as the full flag of the Receive FIFO 1424 (RXFFflag). If either of these FIFQ flags are set, then the process may proceed to step 176, in which a Receive Error Latch is set, and then to step I 77, in which the process waits until the ecntents of the Packet Size Counter 1426 decrements. Ottee there is no more data to be loaded, as indicated by the contents of the Packet Size Counter 1426 being equal to zero, the Receive z0 Irrror Latch is checked to determine whether an error has occurred {step 178). If no error has occ~.irred, then the last word may be written to the Receive F1F0 1424, including setting error bits to indicate that no error occurred. Alternatively, if an error has occurred, than the last word may be written into the Receive FIFO 1424 with error bits set to indicate that an error has vccurrcd. From either step 179 or 18~, the process proceeds back to step 170.
2s Fig. 18 shows the process steps performed by the Receive FIFO Read Control Logic 1430. Initially, as shown in step 181, the process is idle until a signal is received indicating that the Receive FIFO is not empty (RXFFNEMPL). Once such a signal is received, in step 1~2, a signal may be provided to the SLMAC 142 to indicate that there is valid data which is being received from the RDSFh,MR 143 by the LRDFRMR 140. In the example shown in Fig. 14, this 3o is the Signal RSV. Aiso, during step 182, the data which is in the Rerxive FIFO 1424 is provided to the SLMAC 142 via the ReCEive Register 1432, Step 1.83. As indicted with respect to Fig. 17, the Receive FIFO 1424 may contain erxor bits indicating whether an error has ~~,~~n~~~nr~~~ >~.; ~ z ri~.s. .~i ,.i.i , ,;; : ,~,i;: , ~u, l.,- m-:~. CA 02260054 1999-O1-06 '='' -~ ~ ~ ' in.. ;s:s _;s:~:i.~-im:;: yo - IS -.V
occurred during the reception of data from the RDSFRIVIR 143. Accordingly, these error bits are checked in step 18.x. If there is no error, than in step 185 the final ward of the data packet is sent to the SLMAC. Alternatively, ifthere was an error bit sat, th°n a fill pattern may instead be sent to the SLMAC and a Receive Error Signal rrxay be inserted (RXER) to the SLMAC
I42, as s shown in step 186. Following either step 185 or 186, th.e Receive Data Valid Signal R.~V may be deasserted.
As described above, some SONLT FramerslDeframers may provide a natzve format transmit capability, as well as other transmit capabilities (e.g., ATM cell framing. In a particular embodiment that implements. the 50NET Framer/Def~amer as PMC-S
Terra Part No.
1o PM5355, an option is provided in which AT~I cell processing is disabled and raw data is either inserted or extracted to or from the SONET payload. To use the PM5355 in this mode, several register bits may be set to the respective values shown below:
'ts l,~g # Register Name Value l5 CDDIS OxSC RACP GFC/Misc. Control I

HCSADD 0x50 RACP Control 0 HCSPASS Ox~O RACP Control ~ 1 HCSI3 0x60 TACP Control 1 zo HCSADD 0x60 TACP Control 0 HCSPASS 0x60 TACP Control I

PASS Ox~O R.ACP Control 1 Such functionality may also be designed into a single ASIC which encompasses the functionality of the RDSFRMR 143 and the LRDFRMR 140 shown in Fig. 14.
Similarly, the 25 functions described above may be allocated to any of several architectural elements and combinations of hardware, software and firmware. For example, all ox airy portion of the functionality described with respect to Fig. 14 may be implemented as a general purpose processor which runs software to provide such functionality.
Fig. I9 illustrates another embodiment of tha invention, in which a data framer 19~
3o determines the packet size of a packet to be transmitted, so that this function need not be performed by a media access contzoller. As with the earlier examples, the packet size may be defined in one embodiment as a number of bytes. As illustrated in Fig. I 9, the data framer 19,2 also provides synclironi~ation between a SONirT framer/deframer 191 and a media access controller 193, so that these two devices may operate asynchronously and at flifferent speeds.

Figure 19 depicts more detail of this alternative SONET/LAN INTERFACE 73' (similar to interface 73 in Fig. 8). A SONET line transceiver 190 provides a physical interface with the SONET network. Coupled to the transceiver 190 is a SONET framer/deframer 191.
At the opposite end, a LAN media access controller (MAC) 193 has one interface coupled to the LAN.
"LAN to raw data framer" (LRDFRMR) 192 provides the interface between the framer/deframer 191 and the MAC controller 193.
In this embodiment, LRDFRMR 192 includes a transmit buffer 194 and transmit packet size control module 195. The control module 195 receives a LAN packet from MAC
controller 193, and transmits the packet to buffer 194 where it is stored. The control module 195 0 determines the size of the LAN packet once it has been completely stored in buffer 194. Such a feature eliminates a need for the MAC controller 193 to determine the size of the LAN packet and to append the packet length field to the LAN packet. LRDFRMR 192 also includes a receive buffer 196 that receives SONET packets from the SONET framer/deframer 191. via receive synchronization module 197. In the event that the SONET framer/deframer 191 and the MAC
controller 193 operate asynchronously or at different speeds, the receive buffer 196 stores at least a portion of the SONET packet prior to it being passed to the MAC controller 193, so that module 197 may provide the received packet at the appropriate speed and time to the MAC
controller 193.
Fig. 20 is a process flow diagram of transmit mode operation of LRDFRMR 192.
In step 201, LRDFRMR 192 begins receipt of a LAN packet from the MAC controller 193.
In step 202, LRDFRMR 192 begins storage of the LAN packet into the transmit buffer 194.
While the LAN
packet is being stored in buffer 194, a counter is incremented (step 203). In one embodiment, MAC controller 193 generates a transmit enable signal TXEN while sending the LAN packet.
While this signal is asserted data from the MAC 193 is stored in the buffer 194, and the control module 195 increments the counter to monitor the size of the LAN packet being stored. Once the LAN packet has been completely stored in buffer 194 (which may be indicated by the TXEN
signal being de-asserted), the counter value may be used as the packet length (step 204). Once the packet length has been determined, a preamble, packet length and the LAN
packet data itself may be transmitted to the SONET framer/deframer 191 (step 205).
Operation in the receive mode of the LRDFRMR 192 is illustrated in Fig. 21. In step 210, the receive synchronization module 197 detects a SONET packet in the raw data that is received from the SONET framer/deframer 191. In one embodiment, the SONET data rate is kc:E. W\:I~.I';v ',» ;:.:~.~;;I., ",; : t:; ;u-:WCA 02~26~0054 1999-O1~-06 ''"
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155.52 bits/sec, which yields an effective rate of I 9.44 Mbyteslsec at a continuous rate.
a However, the effective data rate which an exemplary IvIAC controller may receive data is only 12.5 Mbytes/scc. Therefore, it may be advantageous to provide a buffering mechanism such as buffer 195 to allow for this data rate difference. Thus, in step 21 U, the SQNET packet in the raw s data is received from the SONET fxamerldeframer 191 at a first data rate. In step 2I2, the receive synchronization module 197 begins storing the packet in the receive buffer 196 as the data is being received from the SONET framer 19I. As with earlier embodiments, the detection of the packet may be performed by a preamble detector. In step 214, the synchronization module 197 transfers data firom the receive buffer 196 to the MAC controller 193 at a second data rate ti , that is compatible with the MAC controller 193, until all of the packet is transmitted.
In one illustrative embodiment, the 80NET framcr/defrarner 191 is a PMC Sierra device (Part No. PM53~47), each of the transmit buffer 194 and the receive buffer 196 is a 4K x $ First In, First Out (FIFO), and the transmit packet size control module 19S and the receive synchronization module 197 arc both implemented within an Actel one-time field programmable ~ s gate array {FPGA) with 20,0U0 gates (Pan Na. 32200 DX-1). With rIFOs of this size, this embodiment can support packet lengths of 4096 bytes of Fast Etlzernet packets (100 M/byteslsee) over a SONET STS 3-C fiber at I55 Mbytes/see.
Fig. 22 is a detailed illustration of the alternative SONETIhA.~' interface 73'; in particular, detail is provided regarding a FPGA or ASIC (Application Specific Integrated Circuit) zo embodiment of the transmit packet size control module 195 and the receive synchn~nization module 197 of Fig. 19.
In this embodiment, an ASIC 220 provides an interface between a:vlAC
controller 222, which is also coupled to a LAN 221, and a "ltaw Data to SONET Framer" (R-DSFRN1R) 223.
The ASIC 220 referred to hexein gay be implemented as an FPGA or an ASIC, ar as a z5 combination of discrete devices. In at least one embodiment it is implemented as a one-time programmable FPGA. In another embodiment, it is implemented as a re-programmable FPGA
and is further coupled to a non-volatile memory device and circuitry to program the re-programmable FPGA fxom the memory. device upon power up of the circuit.
The RDSl~1~MR 223 is further coupled to a fiber optic transceiver 224, which provides an 3o interface to the SONET network 218. A reference clock 225 is also coupled to the RDSFRMR
223, and provides a 19.44 MHz reference. Additionally, a second reference clock 226 provides a 25 MHz reference tv the ASIC 220. In this embodiment, a 4K x 8 transmit FIFO
(TXFIFO 227) AI~tE"~IDED '~Iii:~T

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~y,l t_ +.1;~ c3;i _':s;i;ol~t~s ,: a l provides the functions of the transmit buffer 194 of rig. 1'9, and a 4K x &
receives FIFO
(RXFIFO 22$) provides the functions of the receive buffer 196 from Fig. I 9.
As with earlier embodiments, the functionality shown in 1~ lg. 19 may alternatively be provided by discrete circuitry, by soRware modules operating on a general purpose or a special purpose computer, or any combination therea;f.
In operation, a 4l8-bit Converter 229 within ASIG 220 receives LAN packets from the MAC controller 222, and provides this data through the Nlultiplexer TXWRpPMUX
230 and register FtEG 1 (231) to the transmit FIFO 227. While the packet is being loaded, the transmit right (TX WR) state machine 232 controls a 16-bit counter 233 to increment while the packet is 1o still being stored (i.e., while transmit enable TXEN is asserted). The 4/g-bit Converter 229 also translates the 4-bit nibbles received from MAC controller 222 into 8-bit bytes using register A
(2?4), register I3 (235), and input register INRLG (236). Once the data is loaded, the value in the 16-bit counter 233 is stored in a packet count queue FIFO 237, and also in the transmit read (TX
FD) state machine 238 which controls the transmit FIFO input register (TXFIFOII~ 239 to provide synchronization between the transmit FIFO 22~ and the RDSFRMR 223.
Additionally, register REG 3 (240) stores the value indicative of the packet length, so that a packet Length field may be provided to the RDSFRVIR through the ~ 1 (241) and transmit FIFO output register (TX FIFOOUT F~EG) 242. l~iultiplexer MUX 1 (241) also provides the packet data from the transmit FIFO 227 via the transmit FIFO input register 239 and also provides a till pattern from 2o the fill pattern re~~ister 243 when desirable.
Additionally, if an error is detected in the data stored in the transmit FIFO
242, then a bit may be set in a transmit error register (TX'ERR REG) 244, which in turn controls the multiplexer MUX 1 (241 ), to receive inverted data for the last byte of the packet data, which will in turn cause a CRC error when the packet is ultimately received.
Once the TX R.D down counter 245 has reached a value of zero, the TX RD state machine 238 determines that the transfer FIFO 227 has been emptied. The transmit receive (TX-RX) pulse generator 246 provides signals which in one embodiment controls light emitting diodes (LEl;7s) to indicate that data is being either transmitted or received.
In the receive mode, preamble detect logic 250 detects that a preamble has been received 3o by comparing the incoming data with a~known preamble value, and detects that a start of a packet has been recxived by comparing tht incoming data with a known Stark Of Field (SOF) delimiter value. Preamble register R.EG 1 (251) stores the known preamble value (e.g., SSI~ and preamble AMENDED SHEET

register REG 2 (252) stores the known SOF value delimiter (e.g., SDH), so that the preamble detect logic can access these registers for these known values. The preamble detect logic also activates the receive write (RX WR) state machine 253. The packet length field, which typically follows the SOF delimiter, is stored in a receive write (RX WR) counter 254, which data may also be provided to the RX WR state machine 253.
The packet data is stored in the receive FIFO 228 via register REG 8 (255), multiplexes MUX 3 (256), and register REG 9 (257). Once there is data in the receive FIFO
228, the receive read {RX RD) counter 258 controls the receive FIFO 228 to provide the receive packet data to the MAC 222 via register REG 10 (259), multiplexes MUX 4 (260), register REG
11 {261 ), 1o multiplexes MUX 5 (262), and register REG 12 (263). The RX RD counter 258 may also control MUX 4 (260) to provide the preamble from preamble REG 1 (251 ) and the SOF
delimiter from preamble REG 2 (252). Register REG 11 (261 ), together with multiplexes MUX 5 {262), provides a translation from 8-bit bytes to 4-bit nibbles.
As indicated in Fig. 22, various registers and additional inputs on many of the t 5 multiplexers may be used in combination to provide diagnostic capability for various segments of the ASIC 220.
Having thus described at least one illustrative embodiment of the invention, various modifications and improvements will readily occur to those skilled in the art and are intended to be within the scope of the invention. Accordingly, the foregoing description is by way of 2o example only, and not intended to be limiting.

Claims (16)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. An apparatus for transmitting data in packets having a first format dictated by a first protocol from a first network to a second network, comprising:
means for receiving a first packet of data in the first format from a source on the first network, the first packer of data having a variable length;
means for translating the first packet to a second packet of data which is a synchronous transport frame by directly inserting the first packet of data in the first format and a length of the first packet into the second packet of data; and means for transmitting the second packet across a third network which is a SONET network and is coupled between the first network and the second network, so that the second packet is received at the second network.

2. The apparatus of claim 1, wherein:
the first network is a local area network; and the means for receiving includes means far receiving the first packet from the local area network in a frame format which is native to the local area network.

3. The apparatus of claim 1, further comprising means for buffering the first packet of data to provide buffered data and means for determining the length of the first packet based upon the buffered data.

4. The apparatus of claim 1, wherein there is a transmission rate difference between the first and second networks and further comprising:
second means for receiving a third packet of data from a source on the second network;
means for buffering the third packet to account for the rate difference;
and second means for transmitting the third packet to a destination on the first network over the second network.

5. The apparatus of claim 1, wherein the means for transmitting includes means for transmitting a fill pattern across the third network when no packets are received from the first network.

6. In a computer-implemented method for transmitting packet data received from a first network in a native LAN format across a second network in a synchronous transport frame, the frame including a transport overhead and a synchronous payload envelope (SPE), the method comprising the step of:
transmitting a variable length packet received from the first network over the second network in the synchronous transport frame, where the SPE of the synchronous transport frame further includes a packet length field and the variable length packet in the native LAN format.

7. The method of claim 6, the method further comprising a step of transmitting a fill pattern when there are no pending frames to be sent in the synchronous transport frame.

8. The method of claim 6, further comprising a step of determining a packet length of the variable length packet.

9. The method of claim 8, wherein the step of determining the packet length includes receiving and storing the variable length packet in an input buffer.

10. The method of claim 6, wherein there is a transmission rate difference between the first and second networks and further comprising a step of receiving the packet from the first network at a first rate and wherein the step of transmitting is at a second rate.

11. The method of claim 10, wherein the step of transmitting includes a step of buffering data from the first network to account for the rate difference.

12. The method of claim 10, further comprising a step of:
transmitting the synchronous transport frame to a destination on a third network aver the second network.

13. The method of claim 6, further comprising the step of receiving the synchronous transfer frame at a third network.

14. The method of claim 13, wherein the step of receiving includes a step of extracting the variable length packet from the synchronous transport frame.

15. The method of claim 13, wherein the third network is a LAN.

16. In a computer-implemented method for transmitting packet data received from a first network in a native LAN format across a second network in a synchronous transport frame, the frame including a transport overhead and a synchronous payload envelope (SPE), the method comprising the steps of:
receiving a variable length packet from the first network over the second network in the synchronous transport frame, where the SPE the synchronous transport frame further includes a packet length field and the variable length packet in the native LAN format; and extracting the variable length packet from the synchronous transport from the synchronous transport frame, and providing the variable length packet to a LAN.