CA2273628A1 - Method for testability analysis and test point insertion at the rt-leve l of a hardware development language (hdl) specification - Google Patents

Method for testability analysis and test point insertion at the rt-leve l of a hardware development language (hdl) specification Download PDF

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Publication number
CA2273628A1
CA2273628A1 CA002273628A CA2273628A CA2273628A1 CA 2273628 A1 CA2273628 A1 CA 2273628A1 CA 002273628 A CA002273628 A CA 002273628A CA 2273628 A CA2273628 A CA 2273628A CA 2273628 A1 CA2273628 A1 CA 2273628A1
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CA
Canada
Prior art keywords
vhdl
testability
level
test point
directed acyclic
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002273628A
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French (fr)
Other versions
CA2273628C (en
Inventor
Samir Boubezari
Benoit Nadeau-Dostie
Eduard Cerny
Bozena Kaminska
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LogicVision Inc
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LogicVision Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LogicVision Inc filed Critical LogicVision Inc
Publication of CA2273628A1 publication Critical patent/CA2273628A1/en
Application granted granted Critical
Publication of CA2273628C publication Critical patent/CA2273628C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment

Abstract

A method of producing a synthesizable RT-Level VHDL specification for input to a synthesis tool to generate a gate-level circuit having testability enhancement, the method comprising the steps of developing a synthesizable RT-Level VHDL
specification representative of said circuit, analyzing said VHDL
specification to produce a VHDL Intermediate Format (VIF) representation; transforming said VIF
representation into a Directed Acyclic Graph (DAG); performing testability analysis on said Directed Acyclic Graph by computing and propagating Testability Measures (TMs) forward and backward through VHDL statements of said Directed Acyclic Graph; identifying the bits of each signals/variables on which faults are hard to detect; and performing test point insertion in said specification at the RT-Level by adding new VHDL test statements to improve testability.
CA002273628A 1998-06-16 1999-06-02 Method for testability analysis and test point insertion at the rt-leve l of a hardware development language (hdl) specification Expired - Fee Related CA2273628C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/098,555 1998-06-16
US09/098,555 US6363520B1 (en) 1998-06-16 1998-06-16 Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification

Publications (2)

Publication Number Publication Date
CA2273628A1 true CA2273628A1 (en) 1999-12-16
CA2273628C CA2273628C (en) 2002-05-14

Family

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Family Applications (1)

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CA002273628A Expired - Fee Related CA2273628C (en) 1998-06-16 1999-06-02 Method for testability analysis and test point insertion at the rt-leve l of a hardware development language (hdl) specification

Country Status (2)

Country Link
US (1) US6363520B1 (en)
CA (1) CA2273628C (en)

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US20190004928A1 (en) * 2015-12-21 2019-01-03 Safran Electronics & Defense Method for detecting computer module testability problems

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US6594816B1 (en) * 2001-06-05 2003-07-15 Cypress Semiconductor Corporation Method and an apparatus for synthesizing a programmable logic circuit
US6656751B2 (en) * 2001-11-13 2003-12-02 International Business Machines Corporation Self test method and device for dynamic voltage screen functionality improvement
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US20030154063A1 (en) * 2002-02-08 2003-08-14 Martin Lu Active path extraction for HDL code
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US6813751B2 (en) * 2002-07-16 2004-11-02 International Business Machines Corporation Creating standard VHDL test environments
US6922822B2 (en) * 2002-07-19 2005-07-26 Hewlett-Packard Development Company, L.P. Verifying proximity of ground vias to signal vias in an integrated circuit
US6807657B2 (en) * 2002-07-19 2004-10-19 Hewlett-Packard Development Company, L.P. Inter-signal proximity verification in an integrated circuit
US6769102B2 (en) * 2002-07-19 2004-07-27 Hewlett-Packard Development Company Verifying proximity of ground metal to signal traces in an integrated circuit
US7222317B1 (en) * 2004-04-09 2007-05-22 Calypto Designs Systems Circuit comparison by information loss matching
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US20050273683A1 (en) * 2004-06-07 2005-12-08 Logicvision, Inc. Insertion of embedded test in RTL to GDSII flow
US8205186B1 (en) 2005-04-11 2012-06-19 Synopsys, Inc. Incremental modification of instrumentation logic
JP4561992B2 (en) * 2005-07-29 2010-10-13 日本電気株式会社 Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method
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US20070276624A1 (en) * 2006-05-26 2007-11-29 Inventec Corporation Method for improving test suggestion report on electronic parts
US8495533B2 (en) * 2006-09-16 2013-07-23 International Business Machines Corporation Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing
US8365110B2 (en) * 2007-05-25 2013-01-29 The Regents Of The University Of Michigan Automatic error diagnosis and correction for RTL designs
US7689942B2 (en) * 2007-08-25 2010-03-30 International Business Machines Corporation Simultaneous power and timing optimization in integrated circuits by performing discrete actions on circuit components
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CN101877014B (en) * 2009-04-30 2012-07-25 国际商业机器公司 Method and device for detecting temporal constraint conflict
JP5267434B2 (en) * 2009-11-19 2013-08-21 富士通株式会社 Verification support program, verification support apparatus, and verification support method
JP2011112434A (en) * 2009-11-25 2011-06-09 Renesas Electronics Corp Method for inserting test point for logic circuit and logic circuit test apparatus
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US9979782B2 (en) 2015-03-24 2018-05-22 Qualcomm Incorporated Low-power and low-latency device enumeration with cartesian addressing
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US11714129B2 (en) 2020-08-26 2023-08-01 Duke University Observation point injection for integrated circuit testing
US11507720B1 (en) * 2021-06-11 2022-11-22 Cadence Design Systems, Inc. Systems and methods for signal observability rating
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190004928A1 (en) * 2015-12-21 2019-01-03 Safran Electronics & Defense Method for detecting computer module testability problems
US10394688B2 (en) * 2015-12-21 2019-08-27 Safran Electronics & Defense Method for detecting computer module testability problems

Also Published As

Publication number Publication date
CA2273628C (en) 2002-05-14
US6363520B1 (en) 2002-03-26

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