CA2289079A1 - Improved solder ball joint - Google Patents

Improved solder ball joint Download PDF

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Publication number
CA2289079A1
CA2289079A1 CA002289079A CA2289079A CA2289079A1 CA 2289079 A1 CA2289079 A1 CA 2289079A1 CA 002289079 A CA002289079 A CA 002289079A CA 2289079 A CA2289079 A CA 2289079A CA 2289079 A1 CA2289079 A1 CA 2289079A1
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Canada
Prior art keywords
substrate
metal
land
interconnection ball
package
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Abandoned
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CA002289079A
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French (fr)
Inventor
Anthony E. Panczak
Roy D. Hollaway
Thomas P. Glenn
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Amkor Technology Inc
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Individual
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Publication of CA2289079A1 publication Critical patent/CA2289079A1/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01067Holmium [Ho]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/0959Plated through-holes or plated blind vias filled with insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0094Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Abstract

An improved interconnection ball joint for a ball grid array integrated circuit package includes a substrate base (11) having a first surface to which an integrated circuit die (10) is affixed, and an opposite second surface. A metallized via (15) extends through the substrate. The via (15) has a central hole which extends through the substrate. The hole is plugged with a flexible nonconductive material, such as epoxy solder mask material. A metallic interconnection ball land (21) is on the second surface of the substrate, integral with the metallized via and adjacent to the hole and the plug of nonconductive material. A solder interconnection ball (22) is formed on the land, opposite the via and the plug of nonconductive material. A metal-to-metal annular bond is formed at the joint between the interconnection ball (22) and the land (21) around the plug of nonconductive material in the center of the via.

Description

IMPROVED SOLDER BALL JOINT

FIELD OF THE INVENTION
The present invention relates to integrated circuit packages, and in particular to a solder interconnection ball joint for ball grid array packages.
BACKGROUND OF THE INVENTION
Integrated circuit die are typically housed in closed packages. The packages include internal and external structures for electrically connecting the die in the package to external circuitry, e-a., a circuit board. One known type of package is a ball grid array ("BGA") package.
BGA packages characteristically have an array of solder interconnection balls, sometimes described as "bumps", in a selected pattern on a bottom external portion of the package. The interconnection balls are placed on metallic port~~ms of an external circuit board, heated, and upon re-solidifying, form conductive, metal-to-metal bonds with metallization or metal traces the circuit board.
BGA packages typically have a flat, insulating substrate base having first and second surfaces. The integrated circuit die enclosed in the package is above an interior first surface of the substrate. The substrate has a plurality of through-holes drilled between its interior (i.e., within the package) first surface and exterior second surface. The circumference of each drilled through-hole is lined throughout its entire length with metal, so that a conductive metallized via is formed between the interior and exterior surfaces of the substrate. The hole at the center of the via may become filled with epoxy solder mask material as a result of manufacturing steps which apply layers of epoxy solder mask material onto the surfaces of the substrate.
Metal conductive structures within the package, such as metal traces on the interior first surface of the substrate and bond wires, electrically connect the metal lining of each of the vias to contact pads on the die. At an opposite end of each via, at the exterior second surface of the substrate; the metal of the via is electrically connected to metal lines or traces on the exterior surface of t~~ substrate. These metal traces extend laterally away from the via to a flat metal interconnection ball land on the exterior surface of the substrate. Hence, the land is displaced from the metallized via.
A heated solder interconnection ball is placed on a the.exposed metal surface of the land. Upon re-solidification of the solder, an interconnection ball joint is formed at the intersection of the interconnection ball and the metal surface of the land.
The metal-to-metal bond between the interconnection ball and the land at the joint is uninterrupted, with no purposeful discontinuities or voids.
BGA packages having such uninterrupted metal-to-metal bonding at their interconnection ball joints are prone to electrical connectivity failures. Applicants have discovered, for example, in packages where solder interconnection balls are in an uninterrupted metal-to-metal bond with a nickel layer of an interconnect~.cn ball land, that the nickel layer tends to crack, causing a failure in the electrical connection between the interconnection ball and the package.
Accordingly, there is a need for a package, which ... ~ , r may be readily manufactured and is not susceptible, or is less susceptible, to failure by cracking at the metal-to-metal joint between a land on the package substrate and the interconnection ball.
SUMMARY OF INVENTION
Embodiments of an improved interconnection ball joint for a ball grid array ("BGA") integrated circuit package are disclosed. The joint has improved cracking resistance compared to the interconnection ball joints on conventional BGA packages.
The package has a substrate base. The substrate has a first surface and an opposite seconc: ~~~Yface.
The integrated circuit die is affixed, such as by a conventional adhesive, to the first surface of the substrate. A metal-lined via extends through the substrate from the first surface to the second surface of the substrate. This metallized via has a central hole, i.e., within the metal plating that lines the walls of the via. The hole extends throughout the length of the via, i.e., through the substrate from the first surface to the second surface of the substrate.
A planar metallic interconnection ball land is formed on the second surface of the substrate. The land is integral with the metal lining of the metallized via. The land is adjacent to and formed around the via and the hole.
The central hole within the metal lining of the via contains, at least adjacent to the land, a plug of a flexible nonconductive material, such as epoxy solder mask material. In the example, the plug of nonconductive material within the via extends throughout the entire length the hole through the substrate.
A metallic solder interconnection ball is placed symmetrically and accurately on the planar surface of the land, forming an interconnection ball joint. At the joint, the interconnection ball is centered on and opposite the metallized via and the plug of nonconductive material in the central hole of the via.
The interconnection ball forms a metal-to-metal annular bond with the land around the plug of nonconductive material in the central hole of the via.
In contrast with the interconnection ball joints of conventional BGA packages, which have uninterrupted metal-to-metal bonds at the joints between the interconnection balls and lands, joints in accordance with the present invention have a discontinuity in their metal-to-metal bonds. In the embodiments described herein, the metal-to-metal bonding at the joint occurs around the approximately circular surface of the plug of nonconductive material in the central hole of the metallized via.
Joints in accordance with the present invention unexpectedly demonstrate superior shearing strengths and cracking resistance, comparea 'o conventional interconnection ball joints, due to the presence of such discontinuities in the metal-to=metal bonding at the joint. This reduces thE. risk of electrical failure due to cracking at the joint. Moreover, the embodiments described herein achieve this result in a manner which allows miniaturization of the package itself, because the interconnection balls are placed directly below the conductive vias through the substrate, eliminating the need for some or all metal traces on the external lower substrate surface.
A example package employs a plurality of such interconnection ball joints. The integrated circuit die within the package is electrically connected to the interconnection balls by a conductive path that extends through the metallized vias and the interconnection ball lands. The die and the other structures on the _.. .._..__.._...,..~._. m,._ ..._ ... . ..~ ._. , . ~

first surface of the substrate are encapsulated in a conventional encapsulating material, such as plastic.
BRIEF DESCRIPTION OF DRAWINGS
Figure 1 is a cross-sectional side view of a portion of a BGA package, before encapsulation of the die and bond wires, which displays a single interconnection ball land prior to placement of an interconnection ball on the land.
Figure 2 is a top view of an interconnection ball land on the bottom external surface of a BGA package.
Figure 3 is a cross-sectional side view of a portion of a BGA package, before encapsulation of the die and bond wires, which displays a single interconnection ball joint.
Figure 4 is a cross-sectional side view of an integrated circuit package showing a plurality of interconnection ball joints.
DETAILED DESCRIPTION
Figure 1 shows relevant portions of an exemplary ZO BGA package in accordance with the present invention, before an interconnection ball is placed on the package and before encapsulation of the die and bond wires.
Substrate 11 is a substantially planar sheet of a nonconductive material. Substrate 11 forms an insulating base of the DGA package.
Substrate 11 has an upper first surface 12.
Inside the package, integrated circuit die l0 rests on and is affixed to upper first surface 12. Substrate 11 has a lower second surface 13, which is opposite upper first surface 12. Lower second surface 13 forms the external underside of the BGA package. Portions of upper first surface 12 and lower second surface 13 of substrate 11 are covered by layers 14 of a non-conductive epoxy solder masking material.
In this embodiment, substrate 11 is formed of a flat non-conductive laminate. An example thickness of _5_ substrate 11 is 0.36 mm to 0.56 mm, but the thickness rnay vary depending on the package application.
Examples of suitable laminates include Mitsubishi-BT, Arlon 45N, and Nellco BT. Alternatively, substrate 11 may be ceramic or insulated metal.
Metallized via 15 of Figure 1 is a metal-lined, epoxy-filled circular drill hole that extends though substrate 11, from upper first surface 12 to lower second surface 13. Lining the circumferential walls of via 15, throughout its length and about its entire circumference, is conductive metal plating 16. Within the metallized walls of via 15, throughout its length and adjacent to plating 16, is plug 17. Plug 17 fills the central hole within m~~-al lining 16 of via 15.
Plug 17 is formed of a compliant, non-conductive material. In the example of Figure 1, plug 17 is formed of epoxy solder mask material like layers 14.
However, the material of plug 17 does not necessarily have to be the same as the material of layers 14.
Metallized via 15 of Figure 1 may be formed by, first, drilling a circular hole through substrate 11.
An example drill hole diameter is approximately 0.3 mm.
Then, metal plating 16 is deposited on the walls of the drill hole, throughout its length and about its entire circumference, forming a conductive path through substrate 11. Metal plating 16 may be a layer of copper that is 0.0025 mm thick that is deposited by a conventional PTH copper plating process.
After the mer_al plating step, there is an unfilled hole at the approximate center of via 15, within metal plating 16. This central hole extends the length of via 15, from upper first surface 12 to lower second surface 13 of substrate 11. Plug 17 is formed in this central hole of via 15. Plug 17 may be formed during the formation of layers 14, or by a separate step particularly aimed at filling the hole within via 15.

~ m. T , r The shape, dimensions, and materials of via 15 may vary, depending on the packaging application. For example, the diameter of via 15 may be larger or smaller. If larger interconnection balls are used, then via 15 may have a larger diameter, and vice versa.
The desired size of the package and the reliability and electrical requirements of the package are also considerations in determining the size of via 15. As another example, instead of copper, metal plating 16 may be another metal, such as gold. As a final example, instead of epoxy solder mask material, plug 17 can be formed of a different material that is compliant, non-conductive, and does not fern a. bond with the metal of the land or interconnection ball. An alternative material for plug 17 is silicone, which is readily obtainable from the Dow Corning Company, among other sources.
At the intersection of via 15 and upper first surface 12 of substrate 11, via 15 is electrically connected to a conductive metal trace denoted as metallization 18, which extends laterally away from via 15 on upper first surface 12 of substrate 11. An opposite second end of metallization 18 is electrically connected to a conductive metal contact 19, which in turn is connected by a conductive bond wire 20 to a conductive bonding pad on die 10. Thus, there is a conductive path between die 10 and metal plating 16 of via 15. There are a variety of alternative, conventional ways to effect such an electrical connection, such as with tape automated bonding or a flip-chip configuration.
Returning to Figure 1, a conductive approximately planar metal interconnection ball land 21 is formed around via 15, at the intersection of via 15 with lower second surface 13 of substrate 11. The metal of land 21 is integral with metal lining 16 of via 15, ensuring _7_ electrical connectivity, and is around plug 17. In the embodiment of Figure 1, land 21 is formed of substantially planar layers of three different metals.
Beginning at lower second surface 13 of substrate 11, these metal layers include: an underlying first metal layer 23, which is connected to plating 16 of via 15;
an intermediate second metal layer 24; and a topmost third metal layer 25.
As examples, layer 23 may be copper that is approximately 0.019 mm to 0.038 mm thick; intermediate layer 24 may be nickel that is approximately 0.005 mm thick; and topmost layer 25 may be gold that is approximately 0.0005 mm thick. Each of these copper, nickel, and gold layers may be deposited on substrate 11 by conventional electrcplating methods, such as the Learonal method.
In Figure 1, the metal plane of land 41 has a discontinuity, specifically a circular hole, at its center. The hole is the center portion of via 15, which is adjacent to land 21 and ~~lled with nonconductive epoxy solder mask material (i.e., plug 17). The exposed surface of plug 17, near lower second surface 13 of substrate 11 and adjacent to land 21, is substantially planar across via 15 and is approximately flush with the adjacent layer 25 of land 21. In an alternative embodiment, the exposed surface of plug 17 may be slightly below the adjacent metal surface of layer 25 of land 21.
Figure 2 is a top view of land 21 of Figure 1.
Land 21 is depicted as having an overall circular shape, although it may have other shapes, such as a square shape, depending on the application. The exposed surface of plug 17 of via 15 is adjacent to and at the approximate center of the metal surface of land 21. Layer 25 of land 21 is exposed in this view. Land 21 surrounds plug 17, and is electrically connected to _g_ ..,.... . .. ..._.... ..__..,.W.~»._, ..~.......... ... T. .. . ~.. , .~,.

metal plating 16 of via 15. Accordingly, there is a conductive path between land 21 and die 10 through metal plating 16 of via 15.
Figure 3 shows an embodiment, in accordance with . 5 the present invention, of an interconnection ball ~_oint 30, which was formed by the placement of a solder interconnection ball onto land 21 of Figures 1 and 2.
Annular joint 30 is formed at t~:e intQrsection of interconnection ball 22, interconnection ball land 21, and nonconductive plug 17. A conductive metal-to-metal annular bond forms around the circular plug 17 of nonconductive epoxy solder mask material, which is contained within via 15, near lower second surface 13 of substrate 11 and adjacent to land 21. A conductive path exists between interconnection ball 22 and die 10 through land 21, via 15, and the other conductive structures described above. The shape of the perimeter of the annular joint and bond may vary, for example, according to the shape of the interconnection ball.
For example, the outer periphery of the resultant annular joint may be rectilinear, and t-_he inner periphery of the annular joint may be circular.
Interconnection ball 22 serves as a conductive connection point between the BGA package and an external circuit board root shown>.
In the embodiment of Figure 3, interconnection ball 22 is formed of eutectic 63/37 tin/lead solder.
Alternatively, other solders may be used to form interconnection ball 22, such as non-eutectic tin/lead solder, non-lead solders, or other low melting point solders formed of a metal or an alloy of metals.
In the example of Figure 3, the eutectic solder of interconnection ball 22 is shaped, heated, and placed onto land 21. Upon re-solidification of the solder, a metal-to-metal annular bond is formed about circular plug 17 between interconnection ball 22 and land 21 (see Figure 2).
Where metal layers 23, 24, and 25 of land 21 are copper, nickel, and gold, respectively, as in the example described above, the metal-to-metal bond at joint 30 is primarily between the nickel intermediate layer 24 and the eutectic tin/lead solder of interconnection ball 22, because all or most of gold layer 25 dissolves into the solder. Accordingly, Figure 3 does not show gold layer 25.
Joint 30 of Figure 3 does not have an uninterrupted metal-to-metal bond like the interconnection ball joints of the conventional BGA
packages described above. Circular plug 17 in via 15 is at the approximate c~n~Cr of land 21 (see Figure 2) and joint 30. Because of this epoxy-filled circular hole in the metal horizontal plane of land 21, there is a circular discontinuity in the metal-to-metal bonding at joint 30. Interconnection ball 22 forms a metal-to-metal annular bond with the planar metal surface of land 21 about plug 17, but does not bond with the nonconductive surface of plug 17.
Applicants have discovered that interconnection ball joints, such as the example of Figure 3, having a discontinuity in the metal-to-metal bonding between the interconnection ball and the metal land demonstrate significantly higher shearing strengths than the uninterrupted metal-to-metal joints of conventional BGA
packages. This result is unexpected, assuming similar size interconnection ball lands, because the area of the metal-to-metal bond of the interconnection ball joint is smaller. Applicants hypothesize that the discontinuity in the metal-to-metal bond (i.e., the central hole of via 15, which is filled with plug 17 of a non-conductive material) functions Like a hole drilled in a glass automobile windshield at the tip of __...w . ._~._.---.._...~ ... ._ .. . .~. . i . t WO 98/53498 PCTlUS98/09214 a propagating crack. The hole stops the crack from propagating further. In the case of Figure 1, joint 30 reduces the risk of electrical connectivity failures due to, for example, cracking of nickel layer 24.

The embodiment of Figure 3 is particularly suited for current and future BGA packaging applications, because of its efficient, compact design. By placing interconnection ball 22 onto land 21, opposite and directly below via 15 and plug 17, and by using via 15 l0 as the discontinuity in land 21, metal traces on the Lower surface of the BGA package can be eliminated.

This reduces the package's surface area and cost.

Figure 4 is a cross-sectional side view of an exemplary integrated circuit package 40 employing interconnection ball joints in accordance with the present invention. Figure 4 includes components described above with respect to Figures 1-3. For clarity, Figure 4 only shows two of bond wires 20, contacts 19, metal traces 18, vias 15, interconnection balls 22, and joints 30, although many more of these structure may exist in a typical package, depending on the particular packaging application. Also for clarity, layers 14 and plug 17 are not shown.

Figure 4 shows encapsulating material 41, which covers and seals die 10, bond wires 20, contacts 19, metal trace 18, and the remainder of first surface 12 of substrate 11 within package 40. Encapsulating material 41 may be, for example, plastic, such as an epoxy resin or other resin conventionally used in semiconductor packages for encapsulation.

The above-described embodiments are exemplary.

Other embodiments, within the scope of the claims below, will be apparent to those skilled in the art.

Claims (13)

1. An interconnection ball joint in an integrated circuit package comprising:
a substrate having a first surface and an opposite second surface;
a metallized via extending through the substrate from the first surface to the second surface of the substrate, said via including a central hole which extends from the first surface to the second surface of the substrate;
a metallic interconnection ball land, on the second surface of the substrate, integral with the metallized via and adjacent to the hole;
the hole containing a nonconductive material plugging the hole adjacent to the land;
a metallic solder interconnection ball; and wherein the interconnection ball is in a metal-to-metal annular bond with the land around the hole.
2. The interconnection ball point of claim 1, wherein the land includes layers of different metals.
3. The interconnection ball joint of claim 2, wherein the land includes a layer of nickel and a layer of copper.
4. The interconnection ball joint of claim 3, wherein the nonconductive material is an epoxy material.
5. The interconnection ball joint of claim 1, wherein the nonconductive material is an epoxy material.
6. A package for an integrated circuit comprising:

a substrate having a first surface and an opposite second surface;
an integrated circuit die affixed to the first surface;
a metallized via extending through the substrate from the first surface to the second surface of the substrate, said via including a central hole which extends from the first surface ro the second surface of the substrate;
a metallic interconnection ball land, on the second surface of the substrate, integral with the metallized via and adjacent to the hole;
the hole containing a nonconductive material plugging the hole adjacent to the land;
a metallic solder interconnection ball;
wherein the interconnection ball is in a metal-to-metal annular bond with the land around the hole; and wherein the interconnection ball is electrically connected to the integrated circuit die by a conductive path which extends through the metallized via.
7. The package of Claim 6, wherein the land includes layers of different metals.
8. The package of Claim 7, wherein the land includes a layer of nickel and a layer of copper.
9. The package of claim 7, wherein the nonconductive material is an epoxy material.
10. The package of claim 6, wherein the nonconductive material is an epoxy material.
11. The package of Claim 10, wherein the conductive path includes a metal trace on the first surface of said substrate, and a metal bond wire.
12. The package of claim 12, further comprising an encapsulating material, wherein the encapsulating material covers the integrated circuit die, the metal trace, the bond wire, and the first surface of the substrate.
13. The package of claim Z2, wherein the land includes a layer of nickel and a layer of copper.
CA002289079A 1997-05-23 1998-05-13 Improved solder ball joint Abandoned CA2289079A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/862,687 1997-05-23
US08/862,687 US5796163A (en) 1997-05-23 1997-05-23 Solder ball joint
PCT/US1998/009214 WO1998053498A1 (en) 1997-05-23 1998-05-13 Improved solder ball joint

Publications (1)

Publication Number Publication Date
CA2289079A1 true CA2289079A1 (en) 1998-11-26

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CA002289079A Abandoned CA2289079A1 (en) 1997-05-23 1998-05-13 Improved solder ball joint

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US (1) US5796163A (en)
EP (1) EP1018157A1 (en)
JP (1) JP2001526002A (en)
KR (1) KR20010012494A (en)
AU (1) AU7565298A (en)
CA (1) CA2289079A1 (en)
WO (1) WO1998053498A1 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5936848A (en) * 1995-12-20 1999-08-10 Intel Corporation Electronics package that has a substrate with an array of hollow vias and solder balls that are eccentrically located on the vias
JPH1174651A (en) * 1997-03-13 1999-03-16 Ibiden Co Ltd Printed wiring board and its manufacture
JP3420706B2 (en) * 1998-09-22 2003-06-30 株式会社東芝 Semiconductor device, method of manufacturing semiconductor device, circuit board, and method of manufacturing circuit board
US6248961B1 (en) * 1998-12-15 2001-06-19 International Business Machines Corporation Wave solder application for ball grid array modules and solder plug
US6316952B1 (en) 1999-05-12 2001-11-13 Micron Technology, Inc. Flexible conductive structures and method
KR100368025B1 (en) 2000-09-26 2003-01-15 삼성전자 주식회사 Ciruict board having center-directional package land types and ball grid array package using the circuit board
US7015072B2 (en) 2001-07-11 2006-03-21 Asat Limited Method of manufacturing an enhanced thermal dissipation integrated circuit package
US6734552B2 (en) 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
US6790710B2 (en) * 2002-01-31 2004-09-14 Asat Limited Method of manufacturing an integrated circuit package
US20030034175A1 (en) * 2001-08-20 2003-02-20 Honeywell Advanced Circuits, Inc. Configurations and methods for improved copper distribution uniformity in printed wiring boards
KR100763963B1 (en) * 2001-08-21 2007-10-05 삼성테크윈 주식회사 TBGA Semiconductor Package and the fabrication method thereof
US6683468B1 (en) * 2001-08-29 2004-01-27 Cypress Semiconductor Corporation Method and apparatus for coupling to a device packaged using a ball grid array
US20030178719A1 (en) * 2002-03-22 2003-09-25 Combs Edward G. Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package
US6940154B2 (en) * 2002-06-24 2005-09-06 Asat Limited Integrated circuit package and method of manufacturing the integrated circuit package
US7294929B2 (en) * 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
JP4426900B2 (en) * 2004-05-10 2010-03-03 三井金属鉱業株式会社 Printed wiring board, manufacturing method thereof, and semiconductor device
US7097462B2 (en) * 2004-06-29 2006-08-29 Intel Corporation Patch substrate for external connection
JP3801188B2 (en) * 2004-09-06 2006-07-26 セイコーエプソン株式会社 Semiconductor device and manufacturing method of semiconductor device
US7718927B2 (en) * 2005-03-15 2010-05-18 Medconx, Inc. Micro solder pot
US8399291B2 (en) * 2005-06-29 2013-03-19 Intel Corporation Underfill device and method
US20070045844A1 (en) 2005-08-24 2007-03-01 Andry Paul S Alpha particle shields in chip packaging
CN101409273B (en) * 2007-10-08 2010-12-08 全懋精密科技股份有限公司 Ball-placing side surface structure for package substrate and manufacturing method thereof
US7749887B2 (en) * 2007-12-18 2010-07-06 Micron Technology, Inc. Methods of fluxless micro-piercing of solder balls, and resulting devices
US20090188710A1 (en) * 2008-01-30 2009-07-30 Cisco Technology, Inc. System and method for forming filled vias and plated through holes
KR20100033012A (en) * 2008-09-19 2010-03-29 주식회사 하이닉스반도체 Semiconductor package and stacked semiconductor package having the same
KR100999515B1 (en) * 2008-11-14 2010-12-09 삼성전기주식회사 Manufacturing method of printed circuit board
KR101633373B1 (en) * 2012-01-09 2016-06-24 삼성전자 주식회사 COF package and semiconductor comprising the same
US9236339B2 (en) 2012-05-31 2016-01-12 Samsung Electro-Mechanics Co., Ltd. Plug via stacked structure, stacked substrate having via stacked structure and manufacturing method thereof
US20220312591A1 (en) * 2021-03-26 2022-09-29 Juniper Networks, Inc. Substrate with conductive pads and conductive layers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241133A (en) * 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5450290A (en) * 1993-02-01 1995-09-12 International Business Machines Corporation Printed circuit board with aligned connections and method of making same
JP3377867B2 (en) * 1994-08-12 2003-02-17 京セラ株式会社 Package for storing semiconductor elements
JP3123638B2 (en) * 1995-09-25 2001-01-15 株式会社三井ハイテック Semiconductor device
US5689091A (en) * 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure

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JP2001526002A (en) 2001-12-11
US5796163A (en) 1998-08-18
AU7565298A (en) 1998-12-11
KR20010012494A (en) 2001-02-15
WO1998053498A1 (en) 1998-11-26
EP1018157A1 (en) 2000-07-12

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