CA2293241C - Adaptive biasing in a power amplifier - Google Patents
Adaptive biasing in a power amplifier Download PDFInfo
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- CA2293241C CA2293241C CA002293241A CA2293241A CA2293241C CA 2293241 C CA2293241 C CA 2293241C CA 002293241 A CA002293241 A CA 002293241A CA 2293241 A CA2293241 A CA 2293241A CA 2293241 C CA2293241 C CA 2293241C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
Abstract
The invention relates to an amplifier arrangement for amplifying an input signal (20) using a distorting main power amplifier (14) such as one operating as a class AB amplifier. The amplifier can be biased at different operating points. The method and apparatus modify bias control signals to the main amplifier (14) to reduce or minimize the distortion energy added by the main power amplifier (14). A digitally controlled processor (90) iteratively modifies various control bias signals to adjust the output (18) of the amplifier. Different gain (26, 52, 60, 66) and phase (28, 62, 68) control elements can also be iteratively updated at different rates.
Description
ADAPTIVE BIASING IN A POWER AMPLIFIER
Backcrround of the Invention The invention relates generally to power amplifiers, and in particular to minimizing distortion in the input/output transfer function for amplifiers, particularly high power class AB power amplifiers.
High power, broad band power amplifiers are well known. These amplifiers may operate in a feed forward configuration, or may have other forms of linearization which are required when the main power amplifier operates, for example, as a class AB amplifier. Although class A amplifiers usually produce less distortion than class AB amplifiers, class A amplifiers are also less efficient than class AB amplifiers. Thus, in order to retain the advantages of efficiency while minimizing distortion, class AB amplifier configurations have been developed which implement various forms of error or distortion correction.
For example, one form of error correction attempts to distort the input signal in a manner which compensates for the distortions of the class AB amplifier. Thus, a predistortion circuit can be provided with various manual adjustments to produce a distortion signal from the original signal, so that when the distortion signal is combined with the input signal, and the combination is input to the power amplifier, operating for example, as a class AB amplifier, the output is substantially a linear amplification of the original input signal to the amplifier arrangement.
Such predistortion circuities typically employ a low power amplifier, preferably having the same general distortion characteristics as the main amplifier, so that its output, properly processed, can be used to obtain the necessary distortion components required to be combined with the input signal to the predistortion circuitry to generate a predistorted input to the main amplifier.
Such configurations operate to substantially reduce the intermodulation frequency distortions produced by a class AB amplifier when the variable elements of the predistortion circuitry are properly adjusted.
However, even in properly adjusted amplifier arrangements using predistortion, a certain amount of instability can be observed. For many amplifiers operating in a Class AB mode, the bias point of the amplifier can affect the distortion it produces.
Further, in current lateral MOSFET's operating as a class AB amplifier, amplifier component drift can be caused by temperature transients, and if the amplifier characteristics are sensitive to average power input, there can be further amplifier instability. Typically, however, these parameters are relatively slowly varying (for example a typical response time would be on the order of one millisecond); and even a low bandwidth amplifier has a signal bandwidth of one megahertz which corresponds to a period of one microsecond. While these instabilities have been attended to in a feed forward cancellation loop circuitry, for example, they are not adequately handled at the power amplifier itself.
Thus, the invention provides an advantageous approach toward maintaining stability in the input/output relationship of a high power class AB power amplifier arrangement. There results better linear stability over time and lower intermodulation distortions in the amplifier output.
Summarv of the Invention The invention relates to an amplifier arrangement for amplifying an input signal. The amplifier arrangement features a main amplifier (typically a class AB amplifier), an error loop including a comparator which differences a delayed derivative of the input signal to the amplifier arrangement with a signal representative of the output of the main amplifier to produce an error signal, a first distortion controlled feedback loop including a detector for receiving the error signal and generating a detected error signal output dependent upon the energy in said error signal, and a bias signal generation circuit for generating at least one bias control signal for optimally setting the bias point of the main amplifier. The bias signal generation circuit has a signal correction circuit for receiving the detected error signal output and for generating a bias control signal. The main amplifier is responsive to the bias control signal for changing its operating point for reducing distortion in its output.
In another aspect of the invention, the error loop features an error loop delay circuit connected to receive a signal derived from the input signal to be amplified and an error loop phase and amplitude correction circuit connected in series with the error loop delay circuit, the error loop delay circuit and the error loop phase and gain correction circuits together generating the delayed derivative of the input signal.
The amplifier arrangement further features a detector which, in one embodiment, has an energy measurement circuit for measuring the energy in the error signal and a compensation circuit which has a control processor responsive to the energy measurement circuit for iteratively adjusting the error correction circuitry bias control signal. Preferably, the control processor also operates cyclicly for adjusting a phase correction control circuit and then a gain correction control circuit in the error loop, in a continuously repeating pattern, to reduce the error signal.
Backcrround of the Invention The invention relates generally to power amplifiers, and in particular to minimizing distortion in the input/output transfer function for amplifiers, particularly high power class AB power amplifiers.
High power, broad band power amplifiers are well known. These amplifiers may operate in a feed forward configuration, or may have other forms of linearization which are required when the main power amplifier operates, for example, as a class AB amplifier. Although class A amplifiers usually produce less distortion than class AB amplifiers, class A amplifiers are also less efficient than class AB amplifiers. Thus, in order to retain the advantages of efficiency while minimizing distortion, class AB amplifier configurations have been developed which implement various forms of error or distortion correction.
For example, one form of error correction attempts to distort the input signal in a manner which compensates for the distortions of the class AB amplifier. Thus, a predistortion circuit can be provided with various manual adjustments to produce a distortion signal from the original signal, so that when the distortion signal is combined with the input signal, and the combination is input to the power amplifier, operating for example, as a class AB amplifier, the output is substantially a linear amplification of the original input signal to the amplifier arrangement.
Such predistortion circuities typically employ a low power amplifier, preferably having the same general distortion characteristics as the main amplifier, so that its output, properly processed, can be used to obtain the necessary distortion components required to be combined with the input signal to the predistortion circuitry to generate a predistorted input to the main amplifier.
Such configurations operate to substantially reduce the intermodulation frequency distortions produced by a class AB amplifier when the variable elements of the predistortion circuitry are properly adjusted.
However, even in properly adjusted amplifier arrangements using predistortion, a certain amount of instability can be observed. For many amplifiers operating in a Class AB mode, the bias point of the amplifier can affect the distortion it produces.
Further, in current lateral MOSFET's operating as a class AB amplifier, amplifier component drift can be caused by temperature transients, and if the amplifier characteristics are sensitive to average power input, there can be further amplifier instability. Typically, however, these parameters are relatively slowly varying (for example a typical response time would be on the order of one millisecond); and even a low bandwidth amplifier has a signal bandwidth of one megahertz which corresponds to a period of one microsecond. While these instabilities have been attended to in a feed forward cancellation loop circuitry, for example, they are not adequately handled at the power amplifier itself.
Thus, the invention provides an advantageous approach toward maintaining stability in the input/output relationship of a high power class AB power amplifier arrangement. There results better linear stability over time and lower intermodulation distortions in the amplifier output.
Summarv of the Invention The invention relates to an amplifier arrangement for amplifying an input signal. The amplifier arrangement features a main amplifier (typically a class AB amplifier), an error loop including a comparator which differences a delayed derivative of the input signal to the amplifier arrangement with a signal representative of the output of the main amplifier to produce an error signal, a first distortion controlled feedback loop including a detector for receiving the error signal and generating a detected error signal output dependent upon the energy in said error signal, and a bias signal generation circuit for generating at least one bias control signal for optimally setting the bias point of the main amplifier. The bias signal generation circuit has a signal correction circuit for receiving the detected error signal output and for generating a bias control signal. The main amplifier is responsive to the bias control signal for changing its operating point for reducing distortion in its output.
In another aspect of the invention, the error loop features an error loop delay circuit connected to receive a signal derived from the input signal to be amplified and an error loop phase and amplitude correction circuit connected in series with the error loop delay circuit, the error loop delay circuit and the error loop phase and gain correction circuits together generating the delayed derivative of the input signal.
The amplifier arrangement further features a detector which, in one embodiment, has an energy measurement circuit for measuring the energy in the error signal and a compensation circuit which has a control processor responsive to the energy measurement circuit for iteratively adjusting the error correction circuitry bias control signal. Preferably, the control processor also operates cyclicly for adjusting a phase correction control circuit and then a gain correction control circuit in the error loop, in a continuously repeating pattern, to reduce the error signal.
The method of the invention relates to minimizing distortion energy in an amplified signal output from a main amplifier (preferable operating as a class AB
amplifier) which is part of an amplifier arrangement having an input and an output. The method features the steps of generating an amplifier output signal from the amplifier arrangement; generating an error signal from the output of the main amplifier representing a distortion error energy, and iteratively and successively correcting, using a digitally controlled processor responsive at least to signals derived from the error signal, bias control signals to at least one of the main amplifier and phase and gain adjustments in an error loop.
In various aspects of the invention, the error signal generating step features comparing a signal derived from the output of the main amplifier and a signal derived from the input signal to the amplifier arrangement, generating a difference signal, and then measuring an energy content of a signal derived from the difference signal.
The invention thus advantageously biases, in a dynamic manner, the input bias control signal to a class AB or other distorting main amplifier or active devices) and thereby causes a substantial minimization of the distortion characteristics of the entire amplifier arrangement. The dynamic character of the system also adjusts for various instabilities including those caused by temperature, signal level, and component drift.
Brief Description of the Drawings Other objects, features, and advantages of the invention will be apparent from the following description, taken together with the drawings in which:
Figure 1 is a schematic block diagram of an embodiment of the predistorter amplifier and control circuitry illustrating one aspect of distortion minimization in accordance with the invention;
Figure 2 is a flow chart illustrating operation of the digitally controlled processor in accordance with the invention; and Figure 3 is a simplified schematic diagram illustrating bias control according to the invention.
Description of the Preferred Embodiments Referring to Figure l, an amplifier arrangement 10 has a predistortion circuitry 12, a main power amplifier 14, and a control circuitry 16. Amplifier 14 is typically a high power class AB amplifier whose output over a line 18 can be either used directly, or can be the input to a feed forward distortion cancellation circuitry such as that described in my copending U.S. Patent No. 5,796,304, entitled BROADBAND AMPLIFIER WITH QUADRATURE PILOT SIGNAL.
The input to the amplifier arrangement, over a line 20, is split (or sampled) for a number of purposes.
First, a line sampling coupler 22 directs part of the input signal to a delay element 24. The output of the delay element is directed to a controlled gain circuitry 26 and from there to a controlled phase circuitry 28. The output of the phase circuitry 28 is passed to a comparison device 30. (The processing order of delay 24, and circuitries 26, 28 is not important).
The remaining input signal over line 36 is sampled by another coupler 38 and the output of coupler 38 is received by a signal sp utter 40 which divides the signal equally for output over lines 42 and 44. The remaining -5a-input signal from line 36 is directed to a delay element 46.
The output of sp utter 40 over line 42 is directed to a delay element 48, the output of which is received by comparison circuitry 50. The other output of sp utter 40 over line 44 is received by a gain controlled amplifier 52, the output of which is directed to an auxiliary amplifier 54. The output of amplifier 54 is received by a controlled gain circuitry 60. The output of controlled gain circuitry 60 is delivered to a controlled phase circuitry 62 the output of which is compared with the signal from delay element 48 in comparison circuitry 50.
The difference between the two signals, representing distortion components introduced primarily by amplifier 54, is passed through a linear amplifier 64 to a controlled gain circuit 66. The output of the control gain circuit 66 is received by a controlled phase circuit 68. The output of the controlled phase circuit 68 is delivered to a coupler 70 which combines the output of the phase circuit 68 with the output of the delay element 46, to generate an input, over a line 72, to the main power amplifier 14.
The output of the main power amplifier 14, over a line 74, is sampled by a coupler 76 and the sampled output signal is compared (differenced) to the output of the phase controlled circuit 28 available over a line 78, to generate a distortion error signal on a line 80. The distortion error signal over line 80 is amplified using amplifiers 82 and 84, connected in series with each other, and the output of amplifier 84 is detected, here using a Schottky diode 86 to measure the energy in the signal, for input to a digital controller 90. The digital controller 90 outputs, in this illustrated embodiment, seven digital signals over lines 92a, 92b, 94a, 94b, 96, 98a, and 98b to control digital to analog (D/A) converters 100a, 100b, 102a, 102b, 104, 106a, and 106b, respectively. The analog outputs of the digital to analog converters are directed to control the various gain and phase elements of the predistortor circuitry 12 and the feedback control circuitry gain and phase 26 and 28.
The output of the comparison circuit 50, amplified by amplifier 64 to give it a proper signal value for eventual coupling into the output from the delay element 46, is sampled by a coupler 118. The output of the coupler, like the output of comparison circuitry 30, is passed through a pair of amplifiers 120, 122, and is detected at the output of amplifier 122, in the illustrated embodiment of the invention, using a Schottky diode 124, which provides a measure of the energy in the signal output of amplifier 122. That energy value is received by the controller 90 which uses that value to adjust and control the value of the gain at circuits 52 and 60, and the phase correction at circuit 64.
The circuit arrangement 10 thus has three loops in operation. One loop the first distortion loop, includes delay 48, amplifier 52, auxiliary amplifier 54, gain and phase correction circuits 60 and 62, and comparison circuitry 50. The second distortion loop includes those previous elements, and further, linear amplifier 64, and gain and phase correction circuits 66 and 68, along with delay 46. The system error loop includes those previously identified elements plus the main amplifier 14, delay 24, gain and phase correction elements 26 and 28, and comparison circuitry 30. The loops are controlled by the error correction circuitry including the processor 90, the A-to-D's 100a, 100b, 102a, 102b, 104, 106a, and 106b, the amplifiers 82, 84, 120, 122, and the detection elements, here the Schottky diodes, 86 and 124.
The circuit arrangement operates as follows. A
sample of the input over line 20 is obtained by coupler 38 and is directed through the voltage variable splitter/attenuator 40 to the linear amplifier 52. The *rB
_ g _ purpose of the linear amplifier is to increase the signal level to drive the auxiliary amplifier 54 which has been designed to produce substantially, to the extent possible, the same magnitude and type of distortion as the main amplifier 14. The output of the distortion auxiliary amplifier is adjusted by gain and phase correction circuits 60 and 62 and then subtracted from the delayed version of the input signal, from delay 48, to cancel the main input signal in the output of the auxiliary amplifier 54 leaving the distortion, at the output of comparator 50. These distortion products are then again amplified, and phase and amplitude corrected, passing through amplifier 64 and then gain and phase correction circuitry 66 and 68. The output of phase correction circuitry 68 is then injected 180° out of phase with the original signal.
The distortion products of a similar nonlinear device (amplifier 54) injected 180° degrees out of phase with the desired signal from delay 46, improves the apparent linearity of the following nonlinear power amplifier 14 operating, for example, as a class AB
amplifier. The improvement occurs typically in the third order intermodulation products, and is less for the high order products.
The output of the main amplifier is also sampled by coupler 76. The comparison circuit 30 then compares the sampled output of the main amplifier with the original input signal processed as follows. A sample of the original input signal on line 20 is obtained from coupler 22 and passes through delay line 24. The delay lines 24, 46, and 48 are all selected to maintain the signals in time phase as they are coupled together, taking into account the delays inherent in the amplifier and correction circuities. The delayed output of delay element 24 is phase and gain corrected and delivered to _ g _ the comparison circuitry 30, the output of which is a measure of the distortion products at the main amplifier output after a null has been obtained. This nulled signal is then used, in part, to control the various elements of the predistortion circuitry 12 and the nulling feed forward circuits 26, 28, to optimize operation at any given power level, temperature, tone spacing, etc.
Referring to the correction and control circuitry 16, the error signal output from comparison circuitry 30 is amplified and isolated by amplifiers 82 and 84, is detected using the Schottky diode 86, in this illustrated embodiment of the invention, and is provided as an input to the processor 90. As noted above, the processor 90 also receives an input from the predistortion circuitry, where the output of the linear amplifier 64, which contains the distortion output from the first distortion loop, is passed through and isolated by amplifiers 120, 122, and detected by Schottky diode 124. In essence, the Schottky diodes measure the energy contained in the signal applied to them and that energy signal is provided to the controller 90 (through analog to digital converters (not shown)).
The controller 90 operates on a priority basis, as described below, and based upon the energy inputs applied to it, and its program priority basis, continuously and iteratively outputs digital signal values to the D to A
converters. The D to A converters, upon receiving a new digital signal value, convert their digital inputs to an analog signal output for controlling the various phase and gain elements of the circuitry, that is, the amplifier 52 before the auxiliary amplifier 54, and the gain and phase correction circuits 60, 62, 66, 68, and 26, 28. As these circuits vary in gain and/or phase, the effect is to linearize the input/output relationship from the input signal 20 to the output signal 18 for the entire circuit arrangement. This is performed, as described above, by adding distortion signals (predistorting) to the input of the main amplifier so that the overall response at the output of the main amplifier is linear with respect to the input signal over line 20.
In operation, controller 90 operates substantially in a feedback loop environment. It iteratively adjusts the varying control elements to which it is connected and determines whether the adjustment improves, has no effect, or renders worse, the error products such as the output of the first distortion loop on line 140 or in the error output of the overall device on line 80. The object is to minimize the distortion at the output of linear amplifier 14 upon reaching a null at the output of comparator 30. In performing this process, referring to Figure 2, the controller operates to give highest priority to the gain and phase control circuits 26, 28, which operate at approximately a millisecond cycle time as opposed to a lower priority in controlling the operation of gain and phase correction circuities 60 and 62 which are updated approximately every three to four milliseconds; and a lowest priority to the adjustment of amplifier 52 and gain and phase correction circuities 66 and 68 which are corrected approximately every 50 milliseconds. The control processor can be for example a model MC68HCIlE9 processor manufactured by Motorola.
Accordingly, in operation, controller 90 loops between the various correction circuities in order to continuously maintain and update the correction output values. Thus, once started (referring to Figure 2) the system first checks whether to adjust gain and phase correction circuits 26, 28. This decision can be based, for example, upon an internal clock measurement so that these elements can be updated every millisecond. This is tested at step 200. If the elements are to be adjusted, then the gain can be adjusted at step 202 and the phase can be adjusted at step 204, after which control returns to the main loop. Thereafter, the system determines whether to adjust the control voltages to gain amplifier 52, gain correction circuit 66, and gain correction circuit 68. If, the decision at step 206 is ~~yes~~, the control signals to each of the three elements are adjusted in sequence at steps 208, 210, and 214. Control then again returns to the main loop. Finally, the system checks at 218 whether to adjust the signals controlling gain and phase correction circuits 60 and 62. If the gain and phase are to be adjusted, the system then adjusts, as necessary, those elements at 220 and 222 and control returns to the main loop. The next step reads new detector values at the inputs from detection elements 86 and 12.4. This is indicated at step 224.
In a particular embodiment of the invention, gain and phase correction circuitries 26 and 28 are adjusted based solely upon the error signal value from detector 86. Similarly, gain element 52 and gain and phase correction circuitries 66 and 68 are also determined based solely on the signal level of detector 86.
Finally, the gain and phase correction circuits 60 and 62 are adjusted based solely upon the detector output measurements of detector 124.
Referring now to Figure 3, a power amplifier circuit 198 in which there is no predistortion, has a main amplifier 200 which is operating in as a Class AB
amplifier. The distortion energy output of the amplifier will be affected by the bias point of the amplifier. In a specific example, for example, a lateral MOSFET device can be used as an RF MOSFET transistor amplifier. While this device produces lower source inductance and can operate into the two gigahertz range, in addition to being generally affected by its bias point, this amplifier has associated with it a drift in its operating bias current over long periods of time (for example, hundreds of hours). Accordingly, when these devices are employed over thousands of hours, in a single year, there is concern with regard to the continued operating characteristics of the amplifier.
Accordingly, in connection with the invention, a bias control signal over a line 202 is provided from a digital to analog converter 204. The digital to analog converter is controlled by a controller 206, for example the Motorola controller noted above, which responds to detected energy from a Schottky diode 208 which receives the output of series connected amplifiers 210 and 212.
The input to amplifier 212 ideally represents the distortion components in the output of main amplifier 200. Those distortion components are obtained by subtracting, using a comparator 214, a signal derived from the output of the main amplifier using a coupler 216 and a signal derived from the input to the main amplifier, sampled at coupler 220, and passed through a delay 222 and phase and amplitude correction circuitries 224 and 240 respectively.
In accordance with the invention, therefore, the controller operates, iteratively, to periodically adjust the bias to the main amplifier. It then determines whether the distortion energy detected by Schottky diode 208 increases or decreases. In addition, the phase and amplitude circuitries 224 and 240 can be adjusted in the normal manner, as described above, to help improve the characteristics of the out of phase signal being input to comparator 214.
As a result, therefore, the desired output of the amplifier 200 is pulled by the adaptive control of the WO 99/52204 PCT/US99/0?64?
phase shifter circuitry 224 and variable attenuator 240.
The remaining power at the detector is then minimized to minimize the distortion products. Since the optimum bias point for the main amplifier 200 will be dependent upon the power level, the number of tones, tone spacing, etc., in the input signal over line 242, the bias will be initially adaptively adjusted in each mode for the best operating performance and that performance will then continue to be achieved over time as the adaptive circuit continually and iteratively adjusts the control signals to the main amplifier and the circuitries 224 and 240 (in this illustrative embodiment). Thus, in this embodiment, when the main error amplifier signal from coupler 216 is nulled, what remains is the distortion power and therefore what is detected at Schottky diode 208 is the distortion power which can be used to adaptively tune the amplifier, a predistorter as illustrated in Figure 1, or any other nonlinear device for improved linearity. The continuous bias adjustment to minimize main amplifier output distortion, when the amplifier is a lateral MOSFET
also has the desirable effect of compensating for thermal and other drift over time.
The controller 206 thus also controls the digital to analog converters 244, the outputs of which control the phase and amplitude circuitries 224 and 240 respectively.
Additions, subtractions, and other modifications of the described and preferred embodiments of the invention will be apparent to those practiced in this field and are within the scope of the following claims.
amplifier) which is part of an amplifier arrangement having an input and an output. The method features the steps of generating an amplifier output signal from the amplifier arrangement; generating an error signal from the output of the main amplifier representing a distortion error energy, and iteratively and successively correcting, using a digitally controlled processor responsive at least to signals derived from the error signal, bias control signals to at least one of the main amplifier and phase and gain adjustments in an error loop.
In various aspects of the invention, the error signal generating step features comparing a signal derived from the output of the main amplifier and a signal derived from the input signal to the amplifier arrangement, generating a difference signal, and then measuring an energy content of a signal derived from the difference signal.
The invention thus advantageously biases, in a dynamic manner, the input bias control signal to a class AB or other distorting main amplifier or active devices) and thereby causes a substantial minimization of the distortion characteristics of the entire amplifier arrangement. The dynamic character of the system also adjusts for various instabilities including those caused by temperature, signal level, and component drift.
Brief Description of the Drawings Other objects, features, and advantages of the invention will be apparent from the following description, taken together with the drawings in which:
Figure 1 is a schematic block diagram of an embodiment of the predistorter amplifier and control circuitry illustrating one aspect of distortion minimization in accordance with the invention;
Figure 2 is a flow chart illustrating operation of the digitally controlled processor in accordance with the invention; and Figure 3 is a simplified schematic diagram illustrating bias control according to the invention.
Description of the Preferred Embodiments Referring to Figure l, an amplifier arrangement 10 has a predistortion circuitry 12, a main power amplifier 14, and a control circuitry 16. Amplifier 14 is typically a high power class AB amplifier whose output over a line 18 can be either used directly, or can be the input to a feed forward distortion cancellation circuitry such as that described in my copending U.S. Patent No. 5,796,304, entitled BROADBAND AMPLIFIER WITH QUADRATURE PILOT SIGNAL.
The input to the amplifier arrangement, over a line 20, is split (or sampled) for a number of purposes.
First, a line sampling coupler 22 directs part of the input signal to a delay element 24. The output of the delay element is directed to a controlled gain circuitry 26 and from there to a controlled phase circuitry 28. The output of the phase circuitry 28 is passed to a comparison device 30. (The processing order of delay 24, and circuitries 26, 28 is not important).
The remaining input signal over line 36 is sampled by another coupler 38 and the output of coupler 38 is received by a signal sp utter 40 which divides the signal equally for output over lines 42 and 44. The remaining -5a-input signal from line 36 is directed to a delay element 46.
The output of sp utter 40 over line 42 is directed to a delay element 48, the output of which is received by comparison circuitry 50. The other output of sp utter 40 over line 44 is received by a gain controlled amplifier 52, the output of which is directed to an auxiliary amplifier 54. The output of amplifier 54 is received by a controlled gain circuitry 60. The output of controlled gain circuitry 60 is delivered to a controlled phase circuitry 62 the output of which is compared with the signal from delay element 48 in comparison circuitry 50.
The difference between the two signals, representing distortion components introduced primarily by amplifier 54, is passed through a linear amplifier 64 to a controlled gain circuit 66. The output of the control gain circuit 66 is received by a controlled phase circuit 68. The output of the controlled phase circuit 68 is delivered to a coupler 70 which combines the output of the phase circuit 68 with the output of the delay element 46, to generate an input, over a line 72, to the main power amplifier 14.
The output of the main power amplifier 14, over a line 74, is sampled by a coupler 76 and the sampled output signal is compared (differenced) to the output of the phase controlled circuit 28 available over a line 78, to generate a distortion error signal on a line 80. The distortion error signal over line 80 is amplified using amplifiers 82 and 84, connected in series with each other, and the output of amplifier 84 is detected, here using a Schottky diode 86 to measure the energy in the signal, for input to a digital controller 90. The digital controller 90 outputs, in this illustrated embodiment, seven digital signals over lines 92a, 92b, 94a, 94b, 96, 98a, and 98b to control digital to analog (D/A) converters 100a, 100b, 102a, 102b, 104, 106a, and 106b, respectively. The analog outputs of the digital to analog converters are directed to control the various gain and phase elements of the predistortor circuitry 12 and the feedback control circuitry gain and phase 26 and 28.
The output of the comparison circuit 50, amplified by amplifier 64 to give it a proper signal value for eventual coupling into the output from the delay element 46, is sampled by a coupler 118. The output of the coupler, like the output of comparison circuitry 30, is passed through a pair of amplifiers 120, 122, and is detected at the output of amplifier 122, in the illustrated embodiment of the invention, using a Schottky diode 124, which provides a measure of the energy in the signal output of amplifier 122. That energy value is received by the controller 90 which uses that value to adjust and control the value of the gain at circuits 52 and 60, and the phase correction at circuit 64.
The circuit arrangement 10 thus has three loops in operation. One loop the first distortion loop, includes delay 48, amplifier 52, auxiliary amplifier 54, gain and phase correction circuits 60 and 62, and comparison circuitry 50. The second distortion loop includes those previous elements, and further, linear amplifier 64, and gain and phase correction circuits 66 and 68, along with delay 46. The system error loop includes those previously identified elements plus the main amplifier 14, delay 24, gain and phase correction elements 26 and 28, and comparison circuitry 30. The loops are controlled by the error correction circuitry including the processor 90, the A-to-D's 100a, 100b, 102a, 102b, 104, 106a, and 106b, the amplifiers 82, 84, 120, 122, and the detection elements, here the Schottky diodes, 86 and 124.
The circuit arrangement operates as follows. A
sample of the input over line 20 is obtained by coupler 38 and is directed through the voltage variable splitter/attenuator 40 to the linear amplifier 52. The *rB
_ g _ purpose of the linear amplifier is to increase the signal level to drive the auxiliary amplifier 54 which has been designed to produce substantially, to the extent possible, the same magnitude and type of distortion as the main amplifier 14. The output of the distortion auxiliary amplifier is adjusted by gain and phase correction circuits 60 and 62 and then subtracted from the delayed version of the input signal, from delay 48, to cancel the main input signal in the output of the auxiliary amplifier 54 leaving the distortion, at the output of comparator 50. These distortion products are then again amplified, and phase and amplitude corrected, passing through amplifier 64 and then gain and phase correction circuitry 66 and 68. The output of phase correction circuitry 68 is then injected 180° out of phase with the original signal.
The distortion products of a similar nonlinear device (amplifier 54) injected 180° degrees out of phase with the desired signal from delay 46, improves the apparent linearity of the following nonlinear power amplifier 14 operating, for example, as a class AB
amplifier. The improvement occurs typically in the third order intermodulation products, and is less for the high order products.
The output of the main amplifier is also sampled by coupler 76. The comparison circuit 30 then compares the sampled output of the main amplifier with the original input signal processed as follows. A sample of the original input signal on line 20 is obtained from coupler 22 and passes through delay line 24. The delay lines 24, 46, and 48 are all selected to maintain the signals in time phase as they are coupled together, taking into account the delays inherent in the amplifier and correction circuities. The delayed output of delay element 24 is phase and gain corrected and delivered to _ g _ the comparison circuitry 30, the output of which is a measure of the distortion products at the main amplifier output after a null has been obtained. This nulled signal is then used, in part, to control the various elements of the predistortion circuitry 12 and the nulling feed forward circuits 26, 28, to optimize operation at any given power level, temperature, tone spacing, etc.
Referring to the correction and control circuitry 16, the error signal output from comparison circuitry 30 is amplified and isolated by amplifiers 82 and 84, is detected using the Schottky diode 86, in this illustrated embodiment of the invention, and is provided as an input to the processor 90. As noted above, the processor 90 also receives an input from the predistortion circuitry, where the output of the linear amplifier 64, which contains the distortion output from the first distortion loop, is passed through and isolated by amplifiers 120, 122, and detected by Schottky diode 124. In essence, the Schottky diodes measure the energy contained in the signal applied to them and that energy signal is provided to the controller 90 (through analog to digital converters (not shown)).
The controller 90 operates on a priority basis, as described below, and based upon the energy inputs applied to it, and its program priority basis, continuously and iteratively outputs digital signal values to the D to A
converters. The D to A converters, upon receiving a new digital signal value, convert their digital inputs to an analog signal output for controlling the various phase and gain elements of the circuitry, that is, the amplifier 52 before the auxiliary amplifier 54, and the gain and phase correction circuits 60, 62, 66, 68, and 26, 28. As these circuits vary in gain and/or phase, the effect is to linearize the input/output relationship from the input signal 20 to the output signal 18 for the entire circuit arrangement. This is performed, as described above, by adding distortion signals (predistorting) to the input of the main amplifier so that the overall response at the output of the main amplifier is linear with respect to the input signal over line 20.
In operation, controller 90 operates substantially in a feedback loop environment. It iteratively adjusts the varying control elements to which it is connected and determines whether the adjustment improves, has no effect, or renders worse, the error products such as the output of the first distortion loop on line 140 or in the error output of the overall device on line 80. The object is to minimize the distortion at the output of linear amplifier 14 upon reaching a null at the output of comparator 30. In performing this process, referring to Figure 2, the controller operates to give highest priority to the gain and phase control circuits 26, 28, which operate at approximately a millisecond cycle time as opposed to a lower priority in controlling the operation of gain and phase correction circuities 60 and 62 which are updated approximately every three to four milliseconds; and a lowest priority to the adjustment of amplifier 52 and gain and phase correction circuities 66 and 68 which are corrected approximately every 50 milliseconds. The control processor can be for example a model MC68HCIlE9 processor manufactured by Motorola.
Accordingly, in operation, controller 90 loops between the various correction circuities in order to continuously maintain and update the correction output values. Thus, once started (referring to Figure 2) the system first checks whether to adjust gain and phase correction circuits 26, 28. This decision can be based, for example, upon an internal clock measurement so that these elements can be updated every millisecond. This is tested at step 200. If the elements are to be adjusted, then the gain can be adjusted at step 202 and the phase can be adjusted at step 204, after which control returns to the main loop. Thereafter, the system determines whether to adjust the control voltages to gain amplifier 52, gain correction circuit 66, and gain correction circuit 68. If, the decision at step 206 is ~~yes~~, the control signals to each of the three elements are adjusted in sequence at steps 208, 210, and 214. Control then again returns to the main loop. Finally, the system checks at 218 whether to adjust the signals controlling gain and phase correction circuits 60 and 62. If the gain and phase are to be adjusted, the system then adjusts, as necessary, those elements at 220 and 222 and control returns to the main loop. The next step reads new detector values at the inputs from detection elements 86 and 12.4. This is indicated at step 224.
In a particular embodiment of the invention, gain and phase correction circuitries 26 and 28 are adjusted based solely upon the error signal value from detector 86. Similarly, gain element 52 and gain and phase correction circuitries 66 and 68 are also determined based solely on the signal level of detector 86.
Finally, the gain and phase correction circuits 60 and 62 are adjusted based solely upon the detector output measurements of detector 124.
Referring now to Figure 3, a power amplifier circuit 198 in which there is no predistortion, has a main amplifier 200 which is operating in as a Class AB
amplifier. The distortion energy output of the amplifier will be affected by the bias point of the amplifier. In a specific example, for example, a lateral MOSFET device can be used as an RF MOSFET transistor amplifier. While this device produces lower source inductance and can operate into the two gigahertz range, in addition to being generally affected by its bias point, this amplifier has associated with it a drift in its operating bias current over long periods of time (for example, hundreds of hours). Accordingly, when these devices are employed over thousands of hours, in a single year, there is concern with regard to the continued operating characteristics of the amplifier.
Accordingly, in connection with the invention, a bias control signal over a line 202 is provided from a digital to analog converter 204. The digital to analog converter is controlled by a controller 206, for example the Motorola controller noted above, which responds to detected energy from a Schottky diode 208 which receives the output of series connected amplifiers 210 and 212.
The input to amplifier 212 ideally represents the distortion components in the output of main amplifier 200. Those distortion components are obtained by subtracting, using a comparator 214, a signal derived from the output of the main amplifier using a coupler 216 and a signal derived from the input to the main amplifier, sampled at coupler 220, and passed through a delay 222 and phase and amplitude correction circuitries 224 and 240 respectively.
In accordance with the invention, therefore, the controller operates, iteratively, to periodically adjust the bias to the main amplifier. It then determines whether the distortion energy detected by Schottky diode 208 increases or decreases. In addition, the phase and amplitude circuitries 224 and 240 can be adjusted in the normal manner, as described above, to help improve the characteristics of the out of phase signal being input to comparator 214.
As a result, therefore, the desired output of the amplifier 200 is pulled by the adaptive control of the WO 99/52204 PCT/US99/0?64?
phase shifter circuitry 224 and variable attenuator 240.
The remaining power at the detector is then minimized to minimize the distortion products. Since the optimum bias point for the main amplifier 200 will be dependent upon the power level, the number of tones, tone spacing, etc., in the input signal over line 242, the bias will be initially adaptively adjusted in each mode for the best operating performance and that performance will then continue to be achieved over time as the adaptive circuit continually and iteratively adjusts the control signals to the main amplifier and the circuitries 224 and 240 (in this illustrative embodiment). Thus, in this embodiment, when the main error amplifier signal from coupler 216 is nulled, what remains is the distortion power and therefore what is detected at Schottky diode 208 is the distortion power which can be used to adaptively tune the amplifier, a predistorter as illustrated in Figure 1, or any other nonlinear device for improved linearity. The continuous bias adjustment to minimize main amplifier output distortion, when the amplifier is a lateral MOSFET
also has the desirable effect of compensating for thermal and other drift over time.
The controller 206 thus also controls the digital to analog converters 244, the outputs of which control the phase and amplitude circuitries 224 and 240 respectively.
Additions, subtractions, and other modifications of the described and preferred embodiments of the invention will be apparent to those practiced in this field and are within the scope of the following claims.
Claims (12)
1. An amplifier arrangement for amplifying an input signal said amplifier arrangement comprising:
a main amplifier, an error loop having a comparator which differences a delayed derivative of said input signal to said amplifier arrangement with a signal representative of the output of said main amplifier to provide an error signal;
a first distortion controlled feedback loop including a detector for receiving said error signal and generating a detected error signal output dependent upon the energy in said error signal; and a bias signal generation circuit for generating at least one bias signal having signal correction circuitry for receiving the detected error signal output for generating a bias control signal, and said main amplifier being responsive to said bias control signal for changing its operating point for reducing distortion in its output.
a main amplifier, an error loop having a comparator which differences a delayed derivative of said input signal to said amplifier arrangement with a signal representative of the output of said main amplifier to provide an error signal;
a first distortion controlled feedback loop including a detector for receiving said error signal and generating a detected error signal output dependent upon the energy in said error signal; and a bias signal generation circuit for generating at least one bias signal having signal correction circuitry for receiving the detected error signal output for generating a bias control signal, and said main amplifier being responsive to said bias control signal for changing its operating point for reducing distortion in its output.
2. The amplifier arrangement of claim 1 wherein said main amplifier is a broadband radio frequency amplifier operating in a class AB mode.
3. The amplifier arrangement of claim 1 further comprising a phase and a gain correction circuitry in said error loop responsive to said signal correction circuitry.
4. The amplifier arrangement of claim 1 further wherein:
said error loop comprises an error loop delay circuit connected to receive a signal derived from said input signal to be amplified, and an error loop phase and gain correction circuitry connected in series with said error loop delay circuit and responsive to said signal correction circuitry, said error loop delay circuit and said error loop phase and amplitude correcting circuitry together generating said delayed derivative of said input signal.
said error loop comprises an error loop delay circuit connected to receive a signal derived from said input signal to be amplified, and an error loop phase and gain correction circuitry connected in series with said error loop delay circuit and responsive to said signal correction circuitry, said error loop delay circuit and said error loop phase and amplitude correcting circuitry together generating said delayed derivative of said input signal.
5. The amplifier arrangement of claim 4 further wherein said bias signal generation comprises an energy measurement circuit for measuring the energy in said error signal, and said bias signal generation circuit comprises a control processor, responsive to the energy measurement circuit, for iteratively adjusting the signal correction circuitry bias control signal.
6. The amplifier arrangement of claim 5 wherein said controller iteratively adjusts said phase correcting circuit, and then said gain correction circuit, in said error loop, in a continuously repeating pattern.
7. The amplifier arrangement of claim 4 wherein said energy measurement circuit is a Schottky diode circuit.
8. The amplifier arrangement of claim 5 further wherein said control processor is responsive for iteratively controlling, at a low priority, said gain and phase control circuitry in said error loop, in response to said error signal detection circuitry.
9. A method of minimizing distortion energy in an amplified signal output from a main amplifier of an amplifier arrangement, said main amplifier being part of the amplifier arrangement and the arrangement having an input and an output, comprising the steps of:
generating an amplifier output signal from the amplifier arrangement, generating an error signal from the output of the main amplifier representing a distortion error energy, iteratively and successively correcting, using a digitally controlled processor responsive at least to signals derived from said error signal, bias control signals to at least one of the main amplifier and phase and gain adjustments in an error loop.
generating an amplifier output signal from the amplifier arrangement, generating an error signal from the output of the main amplifier representing a distortion error energy, iteratively and successively correcting, using a digitally controlled processor responsive at least to signals derived from said error signal, bias control signals to at least one of the main amplifier and phase and gain adjustments in an error loop.
10. The method of claim 9 wherein said interactively correcting step is responsive to distortion error signals generated within said main amplifier.
11. The method of claim 10 wherein said error signal generating step comprises the step of comparing a signal derived from the output of the main amplifier and a signal derived from the input signal to the amplifier arrangement for generating a difference signal, and measuring an energy content of a signal derived from said difference signal.
12. The method of claim 11 further comprising the step of performing said iterative adjusting and correcting steps at different periodic rates.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/057,380 | 1998-04-08 | ||
| US09/057,380 US6028477A (en) | 1998-04-08 | 1998-04-08 | Adaptive biasing in a power amplifier |
| PCT/US1999/007647 WO1999052204A1 (en) | 1998-04-08 | 1999-04-07 | Adaptive biasing in a power amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2293241A1 CA2293241A1 (en) | 1999-10-14 |
| CA2293241C true CA2293241C (en) | 2002-08-06 |
Family
ID=22010222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002293241A Expired - Lifetime CA2293241C (en) | 1998-04-08 | 1999-04-07 | Adaptive biasing in a power amplifier |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6028477A (en) |
| EP (1) | EP0995261B1 (en) |
| KR (1) | KR100371083B1 (en) |
| BR (1) | BR9906347A (en) |
| CA (1) | CA2293241C (en) |
| DE (1) | DE69929964T2 (en) |
| WO (1) | WO1999052204A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6236267B1 (en) * | 1998-12-29 | 2001-05-22 | International Business Machines Corporation | Linearization for power amplifiers using feed-forward and feedback control |
| US6259319B1 (en) * | 1999-08-19 | 2001-07-10 | Lucent Technologies Inc. | Adaptive gain and/or phase adjustment control system and method |
| KR20010056500A (en) * | 1999-12-15 | 2001-07-04 | 서평원 | Distortion component detector in power amplifier |
| GB2358748A (en) * | 2000-01-31 | 2001-08-01 | Wireless Systems Int Ltd | An arrangement in a predistortion or feedforward linearizer for an amplifier in which I and Q components are adjusted to achieve a desired phase and amplitude |
| EP1249930A3 (en) * | 2001-04-10 | 2004-06-02 | Matsushita Electric Industrial Co., Ltd. | Predistortion linearizer and predistortion compensation method and program |
| US6563385B2 (en) | 2001-04-18 | 2003-05-13 | Xicor, Inc. | Amplifier bias control circuit |
| US6756844B2 (en) * | 2001-08-07 | 2004-06-29 | Hitachi Kokusai Electric Inc. | Distortion compensation amplification apparatus of feed forward type and adaptive pre-distortion type |
| US6812786B2 (en) | 2002-04-11 | 2004-11-02 | Andrew Corporation | Zero-bias bypass switching circuit using mismatched 90 degrees hybrid |
| US6700439B2 (en) | 2002-04-11 | 2004-03-02 | Andrew Corporation | Zero-bias bypass switch |
| SE524408C2 (en) * | 2002-06-19 | 2004-08-03 | Ericsson Telefon Ab L M | Efficient generation of radio frequency streams |
| US7002407B2 (en) | 2002-12-18 | 2006-02-21 | Powerwave Technologies, Inc. | Delay mismatched feed forward amplifier system using penalties and floors for control |
| WO2004062091A1 (en) * | 2002-12-18 | 2004-07-22 | Powerwave Technologies, Inc. | Feed forward amplifier system using penalties and floors for optimal control |
| SE0402524D0 (en) * | 2004-09-21 | 2004-10-15 | Ericsson Telefon Ab L M | Tunable predistors |
| US7634198B2 (en) * | 2006-06-21 | 2009-12-15 | Emcore Corporation | In-line distortion cancellation circuits for linearization of electronic and optical signals with phase and frequency adjustment |
| TWI332749B (en) * | 2006-08-14 | 2010-11-01 | Realtek Semiconductor Corp | Power amplifier circuit having a bias signal inputted into an input terminal and method thereof |
| KR100895532B1 (en) * | 2008-10-24 | 2009-04-30 | 주식회사 엠텍아이앤씨 | Highly efficient digital pre-distortion amplifier |
| US9118366B2 (en) | 2012-09-12 | 2015-08-25 | Mediatek Singapore Pte. Ltd. | Method and apparatus for calibrating an envelope tracking system |
| US9385666B2 (en) | 2013-12-09 | 2016-07-05 | Marvell World Trade Ltd. | Power amplifier with wide band AM-AM feedback and digital pre-distortion |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4879519A (en) * | 1988-10-31 | 1989-11-07 | American Telephone And Telegraph Company, At&T Bell Labs | Predistortion compensated linear amplifier |
| CA2046413C (en) * | 1990-07-11 | 1994-01-04 | Shoichi Narahashi | Feed-forward amplifier |
| JPH07147547A (en) * | 1993-11-24 | 1995-06-06 | Nec Corp | Feedforward type distortion compensation circuit |
| US5485120A (en) * | 1994-07-28 | 1996-01-16 | Aval Communications Inc. | Feed-forward power amplifier system with adaptive control and control method |
| US5621354A (en) * | 1995-10-17 | 1997-04-15 | Motorola, Inc. | Apparatus and method for performing error corrected amplification in a radio frequency system |
| US5789976A (en) * | 1996-06-17 | 1998-08-04 | Corporation De L'ecole Polytechnique | Digital adaptive control of feedforward amplifier using frequency domain cancellation |
| US5867064A (en) * | 1996-08-19 | 1999-02-02 | Motorola, Inc. | Method and apparatus for improving intermodulation in a feed-forward amplifier |
-
1998
- 1998-04-08 US US09/057,380 patent/US6028477A/en not_active Expired - Lifetime
-
1999
- 1999-04-07 KR KR10-1999-7011540A patent/KR100371083B1/en not_active IP Right Cessation
- 1999-04-07 DE DE69929964T patent/DE69929964T2/en not_active Expired - Lifetime
- 1999-04-07 EP EP99917362A patent/EP0995261B1/en not_active Expired - Lifetime
- 1999-04-07 BR BR9906347-6A patent/BR9906347A/en not_active IP Right Cessation
- 1999-04-07 CA CA002293241A patent/CA2293241C/en not_active Expired - Lifetime
- 1999-04-07 WO PCT/US1999/007647 patent/WO1999052204A1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| BR9906347A (en) | 2000-09-19 |
| DE69929964D1 (en) | 2006-04-27 |
| KR20010013533A (en) | 2001-02-26 |
| EP0995261A4 (en) | 2001-11-28 |
| EP0995261B1 (en) | 2006-02-22 |
| US6028477A (en) | 2000-02-22 |
| DE69929964T2 (en) | 2006-11-23 |
| WO1999052204A1 (en) | 1999-10-14 |
| CA2293241A1 (en) | 1999-10-14 |
| EP0995261A1 (en) | 2000-04-26 |
| KR100371083B1 (en) | 2003-02-05 |
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