CA2299348A1 - Method and apparatus for selecting thread switch events in a multithreaded processor - Google Patents

Method and apparatus for selecting thread switch events in a multithreaded processor Download PDF

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Publication number
CA2299348A1
CA2299348A1 CA002299348A CA2299348A CA2299348A1 CA 2299348 A1 CA2299348 A1 CA 2299348A1 CA 002299348 A CA002299348 A CA 002299348A CA 2299348 A CA2299348 A CA 2299348A CA 2299348 A1 CA2299348 A1 CA 2299348A1
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Prior art keywords
thread
thread switch
multithreaded processor
switch logic
register
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CA002299348A
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French (fr)
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CA2299348C (en
Inventor
John Michael Borkenhagen
Richard James Eickemeyer
William Thomas Flynn
Andrew Henry Wottreng
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International Business Machines Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

A system and method for performing computer processing operations in a data processing system (10) includes a multithreaded processor (100) and thread switch logic (400).

The multithreaded processor is capable of switching between two or more threads of instractions which can be independently executed. Each thread has a corresponding state in a thread state register (440) depending on its execution status. The thread switch logic contains a thread switch control register (410) to store the conditions upon which a thread will occur. The thread switch logic has a time-out register (430) which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register (420) to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager (460) capable of changing the priority of the different threads and thus superseding thread switch events.
CA002299348A 1997-10-23 1998-10-14 Method and apparatus for selecting thread switch events in a multithreaded processor Expired - Lifetime CA2299348C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/958,716 1997-10-23
US08/958,716 US6697935B1 (en) 1997-10-23 1997-10-23 Method and apparatus for selecting thread switch events in a multithreaded processor
PCT/US1998/021716 WO1999021081A1 (en) 1997-10-23 1998-10-14 Method and apparatus for selecting thread switch events in a multithreaded processor

Publications (2)

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CA2299348A1 true CA2299348A1 (en) 1999-04-29
CA2299348C CA2299348C (en) 2004-10-19

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CA002299348A Expired - Lifetime CA2299348C (en) 1997-10-23 1998-10-14 Method and apparatus for selecting thread switch events in a multithreaded processor

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US (1) US6697935B1 (en)
EP (1) EP1029269B1 (en)
JP (1) JP4006180B2 (en)
KR (1) KR100403658B1 (en)
CN (1) CN1112636C (en)
CA (1) CA2299348C (en)
HU (1) HUP0100013A3 (en)
IL (1) IL134823A (en)
PL (1) PL193285B1 (en)
TW (1) TW409227B (en)
WO (1) WO1999021081A1 (en)

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HUP0100013A3 (en) 2004-03-29
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US6697935B1 (en) 2004-02-24
CA2299348C (en) 2004-10-19
TW409227B (en) 2000-10-21
EP1029269A1 (en) 2000-08-23
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PL193285B1 (en) 2007-01-31
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