CA2302500A1 - Control processor switchover for a telecommunications switch - Google Patents
Control processor switchover for a telecommunications switch Download PDFInfo
- Publication number
- CA2302500A1 CA2302500A1 CA002302500A CA2302500A CA2302500A1 CA 2302500 A1 CA2302500 A1 CA 2302500A1 CA 002302500 A CA002302500 A CA 002302500A CA 2302500 A CA2302500 A CA 2302500A CA 2302500 A1 CA2302500 A1 CA 2302500A1
- Authority
- CA
- Canada
- Prior art keywords
- modules
- module
- switch
- active
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2017—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where memory access, memory control or I/O control functionality is redundant
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2023—Failover techniques
- G06F11/2025—Failover techniques using centralised failover control functionality
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1305—Software aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13104—Central control, computer control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13107—Control equipment for a part of the connection, distributed control, co-processing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13162—Fault indication and localisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13166—Fault prevention
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13167—Redundant apparatus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Hardware Redundancy (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
First and second control processor cards (12, 14) are employed in conjunction with first and second switch fabric cards (16, 18) to interconnect Input/Output cards (24) in a telecommunications switch (10). The control processor cards (12, 14) provide a portion of the functionality previously associated with switch fabric cards (16, 18), such as exertion of control over allocation of bandwidth within the switch. The control processor cards also provide new functionality. In particular, each control processor card can configure both switch fabric cards (16, 18). Redundant control processor cards and redundant switch fabric cards are employed to provide a switch that is less susceptible to failure than switches with only redundant switch fabric cards. Hence, failure of a control processor card and a switch fabric card can be sustained without resulting in switch failure. Timing control functions may also be provided by a separate timing module card (20, 22).
Description
TITLE OF THE INVENTION
CONTROL PROCESSOR SWITCHOVER FOR A TELECOMMUNICATIONS SWITCH
CROSS REFERENCE TO RELATED APPLICATIONS
Not applicable STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR
DEVELOPMENT
Not applicable BACKGROUND OF THE INVENTION
The present invention is generally related to telecommunications switches, and more particularly to high reliability telecommunications switches employing redundant 0 control systems.
Telecommunications switches facilitate routing and transmission of data in telecommunications networks. Such switches typically include a plurality of Input/output ("I/O") cards which are interconnected through a switch fabric card.
5 In particular, the switch fabric interconnects each I/O card with every other I/0 card such that a data unit received at any I/O card can be transmitted to any other I/0 card in the switch.
In addition to interconnecting the I/O cards, the switch 0 fabric may function to control timing operations within the switch and allocate bandwidth to connections through the I/O
cards such that collisions are avoided. Such functionality is relatively complex to implement, and consequently switch fabric cards in a telecommunications switch are prone to failure. In 5 particular, control functions that are heavily software dependent are prone to failure due to software bugs. Such bugs may be triggered by specific sequences of events so the card can at times be restored through a reset operation. However, data can be lost in such a reset operation.
To avoid data loss and switch failure due to a switch fabric card failure it is known to employ redundant switch fabric cards. In particular, it is known to install a plurality of switch fabric cards in a single switch so that a standby switch fabric card can be employed in the event that the active switch fabric card fails. However, switch fabric cards are generally high cost items and it is therefore common 7 practice to install only one standby switch fabric card, which may not provide sufficient reliability.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a control processor card is employed in conjunction with a switch fabric card to interconnect Input/output (~~I/O~~) cards and control switch operation. The control processor card provides a portion of the functionality previously associated with switch fabric cards, such as exertion of control over allocation of bandwidth within the switch and also includes additional control and configuration functionality for a plurality of switch fabric cards, timing module cards and other core switch functions.
In the preferred embodiment first and second control processor cards are employed with first and second switch fabric cards and first and second timing control cards.
Redundant control processor cards and redundant switch fabric cards are employed to provide a switch that is less susceptible to failure than switches with only redundant switch fabric cards. Both active and standby control processor cards are coupled to active and standby switch fabric cards although only the active control processor card is used to control the switch fabric and other core functions at any given time. Upon > failure of the active control processor card, the standby control processor card becomes the active control processor card and the new standby card is reset or removed for repair.
Previously known switch fabric cards perform several complex functions including allocation of bandwidth, interconnection of I/0 cards and timing control. Such functions are software intensive and are generally more prone to failure than other portions of the switch. Failure of any one such function may result in failure of the entire switch fabric card. The present invention localizes failure of such 0 functions by associating performance of those functions with separate cards. Further, by employing redundancy in the control processor card, timing control modules and the switch fabrics, control processor card switchover may be accomplished using either switch fabric as the active switch fabric or 5 either timing control module as the active timing control module.
BRIEF DESCRIPTION OF THE DRAWING
0 The invention will be more fully understood in view of the following Detailed Description of the Invention; in conjunction with the Drawing, of which:
Fig. 1 is a block diagram of a telecommunications switch;
Fig. 2 is a block diagram of the control processor card of 5 Fig. 1;
Fig. 3 is a block diagram of a bistable latch;
Fig. 4 is a block diagram of the control processor busses of Fig. 1; and Fig. 5 is a block diagram of the timing control interface 0 busses of Fig. 1.
DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 illustrates a telecommunications switch 10 having 5 two control processor cards 12, 14, two switch fabric cards 16, ' WO 99/11002 PCTlUS98/17535 18, two timing control module cards 20, 22 and a plurality of Input/output ("I/O") cards 24. All of the cards are interconnected for complete interoperability. The I/O cards 24 are interconnected through both switch fabric cards 16, 18 in a crossbar configuration such that a data unit that is received at any one of the I/O cards 24 can be transmitted to any other I/O card, regardless of which switch fabric card is in active use. Similarly, both of the control processor cards are each coupled to both of the switch fabric cards and both of the 0 timing control cards. The control processor cards are interconnected through shared control signals to a set of central switch resources 26.
The control processor cards 12, 14 function to configure the switch fabric cards, monitor the state of the switch, 5 control switch fabric switchover and control switch resources.
One particular resource that is controlled by the control processor cards is the bandwidth within the switch fabric. The switch fabric cards function to interconnect the I/O cards.
The timing control module cards provide clock signals and 0 control timing within the switch. The I/O cards provide an interface to other devices and may be configured to facilitate communication with specific protocols and connection types such as frame relay, Asynchronous Transfer Mode ("ATM"), Ethernet, Fiber Distributed Data Interface, token ring, Integrated Services Digital Network and T1.
Referring to Figs. 1 and 2, each control processor card 12, 14 includes redundant cell thread interfaces 30, 32 to the switch fabric cards 16, 18, an I960 bus interface 34 to an I960HD Processor and ATMizer Control ("PAC") 38, a lOMbps 0 Ethernet interface controller 40, a hard drive 42, selective reset logic 44, a redundant expansion bus 46 connected to the switch fabric cards, an interface 48 to the timing control module cards, interrupt logic 50 to sum indirect interrupts, and interface 52 to microprocessor ports of internal Application Specific Integrated Circuits ( "ASICs" ) , support for a redundant control processor cards, power module 56, Module Identification Memory ("MIM") interface 58, Light Emitting Diode ("LED") indicators 60 and test logic 62.
When the switch is powered-ON or reset, only one of the control processor cards 12, 14 can become active. The non active control processor card is considered to be in standby mode. An active control processor card is distinguished from a standby control processor card by having exclusive control over central resources and internal resources including the 0 Management Ethernet port 64, Management RS232 port 66, MIM
interface 58 (through which revision numbers and other information can be retrieved from cards in the switch), timing module board microprocessor interface bus, switch~fabric board microprocessor interface bus, selective resets to other system 5 boards, timing module FPGA download interface, switch fabric switchover synchronization backplane signal (SYNC TM), BIO
expansion bus strobe backplane signal, Power and Fan test signals, Buzzer relay and External alarm relays; none of which are implemented on the control processor cards. These 0 resources are not critical to operations of existing ATM
connections, and the resources can be unavailable for the time required to execute a control processor card switchover operation without causing switch failure. Similarly, one switch fabric and one timing control module will be in the 5 active mode during operation, while the non-active switch fabric card and timing control module will be in a standby mode.
Referring to Figs. 2 and 3, to implement redundancy the control processor cards 12, 14 can "switchover" between active 0 and standby modes so that a faulty control processor card can fail and be replaced by the standby control processor card without disrupting data flow. A bistable latch is formed with inverter type latch halves 80, 82 implemented on each control processor card. The latch halves are cross-coupled through a 5 backplane connector 84, and latch logic ensures that different logic levels are maintained at respective state indicator nodes 86, 88 on each control processor card. Relatively little hardware is used in the cross coupled latch to reduce the probability of failure in the bistable latch itself. Software may be employed to ensure that the standby control processor is functioning properly before allowing the switchover operation.
At power-ON the latch resolves the online state, i.e., active or standby, of each control processor card. This state is resolved randomly at power-ON. The online state of the 0 control processor card is employed within a few logic gate delays to control tri-stating of the central resources 26. In particular, the standby control processor card tri-states (at high impedance) any hardware buffers involved in the access of the central resources to avoid interference with the operation 5 of the active control processor.
The active control processor card periodically transmits an "active" or "keep alive" indicator signal 90 to the standby control processor card. The standby control processor monitors the state of the active control processor by receiving the 0 "active" signals from the active control processor through a dedicated backplane channel ("backchannel") 92. If the active control processor fails to send an "active" indicator signal, the standby control processor responds as though the active control processor is faulty. In particular, the standby 5 control processor begins termination of the active control processor by generating a "terminate" signal 94. The terminate signal toggles the state of the cross-coupled bistable latch.
Following the state change caused by the terminate signal the active control processor tri-states access to internal and 0 central resources. A non-maskable interrupt ("NMI") is then sent to the main processor unit. The processor unit in the active control processor card operates for approximately 40ms following receipt of the terminate signal 94 to clean up operations and store current state information to non-volatile 5 storage, at which point the standby control processor becomes -active and the formerly active control processor card is reset .
Following the reset cycle the terminated control processor card assumes standby status. The standby control processor can then be physically removed from the switch for diagnostic testing, repair or replacement.
During the control processor switchover operation any microprocessor transactions in progress in the active timing module and active switch fabric interface are completed before tri-stating is implemented. For example, microprocessor non-0 burst read/write cycles of single header fields are finished before tri-stating. The timing module FPGA download may be interrupted by the control processor switchover, in which case a "NOT DONE" status signal is generated to indicate an incomplete FPGA program cycle to the new active control 5 processor. Multiple microprocessor transactions are necessary to access the MIMs and for FPGA downloading. Consequently, transactions in progress to the MIMs may cause the target MIM
to be in an inconsistent state and cleanup following switchover may be necessary. Tri-state control of the state of the 0 Management Ethernet port, RS232 port, BIO expansion strobe, power/fan test signals, and selective reset strobes may be in an indeterminate state briefly during the switchover. However, the target resource in each case is insensitive to the brief indeterminate state. Relay controls revert to default values 5 on the new active control processor and require reinitialization.
When a control processor card is reset, the online status of that card is forced to be in the standby state. This precaution ensures that the card is held in the standby state 0 when plugged into the switch without powering-down, i.e., "hot-plugging." The precaution is necessary because it is otherwise possible for one side of the cross-coupled latch to power-ON
before the signal connector pins to the other side of the cross-coupled latch on an already connected and active control 5 processor have mated. When the control processor is fully _ 8 _ connected to the backplane connector a slide latch on the front of the card may be used to take the card out of reset. Upon release of the slide latch reset the control processor card retains the standby state if the card has been mated with the active control processor. If there is only one control processor installed in the switch then that control processor card will come out of reset in the active state.
Pulling a slide latch 100 on an active control processor card into a position where the card can be removed from the 0 card cage generates a NMI to the main processor unit 102 on the control processor card. About 40ms after receipt of the NMI
the control processor card is reset. Since reset forces the control processor into the standby state, the other control processor card will enter the active state. For the case of a 5 slide latch reset causing a control processor card switchover, software functions control shutting-dawn of central and internal resources, in contrast with the immediate disconnect caused by a faulty control processor card as described above.
The control processor card is illustrated in greater '0 detail in Fig. 2. The cell thread interfaces 30, 32 connect the control processors to a single port on each respective switch fabric card. In the present embodiment, the cell processor cards employ port 40 of a 40X40 switch fabric. This port is not shared with any I/O card. The interface employs 5 interface logic 104, a buffer management chip 106, and an ATMizer chip 108. A 100Mhz clock that is locked to a clock signal provided by the active timing module card through clock sync and regeneration logic 110, is generated for the interface logic 104 by board clock logic 44. The control processor card 0 also includes an FPGA based control processor Utopia Adapter 112 with a bidirectional single ATM cell deep FIFO memory to match a 16-bit, 50Mhz Utopia level-2 bus 114 of the buffer management chip to an 8-bit, 50Mhz, Utopia level-2 bus 116 of the ATMizer chip 108.
_ g The ATMizer 108 on the PAC 38 sends ATM cells to the thread interface and receives ATM cells from the thread interface over the Utopia2-PAC interface. The Utopia2-PAC
interface connects between the Utopia adapter 112 and the ATMizer 108 and includes two 8-bit point-to-Point busses with associated control logic. One bus accommodates an ingress thread 120 and one bus accommodates an egress thread 122.
These busses exchange data at 50Mhz through a connection between the PAC and control processor.
_0 The Ethernet controller 40 is programmed and accessed as a slave device via an 1960 local bus. Both control processor cards in the switch provide a twisted pair Ethernet interface 64 through transceiver 124. A relay selects the Ethernet interface from the active control processor card to connect to _5 a single RJ45 connector on the Control Processor Adapter ( "CPA" ) .
The control processor card includes a 2.5" ATA-2 (EIDE) laptop hard drive 42 which is accessed via the I960 local bus 34 through bus logic 126. The control processor may also '0 support a 175 Mbyte FLASH drive as an alternative to the hard drive.
All cards may be reset by the control processor via individual reset lines on the backplane. Selective reset logic on the control processor decodes writes to a selective reset .5 register. The writes are seen on the I960 bus and cause the assertion of appropriate reset lines to selected cards.
Referring to Figs. 2 and 4, each control processor card employs two 8-bit multiplexed 33MHz synchronized busses {"EMBusses") 130, 132. EMBus 130 of control processor card 12 0 connects to switch fabric 16 and EMBus 132 of control processor card 12 connects to switch fabric 18. Similarly, EMBus 130 of control processor card 14 connects to switch fabric 18 and EMBus 132 of control processor card 14 connects to switch fabric 16. The EMBusses associated with each respective 5 control processor card are independent of the other control processor cards to reduce the impact of bus failure. The EMBusses support connection to microprocessor interfaces within the switch. Multiplexing permits a lower pin count on the backplane. Since each EMBus is synchronous, bus clocks on the switch fabric and control processor cards are synchronized to each other. Further, all EMBus clock outputs from each control processor to each switch fabric have matched and specified lengths on the backplane.
The following signals are employed on the EMBusses:
0 EMBClk: EMBus Clock provides timing for all transaction on the EMBus. All bus signals are synchronous and sampled on the rising edge of EMBClk. The EMBClk frequency is 33 Mhz. This clock is driven by the control processor.
BCYCLE L: Bus Cycle Low is driven by the control processor to indicate the duration of a complete bus transaction. BCYCLE L is asserted at the beginning of each bus cycle in conjunction with '0 a first addressing phase. BCYCLE L is de-asserted prior to last data transfer, thereby signaling the termination of the transfer cycle is imminent upon completion of the data transfer. Deassertion of BCYCLE L is also 5 intended to reset slave bus controllers assuring synchronization of future bus transactions.
AD: The Address and Data on the EMBus are multiplexed on the same pins. Address is 0 asserted on the bus during the first one/two EMBClk cycles following the BCYCLE L going low.
Address is asserted in LSB/MSB order. After the addressing phase, the Data bus is turned around if necessary. In the case of a control 5 processor write cycle, Data is asserted immediately following the address phase. In the case of a control processor read cycle, the Switch Fabric asserts data onto the bus in conjunction with asserting SXRDY L.
WR L: Read/Write Low is asserted on the bus during the first address cycle and is held active throughout the complete bus cycle . A Read cycle occurs when WR L is low, and a write is _0 indicated when high.
SXRDY L: Slave Transfer Ready is driven low in conjunction with the switch fabric driving valid data in the case of a control processor or when _5 the switch fabric is ready to accept data in the case of a primary control processor write.
EMBINT L [1:0]: Expansion Mux Bus Interrupt Lines.
These signal the host processor that '0 an interrupt is pending.
An EMBus cycle has three phases. Phase 1, parts a and b, commence a bus transfer cycle at which address transfers take place. In Phase 2 the bus turns around, if needed, during the 5 read cycle. In Phase 3 data transfers take place. Phases and data transfers on the EMBusses are synchronously controlled.
BCYCLE L delineates a transfer cycle by marking the beginning and pending termination of a complete cycle. SXRDY L indicates the slave is ready to transmit or receive data.
0 An EMBus write cycle begins with the assertion of BCYCLE_L
and WR~L asserted high. Addressing occurs for two cycles.
Immediately following addressing, the data phase of bus operations takes place. Termination of the WRITE cycle concludes with SXRDY L asserted followed by BCYCLE_L
5 deassertion.
An EMBus read cycle begins with the assertion of BCYCLE L
low during which WR L asserted low. Addressing occurs for two cycles. Immediately following the addressing phase, the bus turnaround phase is instituted. Immediately following addressing, the data phase of bus operations takes place. Data is placed on the AD bus in conjunction with SXFRDY L.
Deassertion of BCYCLE L terminates the READ cycle.
Referring now to Fig. 5, each control processor 12, 14 in the network switch also provides interface busses 140, 142 to _0 the timing modules 20, 22. Only the active control processor is capable of sending-to or receiving-from either of these busses. The standby control processor is isolated, by tri-stating at high impedance, so as not to interfere with communications over the busses involving the active control _5 processor card.
Referring to Figs. 2 and 5, the control processor supports eight bidirectional data signals (in EMBusses 130, 132), address outputs (in timing module interface 48), chip selects (on the I960 bus 34), a soft reset output 150, an interrupt '0 input (on the timing module and switch fabric interfaces), and FPGA download connection for each timing module bus (through the timing module interface 48). Relays on the CPA connect the active control processor to buzzer control, the Ethernet network management port, and alarm contact closures. Both 5 control processor cards share an RS232 port 66 which provides connection to the PAC. The active PAC interfaces to the MIM
via a MIM signal path 58. The control processor card receives digital alarm/status signals from the AC to DC central power modules that generate -48V for the system. Both control 0 processor cards redundantly supply power to the CPA.
The control processor card collects interrupts from various sources including the timing modules, the disk drive, the Ethernet port, the interface logic 104, the buffer management chip 106, fan and power supply alarms. Each 5 interrupt source is returned to the PAC. The control processor provides masking, steering, and status registers for the various interrupt sources.
The power module 56 receives distributed power from the backplane and outputs regulated 3.3 V and 5 V power for components on both the PAC 38 and the control processor card.
The power module also facilitates "hot-plugging" and removal of the control processor card and receives redundant power feeds from the backplane so that the control processor card can continue operation should one of the feeds fail.
.0 The control processor includes an internal MIM device that is accessed via a MIM interface 152 from the PAC. The control processor card also includes eight external MIM interfaces to the timing modules, switch fabric cards, the power subsystem and the backplane. Only the active control processor controls _5 these MIM interfaces. The standby control processor is isolated from the MIM.interfaces. The control processor card is generally designed for in-circuit testability. IEEE 1149.1 boundary scan ports on components may be used to enhance manufacturing test or support In System Programmability ("ISP" ) :0 for Programmable Logic Devices ("PLDs") as needed. IEEE
standard Test Action Group pins are reserved on the connectors between the PAC and the Backplane, but are not presently used.
Having described the preferred embodiments of the invention, other embodiments which incorporate the concepts of 5 the presently disclosed invention will be apparent to those of ordinary skill in the art. Therefore, the invention should not be viewed as limited to the disclosed embodiments but rather should be viewed as limited only by the spirit and scope of the appended claims.
CONTROL PROCESSOR SWITCHOVER FOR A TELECOMMUNICATIONS SWITCH
CROSS REFERENCE TO RELATED APPLICATIONS
Not applicable STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR
DEVELOPMENT
Not applicable BACKGROUND OF THE INVENTION
The present invention is generally related to telecommunications switches, and more particularly to high reliability telecommunications switches employing redundant 0 control systems.
Telecommunications switches facilitate routing and transmission of data in telecommunications networks. Such switches typically include a plurality of Input/output ("I/O") cards which are interconnected through a switch fabric card.
5 In particular, the switch fabric interconnects each I/O card with every other I/0 card such that a data unit received at any I/O card can be transmitted to any other I/0 card in the switch.
In addition to interconnecting the I/O cards, the switch 0 fabric may function to control timing operations within the switch and allocate bandwidth to connections through the I/O
cards such that collisions are avoided. Such functionality is relatively complex to implement, and consequently switch fabric cards in a telecommunications switch are prone to failure. In 5 particular, control functions that are heavily software dependent are prone to failure due to software bugs. Such bugs may be triggered by specific sequences of events so the card can at times be restored through a reset operation. However, data can be lost in such a reset operation.
To avoid data loss and switch failure due to a switch fabric card failure it is known to employ redundant switch fabric cards. In particular, it is known to install a plurality of switch fabric cards in a single switch so that a standby switch fabric card can be employed in the event that the active switch fabric card fails. However, switch fabric cards are generally high cost items and it is therefore common 7 practice to install only one standby switch fabric card, which may not provide sufficient reliability.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a control processor card is employed in conjunction with a switch fabric card to interconnect Input/output (~~I/O~~) cards and control switch operation. The control processor card provides a portion of the functionality previously associated with switch fabric cards, such as exertion of control over allocation of bandwidth within the switch and also includes additional control and configuration functionality for a plurality of switch fabric cards, timing module cards and other core switch functions.
In the preferred embodiment first and second control processor cards are employed with first and second switch fabric cards and first and second timing control cards.
Redundant control processor cards and redundant switch fabric cards are employed to provide a switch that is less susceptible to failure than switches with only redundant switch fabric cards. Both active and standby control processor cards are coupled to active and standby switch fabric cards although only the active control processor card is used to control the switch fabric and other core functions at any given time. Upon > failure of the active control processor card, the standby control processor card becomes the active control processor card and the new standby card is reset or removed for repair.
Previously known switch fabric cards perform several complex functions including allocation of bandwidth, interconnection of I/0 cards and timing control. Such functions are software intensive and are generally more prone to failure than other portions of the switch. Failure of any one such function may result in failure of the entire switch fabric card. The present invention localizes failure of such 0 functions by associating performance of those functions with separate cards. Further, by employing redundancy in the control processor card, timing control modules and the switch fabrics, control processor card switchover may be accomplished using either switch fabric as the active switch fabric or 5 either timing control module as the active timing control module.
BRIEF DESCRIPTION OF THE DRAWING
0 The invention will be more fully understood in view of the following Detailed Description of the Invention; in conjunction with the Drawing, of which:
Fig. 1 is a block diagram of a telecommunications switch;
Fig. 2 is a block diagram of the control processor card of 5 Fig. 1;
Fig. 3 is a block diagram of a bistable latch;
Fig. 4 is a block diagram of the control processor busses of Fig. 1; and Fig. 5 is a block diagram of the timing control interface 0 busses of Fig. 1.
DETAILED DESCRIPTION OF THE INVENTION
Fig. 1 illustrates a telecommunications switch 10 having 5 two control processor cards 12, 14, two switch fabric cards 16, ' WO 99/11002 PCTlUS98/17535 18, two timing control module cards 20, 22 and a plurality of Input/output ("I/O") cards 24. All of the cards are interconnected for complete interoperability. The I/O cards 24 are interconnected through both switch fabric cards 16, 18 in a crossbar configuration such that a data unit that is received at any one of the I/O cards 24 can be transmitted to any other I/O card, regardless of which switch fabric card is in active use. Similarly, both of the control processor cards are each coupled to both of the switch fabric cards and both of the 0 timing control cards. The control processor cards are interconnected through shared control signals to a set of central switch resources 26.
The control processor cards 12, 14 function to configure the switch fabric cards, monitor the state of the switch, 5 control switch fabric switchover and control switch resources.
One particular resource that is controlled by the control processor cards is the bandwidth within the switch fabric. The switch fabric cards function to interconnect the I/O cards.
The timing control module cards provide clock signals and 0 control timing within the switch. The I/O cards provide an interface to other devices and may be configured to facilitate communication with specific protocols and connection types such as frame relay, Asynchronous Transfer Mode ("ATM"), Ethernet, Fiber Distributed Data Interface, token ring, Integrated Services Digital Network and T1.
Referring to Figs. 1 and 2, each control processor card 12, 14 includes redundant cell thread interfaces 30, 32 to the switch fabric cards 16, 18, an I960 bus interface 34 to an I960HD Processor and ATMizer Control ("PAC") 38, a lOMbps 0 Ethernet interface controller 40, a hard drive 42, selective reset logic 44, a redundant expansion bus 46 connected to the switch fabric cards, an interface 48 to the timing control module cards, interrupt logic 50 to sum indirect interrupts, and interface 52 to microprocessor ports of internal Application Specific Integrated Circuits ( "ASICs" ) , support for a redundant control processor cards, power module 56, Module Identification Memory ("MIM") interface 58, Light Emitting Diode ("LED") indicators 60 and test logic 62.
When the switch is powered-ON or reset, only one of the control processor cards 12, 14 can become active. The non active control processor card is considered to be in standby mode. An active control processor card is distinguished from a standby control processor card by having exclusive control over central resources and internal resources including the 0 Management Ethernet port 64, Management RS232 port 66, MIM
interface 58 (through which revision numbers and other information can be retrieved from cards in the switch), timing module board microprocessor interface bus, switch~fabric board microprocessor interface bus, selective resets to other system 5 boards, timing module FPGA download interface, switch fabric switchover synchronization backplane signal (SYNC TM), BIO
expansion bus strobe backplane signal, Power and Fan test signals, Buzzer relay and External alarm relays; none of which are implemented on the control processor cards. These 0 resources are not critical to operations of existing ATM
connections, and the resources can be unavailable for the time required to execute a control processor card switchover operation without causing switch failure. Similarly, one switch fabric and one timing control module will be in the 5 active mode during operation, while the non-active switch fabric card and timing control module will be in a standby mode.
Referring to Figs. 2 and 3, to implement redundancy the control processor cards 12, 14 can "switchover" between active 0 and standby modes so that a faulty control processor card can fail and be replaced by the standby control processor card without disrupting data flow. A bistable latch is formed with inverter type latch halves 80, 82 implemented on each control processor card. The latch halves are cross-coupled through a 5 backplane connector 84, and latch logic ensures that different logic levels are maintained at respective state indicator nodes 86, 88 on each control processor card. Relatively little hardware is used in the cross coupled latch to reduce the probability of failure in the bistable latch itself. Software may be employed to ensure that the standby control processor is functioning properly before allowing the switchover operation.
At power-ON the latch resolves the online state, i.e., active or standby, of each control processor card. This state is resolved randomly at power-ON. The online state of the 0 control processor card is employed within a few logic gate delays to control tri-stating of the central resources 26. In particular, the standby control processor card tri-states (at high impedance) any hardware buffers involved in the access of the central resources to avoid interference with the operation 5 of the active control processor.
The active control processor card periodically transmits an "active" or "keep alive" indicator signal 90 to the standby control processor card. The standby control processor monitors the state of the active control processor by receiving the 0 "active" signals from the active control processor through a dedicated backplane channel ("backchannel") 92. If the active control processor fails to send an "active" indicator signal, the standby control processor responds as though the active control processor is faulty. In particular, the standby 5 control processor begins termination of the active control processor by generating a "terminate" signal 94. The terminate signal toggles the state of the cross-coupled bistable latch.
Following the state change caused by the terminate signal the active control processor tri-states access to internal and 0 central resources. A non-maskable interrupt ("NMI") is then sent to the main processor unit. The processor unit in the active control processor card operates for approximately 40ms following receipt of the terminate signal 94 to clean up operations and store current state information to non-volatile 5 storage, at which point the standby control processor becomes -active and the formerly active control processor card is reset .
Following the reset cycle the terminated control processor card assumes standby status. The standby control processor can then be physically removed from the switch for diagnostic testing, repair or replacement.
During the control processor switchover operation any microprocessor transactions in progress in the active timing module and active switch fabric interface are completed before tri-stating is implemented. For example, microprocessor non-0 burst read/write cycles of single header fields are finished before tri-stating. The timing module FPGA download may be interrupted by the control processor switchover, in which case a "NOT DONE" status signal is generated to indicate an incomplete FPGA program cycle to the new active control 5 processor. Multiple microprocessor transactions are necessary to access the MIMs and for FPGA downloading. Consequently, transactions in progress to the MIMs may cause the target MIM
to be in an inconsistent state and cleanup following switchover may be necessary. Tri-state control of the state of the 0 Management Ethernet port, RS232 port, BIO expansion strobe, power/fan test signals, and selective reset strobes may be in an indeterminate state briefly during the switchover. However, the target resource in each case is insensitive to the brief indeterminate state. Relay controls revert to default values 5 on the new active control processor and require reinitialization.
When a control processor card is reset, the online status of that card is forced to be in the standby state. This precaution ensures that the card is held in the standby state 0 when plugged into the switch without powering-down, i.e., "hot-plugging." The precaution is necessary because it is otherwise possible for one side of the cross-coupled latch to power-ON
before the signal connector pins to the other side of the cross-coupled latch on an already connected and active control 5 processor have mated. When the control processor is fully _ 8 _ connected to the backplane connector a slide latch on the front of the card may be used to take the card out of reset. Upon release of the slide latch reset the control processor card retains the standby state if the card has been mated with the active control processor. If there is only one control processor installed in the switch then that control processor card will come out of reset in the active state.
Pulling a slide latch 100 on an active control processor card into a position where the card can be removed from the 0 card cage generates a NMI to the main processor unit 102 on the control processor card. About 40ms after receipt of the NMI
the control processor card is reset. Since reset forces the control processor into the standby state, the other control processor card will enter the active state. For the case of a 5 slide latch reset causing a control processor card switchover, software functions control shutting-dawn of central and internal resources, in contrast with the immediate disconnect caused by a faulty control processor card as described above.
The control processor card is illustrated in greater '0 detail in Fig. 2. The cell thread interfaces 30, 32 connect the control processors to a single port on each respective switch fabric card. In the present embodiment, the cell processor cards employ port 40 of a 40X40 switch fabric. This port is not shared with any I/O card. The interface employs 5 interface logic 104, a buffer management chip 106, and an ATMizer chip 108. A 100Mhz clock that is locked to a clock signal provided by the active timing module card through clock sync and regeneration logic 110, is generated for the interface logic 104 by board clock logic 44. The control processor card 0 also includes an FPGA based control processor Utopia Adapter 112 with a bidirectional single ATM cell deep FIFO memory to match a 16-bit, 50Mhz Utopia level-2 bus 114 of the buffer management chip to an 8-bit, 50Mhz, Utopia level-2 bus 116 of the ATMizer chip 108.
_ g The ATMizer 108 on the PAC 38 sends ATM cells to the thread interface and receives ATM cells from the thread interface over the Utopia2-PAC interface. The Utopia2-PAC
interface connects between the Utopia adapter 112 and the ATMizer 108 and includes two 8-bit point-to-Point busses with associated control logic. One bus accommodates an ingress thread 120 and one bus accommodates an egress thread 122.
These busses exchange data at 50Mhz through a connection between the PAC and control processor.
_0 The Ethernet controller 40 is programmed and accessed as a slave device via an 1960 local bus. Both control processor cards in the switch provide a twisted pair Ethernet interface 64 through transceiver 124. A relay selects the Ethernet interface from the active control processor card to connect to _5 a single RJ45 connector on the Control Processor Adapter ( "CPA" ) .
The control processor card includes a 2.5" ATA-2 (EIDE) laptop hard drive 42 which is accessed via the I960 local bus 34 through bus logic 126. The control processor may also '0 support a 175 Mbyte FLASH drive as an alternative to the hard drive.
All cards may be reset by the control processor via individual reset lines on the backplane. Selective reset logic on the control processor decodes writes to a selective reset .5 register. The writes are seen on the I960 bus and cause the assertion of appropriate reset lines to selected cards.
Referring to Figs. 2 and 4, each control processor card employs two 8-bit multiplexed 33MHz synchronized busses {"EMBusses") 130, 132. EMBus 130 of control processor card 12 0 connects to switch fabric 16 and EMBus 132 of control processor card 12 connects to switch fabric 18. Similarly, EMBus 130 of control processor card 14 connects to switch fabric 18 and EMBus 132 of control processor card 14 connects to switch fabric 16. The EMBusses associated with each respective 5 control processor card are independent of the other control processor cards to reduce the impact of bus failure. The EMBusses support connection to microprocessor interfaces within the switch. Multiplexing permits a lower pin count on the backplane. Since each EMBus is synchronous, bus clocks on the switch fabric and control processor cards are synchronized to each other. Further, all EMBus clock outputs from each control processor to each switch fabric have matched and specified lengths on the backplane.
The following signals are employed on the EMBusses:
0 EMBClk: EMBus Clock provides timing for all transaction on the EMBus. All bus signals are synchronous and sampled on the rising edge of EMBClk. The EMBClk frequency is 33 Mhz. This clock is driven by the control processor.
BCYCLE L: Bus Cycle Low is driven by the control processor to indicate the duration of a complete bus transaction. BCYCLE L is asserted at the beginning of each bus cycle in conjunction with '0 a first addressing phase. BCYCLE L is de-asserted prior to last data transfer, thereby signaling the termination of the transfer cycle is imminent upon completion of the data transfer. Deassertion of BCYCLE L is also 5 intended to reset slave bus controllers assuring synchronization of future bus transactions.
AD: The Address and Data on the EMBus are multiplexed on the same pins. Address is 0 asserted on the bus during the first one/two EMBClk cycles following the BCYCLE L going low.
Address is asserted in LSB/MSB order. After the addressing phase, the Data bus is turned around if necessary. In the case of a control 5 processor write cycle, Data is asserted immediately following the address phase. In the case of a control processor read cycle, the Switch Fabric asserts data onto the bus in conjunction with asserting SXRDY L.
WR L: Read/Write Low is asserted on the bus during the first address cycle and is held active throughout the complete bus cycle . A Read cycle occurs when WR L is low, and a write is _0 indicated when high.
SXRDY L: Slave Transfer Ready is driven low in conjunction with the switch fabric driving valid data in the case of a control processor or when _5 the switch fabric is ready to accept data in the case of a primary control processor write.
EMBINT L [1:0]: Expansion Mux Bus Interrupt Lines.
These signal the host processor that '0 an interrupt is pending.
An EMBus cycle has three phases. Phase 1, parts a and b, commence a bus transfer cycle at which address transfers take place. In Phase 2 the bus turns around, if needed, during the 5 read cycle. In Phase 3 data transfers take place. Phases and data transfers on the EMBusses are synchronously controlled.
BCYCLE L delineates a transfer cycle by marking the beginning and pending termination of a complete cycle. SXRDY L indicates the slave is ready to transmit or receive data.
0 An EMBus write cycle begins with the assertion of BCYCLE_L
and WR~L asserted high. Addressing occurs for two cycles.
Immediately following addressing, the data phase of bus operations takes place. Termination of the WRITE cycle concludes with SXRDY L asserted followed by BCYCLE_L
5 deassertion.
An EMBus read cycle begins with the assertion of BCYCLE L
low during which WR L asserted low. Addressing occurs for two cycles. Immediately following the addressing phase, the bus turnaround phase is instituted. Immediately following addressing, the data phase of bus operations takes place. Data is placed on the AD bus in conjunction with SXFRDY L.
Deassertion of BCYCLE L terminates the READ cycle.
Referring now to Fig. 5, each control processor 12, 14 in the network switch also provides interface busses 140, 142 to _0 the timing modules 20, 22. Only the active control processor is capable of sending-to or receiving-from either of these busses. The standby control processor is isolated, by tri-stating at high impedance, so as not to interfere with communications over the busses involving the active control _5 processor card.
Referring to Figs. 2 and 5, the control processor supports eight bidirectional data signals (in EMBusses 130, 132), address outputs (in timing module interface 48), chip selects (on the I960 bus 34), a soft reset output 150, an interrupt '0 input (on the timing module and switch fabric interfaces), and FPGA download connection for each timing module bus (through the timing module interface 48). Relays on the CPA connect the active control processor to buzzer control, the Ethernet network management port, and alarm contact closures. Both 5 control processor cards share an RS232 port 66 which provides connection to the PAC. The active PAC interfaces to the MIM
via a MIM signal path 58. The control processor card receives digital alarm/status signals from the AC to DC central power modules that generate -48V for the system. Both control 0 processor cards redundantly supply power to the CPA.
The control processor card collects interrupts from various sources including the timing modules, the disk drive, the Ethernet port, the interface logic 104, the buffer management chip 106, fan and power supply alarms. Each 5 interrupt source is returned to the PAC. The control processor provides masking, steering, and status registers for the various interrupt sources.
The power module 56 receives distributed power from the backplane and outputs regulated 3.3 V and 5 V power for components on both the PAC 38 and the control processor card.
The power module also facilitates "hot-plugging" and removal of the control processor card and receives redundant power feeds from the backplane so that the control processor card can continue operation should one of the feeds fail.
.0 The control processor includes an internal MIM device that is accessed via a MIM interface 152 from the PAC. The control processor card also includes eight external MIM interfaces to the timing modules, switch fabric cards, the power subsystem and the backplane. Only the active control processor controls _5 these MIM interfaces. The standby control processor is isolated from the MIM.interfaces. The control processor card is generally designed for in-circuit testability. IEEE 1149.1 boundary scan ports on components may be used to enhance manufacturing test or support In System Programmability ("ISP" ) :0 for Programmable Logic Devices ("PLDs") as needed. IEEE
standard Test Action Group pins are reserved on the connectors between the PAC and the Backplane, but are not presently used.
Having described the preferred embodiments of the invention, other embodiments which incorporate the concepts of 5 the presently disclosed invention will be apparent to those of ordinary skill in the art. Therefore, the invention should not be viewed as limited to the disclosed embodiments but rather should be viewed as limited only by the spirit and scope of the appended claims.
Claims (34)
1. A telecommunications switch, comprising:
a plurality of interface modules;
a plurality of interconnection modules connected to said interface modules, said interconnection modules providing physical connections between individual interface modules; and a plurality of control modules, each of said plurality of control modules interconnected with each one of said interconnection modules, wherein each of said plurality of control modules is operative to allocate bandwidth within each of said interconnection modules.
a plurality of interface modules;
a plurality of interconnection modules connected to said interface modules, said interconnection modules providing physical connections between individual interface modules; and a plurality of control modules, each of said plurality of control modules interconnected with each one of said interconnection modules, wherein each of said plurality of control modules is operative to allocate bandwidth within each of said interconnection modules.
2. The switch of claim 1 including an active control module and a standby control module.
3. The switch of claim 2 including an active interconnection module and a standby interconnection module.
4. The switch of claim 3 wherein each said control module is disposed on a separate respective printed circuit board.
5. The switch of claim 4 wherein each said interconnection module is disposed on a separate respective printed circuit board.
6. The switch of claim 5 wherein the standby control module is automatically activated upon failure of the active control module.
7. The switch of claim 6 wherein the standby interconnection module is automatically activated upon failure of the active interconnection module.
8. A telecommunications switch, comprising:
a plurality of interface modules;
a plurality of interconnection modules connected to said interface modules, said interconnection modules providing physical connections between individual interface modules, said interconnection modules including an active interconnection module and a standby interconnection module, wherein said standby interconnection module is automatically activated upon failure of the active interconnection module, and wherein each of said plurality of interconnection modules is disposed on a separate respective printed circuit board;
a plurality of control modules operative to configure the interconnection modules, wherein said plurality of control modules include an active control module and a standby control module, wherein said standby control module is automatically activated upon failure of said active control module, wherein each of said plurality of control modules is disposed on a separate respective printed circuit board, wherein each control module includes a latch portion that controls switch state, the active control module latch portion combining with the standby control module latch portion to provide a bistable latch that prevents the control modules from being simultaneously active.
a plurality of interface modules;
a plurality of interconnection modules connected to said interface modules, said interconnection modules providing physical connections between individual interface modules, said interconnection modules including an active interconnection module and a standby interconnection module, wherein said standby interconnection module is automatically activated upon failure of the active interconnection module, and wherein each of said plurality of interconnection modules is disposed on a separate respective printed circuit board;
a plurality of control modules operative to configure the interconnection modules, wherein said plurality of control modules include an active control module and a standby control module, wherein said standby control module is automatically activated upon failure of said active control module, wherein each of said plurality of control modules is disposed on a separate respective printed circuit board, wherein each control module includes a latch portion that controls switch state, the active control module latch portion combining with the standby control module latch portion to provide a bistable latch that prevents the control modules from being simultaneously active.
9. The switch of claim 8 wherein the control modules are mounted in a card cage in the switch, and wherein removal of the active control module from the card cage automatically activates the standby control module.
10. A method for transmitting data associated with data channels in a telecommunications switch having a plurality of interface modules, comprising the steps of:
providing physical connections between individual interface modules with a plurality of interconnection modules;
configuring the interconnection modules with at least one of a plurality of control modules; and allocating the physical connections provided by the interconnection module to data channels formed through the switch with the at least one control module, wherein each of said plurality of control modules are interconnected to each of said interconnection modules, and wherein each of said plurality of control modules is operative to allocate bandwidth within each of said interconnection modules.
providing physical connections between individual interface modules with a plurality of interconnection modules;
configuring the interconnection modules with at least one of a plurality of control modules; and allocating the physical connections provided by the interconnection module to data channels formed through the switch with the at least one control module, wherein each of said plurality of control modules are interconnected to each of said interconnection modules, and wherein each of said plurality of control modules is operative to allocate bandwidth within each of said interconnection modules.
11. The method of claim 10 wherein first and second control modules are employed and including the further step of designating the first control module as an active control module and designating the second control module as a standby control module.
12. The method of claim 11 wherein first and second interconnection modules are employed and including the further step of designating the first interconnection module as an active interconnection module and designating the second interconnection module as a standby interconnection module.
13. The method of claim 12 wherein each said control module is located on a separate respective printed circuit board.
14. The method of claim 13 wherein each said interconnection module is located on a separate respective printed circuit board.
15. The method of claim 14 including the further step of automatically activating the standby control module upon failure of the active control module.
16. The method of claim 15 including the further step of automatically activating the standby interconnection module upon failure of the active interconnection module.
17. A method for transmitting data in a telecommunications switch, comprising the steps of:
providing physical connections between individual interface modules with a plurality of interconnection modules;
configuring the interconnection modules with at least one of a plurality of control modules;
allocating the physical connections provided by the interconnection module to data channels formed through the switch with the at least one control module;
designating a first control module as an active control module and designating a second control module as a standby control module;
designating a first interconnection module as an active interconnection module and designating a second interconnection module as a standby interconnection module;
automatically activating the standby control module upon failure of the active control module;
automatically activating the standby interconnection module upon failure of the active interconnection module; and wherein each control module includes a latch portion that controls switch state, and including the further step of combining the active control module latch portion with the standby control module latch portion to provide a bistable latch that prevents the control modules from being simultaneously active.
providing physical connections between individual interface modules with a plurality of interconnection modules;
configuring the interconnection modules with at least one of a plurality of control modules;
allocating the physical connections provided by the interconnection module to data channels formed through the switch with the at least one control module;
designating a first control module as an active control module and designating a second control module as a standby control module;
designating a first interconnection module as an active interconnection module and designating a second interconnection module as a standby interconnection module;
automatically activating the standby control module upon failure of the active control module;
automatically activating the standby interconnection module upon failure of the active interconnection module; and wherein each control module includes a latch portion that controls switch state, and including the further step of combining the active control module latch portion with the standby control module latch portion to provide a bistable latch that prevents the control modules from being simultaneously active.
18. The method of claim 17 wherein the control modules are mounted in a card cage in the switch, and including the further step of automatically activating the standby control module upon removal of the active control module from the card cage.
19. A telecommunications switch for transmitting data associated with data channels, comprising:
at least two switch fabric modules each having a plurality of inputs and outputs, one of said two switch fabric modules being in an active state and the remaining ones of said switch fabric being in a standby state;
at least two control processor modules, one of said control processor modules being in an active state and the remaining ones of said control processor modules being in a standby state, each of said at least two control modules being electronically coupled to each of said at least two switch fabric modules, wherein each of said at least two control processor modules is operative to allocate bandwidth in each of said at least two switch fabric modules; and said active control processor module being operative to configure said first and second switch fabric modules, and wherein the active one of said switch fabric modules is operative to forward data units from said switch fabric module inputs to said outputs.
at least two switch fabric modules each having a plurality of inputs and outputs, one of said two switch fabric modules being in an active state and the remaining ones of said switch fabric being in a standby state;
at least two control processor modules, one of said control processor modules being in an active state and the remaining ones of said control processor modules being in a standby state, each of said at least two control modules being electronically coupled to each of said at least two switch fabric modules, wherein each of said at least two control processor modules is operative to allocate bandwidth in each of said at least two switch fabric modules; and said active control processor module being operative to configure said first and second switch fabric modules, and wherein the active one of said switch fabric modules is operative to forward data units from said switch fabric module inputs to said outputs.
20. The switch of claim 19 wherein the switch includes an Ethernet port that is controlled by the active control processor module.
-19a-
-19a-
21. The switch of claim 19 wherein the switch includes an RS232 port that is controlled by the active control processor module.
22. A telecommunications switch for transmitting data associated with data channels, comprising:
at least two switch fabric modules each having a plurality of inputs and outputs, one of said two switch fabric modules being in an active state and the remaining ones of said switch fabric being in a standby state;
at least two control processor modules, one of said control processor modules being in an active state and the remaining ones of said control processor modules being in a standby state, each of said at least two control modules being electronically coupled to each of said at least two switch fabric modules;
said active control processor module being operative to configure said first and second switch fabric modules, and wherein the active one of said switch fabric modules is operative to forward data units from said switch fabric module inputs to said output, wherein the switch fabric modules each include a revision identifier stored in memory, and wherein the active control processor module has access to such memory.
at least two switch fabric modules each having a plurality of inputs and outputs, one of said two switch fabric modules being in an active state and the remaining ones of said switch fabric being in a standby state;
at least two control processor modules, one of said control processor modules being in an active state and the remaining ones of said control processor modules being in a standby state, each of said at least two control modules being electronically coupled to each of said at least two switch fabric modules;
said active control processor module being operative to configure said first and second switch fabric modules, and wherein the active one of said switch fabric modules is operative to forward data units from said switch fabric module inputs to said output, wherein the switch fabric modules each include a revision identifier stored in memory, and wherein the active control processor module has access to such memory.
23. The switch of claim 19 wherein the standby control processor module is automatically activated upon failure of the active control module.
-19b-
-19b-
24. The switch of claim 23 wherein the standby switch fabric module is automatically activated upon failure of the active switch fabric module.
25. The switch of claim 24 wherein each control processor module includes a latch portion that controls switch state, the active control processor module latch portion combining with the standby control processor module latch portion to provide a bistable latch that prevents the control processor modules from being simultaneously active.
26. The switch of claim 25 wherein the control processor modules are mounted in a card cage in the switch, and wherein removal of the active control processor module from the card cage automatically activates the standby control processor module.
27. A method for transmitting data associated with data channels in a telecommunications switch, comprising the steps of:
setting one of two switch fabric modules in an active state and the other of said two switch fabric modules in a standby state, each switch fabric module having a plurality of inputs and outputs:
setting one of at least two control processor modules in an active state and the remaining ones of said at least two control processor modules in a standby state, each of said at -19c-least two control processor modules being electronically coupled to each of said at least two switch fabric modules, wherein each of said at least two control processor modules is operative to allocate bandwidth within each of said switch modules;
configuring said first and second switch fabric modules with said active control module; and forwarding data units received at inputs of the active switch fabric module to outputs of said switch fabric module.
setting one of two switch fabric modules in an active state and the other of said two switch fabric modules in a standby state, each switch fabric module having a plurality of inputs and outputs:
setting one of at least two control processor modules in an active state and the remaining ones of said at least two control processor modules in a standby state, each of said at -19c-least two control processor modules being electronically coupled to each of said at least two switch fabric modules, wherein each of said at least two control processor modules is operative to allocate bandwidth within each of said switch modules;
configuring said first and second switch fabric modules with said active control module; and forwarding data units received at inputs of the active switch fabric module to outputs of said switch fabric module.
28. The method of claim 27 wherein the switch includes an Ethernet port and including the further step of controlling the Ethernet port with the active control processor module.
29. The method of claim 27 wherein the switch includes an RS232 port and including the further step of controlling the RS232 port with the active control processor module.
30. A method for transmitting data associated with data channels in a telecommunications switch, comprising the steps of:
setting one of two switch fabric modules in an active state and the other of said two switch fabric modules in a standby state, each switch fabric module having a plurality of inputs and outputs;
setting one of at least two control processor modules in an active state and the remaining ones of said at least two control processor modules in a standby state, each of said at -19d-least two control processor modules being electronically coupled to each of said at least two switch fabric modules;
configuring said first and second switch fabric modules with said active control module; and forwarding data units received at inputs of the active switch fabric module to outputs of said switch fabric module wherein the switch fabric modules each include a revision identifier stored in memory, and including the further step of accessing at least one such identifier with the active control processor module.
setting one of two switch fabric modules in an active state and the other of said two switch fabric modules in a standby state, each switch fabric module having a plurality of inputs and outputs;
setting one of at least two control processor modules in an active state and the remaining ones of said at least two control processor modules in a standby state, each of said at -19d-least two control processor modules being electronically coupled to each of said at least two switch fabric modules;
configuring said first and second switch fabric modules with said active control module; and forwarding data units received at inputs of the active switch fabric module to outputs of said switch fabric module wherein the switch fabric modules each include a revision identifier stored in memory, and including the further step of accessing at least one such identifier with the active control processor module.
31. The method of claim 27 including the further step of automatically activating the standby control processor module upon detection of failure of the active control module.
32. The method of claim 31 including the further step of automatically activating the standby switch fabric module upon detection of failure of the active switch fabric module.
33. A method for transmitting data associated with data channels in a telecommunications switch, comprising the steps of:
setting one of two switch fabric modules in an active state and the other of said two switch fabric modules in a standby state, each switch fabric module having a plurality of inputs and outputs;
-19e-setting one of at least two control processor modules in an active state and the remaining ones of said at least two control processor modules in a standby state, each of said at least two control processor modules being electronically coupled to each of said at least two switch fabric modules;
configuring said first and second switch fabric modules with said active control module;
forwarding data units received at inputs of the active switch fabric module to outputs of said switch fabric module;
automatically activating the standby switch fabric module upon detection of failure of the active switch fabric module;
automatically activating the standby switch fabric module upon detection of failure of the active switch fabric module;
and wherein each control processor module includes a latch portion that controls switch state, and including the further step of combining the active control processor module latch portion with the standby control processor module latch portion to provide a bistable latch that prevents the control processor modules from being simultaneously active.
setting one of two switch fabric modules in an active state and the other of said two switch fabric modules in a standby state, each switch fabric module having a plurality of inputs and outputs;
-19e-setting one of at least two control processor modules in an active state and the remaining ones of said at least two control processor modules in a standby state, each of said at least two control processor modules being electronically coupled to each of said at least two switch fabric modules;
configuring said first and second switch fabric modules with said active control module;
forwarding data units received at inputs of the active switch fabric module to outputs of said switch fabric module;
automatically activating the standby switch fabric module upon detection of failure of the active switch fabric module;
automatically activating the standby switch fabric module upon detection of failure of the active switch fabric module;
and wherein each control processor module includes a latch portion that controls switch state, and including the further step of combining the active control processor module latch portion with the standby control processor module latch portion to provide a bistable latch that prevents the control processor modules from being simultaneously active.
34. The method of claim 33 wherein the control processor modules are mounted in a card cage in the switch, and including the further step of automatically activating the standby control processor module upon removal of the active control processor module from the card cage.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/919,828 US5953314A (en) | 1997-08-28 | 1997-08-28 | Control processor switchover for a telecommunications switch |
US08/919,828 | 1997-08-28 | ||
PCT/US1998/017535 WO1999011002A1 (en) | 1997-08-28 | 1998-08-25 | Control processor switchover for a telecommunications switch |
Publications (1)
Publication Number | Publication Date |
---|---|
CA2302500A1 true CA2302500A1 (en) | 1999-03-04 |
Family
ID=25442720
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002302500A Abandoned CA2302500A1 (en) | 1997-08-28 | 1998-08-25 | Control processor switchover for a telecommunications switch |
Country Status (5)
Country | Link |
---|---|
US (1) | US5953314A (en) |
EP (1) | EP1010277A4 (en) |
AU (1) | AU9118398A (en) |
CA (1) | CA2302500A1 (en) |
WO (1) | WO1999011002A1 (en) |
Families Citing this family (93)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6195351B1 (en) * | 1998-01-28 | 2001-02-27 | 3Com Corporation | Logical switch set |
JP3794151B2 (en) * | 1998-02-16 | 2006-07-05 | 株式会社日立製作所 | Information processing apparatus having crossbar switch and crossbar switch control method |
WO1999053627A1 (en) | 1998-04-10 | 1999-10-21 | Chrimar Systems, Inc. Doing Business As Cms Technologies | System for communicating with electronic equipment on a network |
US6327243B1 (en) * | 1998-08-03 | 2001-12-04 | Samsung Electronics Co., Ltd. | System and method for performing a seamless switchover from a primary packet router to a secondary packet router |
US6628648B1 (en) * | 1998-09-18 | 2003-09-30 | The United States Of America As Represented By The Secretary Of The Navy | Multi-interface point-to-point switching system (MIPPSS) with hot swappable boards |
US6898189B1 (en) * | 2000-08-23 | 2005-05-24 | Cisco Technology, Inc. | Restartable spanning tree for high availability network systems |
US6707789B1 (en) * | 1998-12-18 | 2004-03-16 | At&T Corp. | Flexible SONET ring with integrated cross-connect system |
US7551549B1 (en) * | 1999-03-24 | 2009-06-23 | Alcatel-Lucent Canada Inc. | Method and apparatus for line card redundancy in a communication switch |
US6748474B1 (en) * | 2000-02-25 | 2004-06-08 | Telica, Inc. | Midplane apparatus |
US7164698B1 (en) * | 2000-03-24 | 2007-01-16 | Juniper Networks, Inc. | High-speed line interface for networking devices |
US7139282B1 (en) | 2000-03-24 | 2006-11-21 | Juniper Networks, Inc. | Bandwidth division for packet processing |
US6778491B1 (en) * | 2000-03-31 | 2004-08-17 | Alcatel | Method and system for providing redundancy for signaling link modules in a telecommunication system |
US7079525B1 (en) | 2000-04-27 | 2006-07-18 | Cisco Technology, Inc. | Network switch having a hybrid switch architecture |
US6880086B2 (en) | 2000-05-20 | 2005-04-12 | Ciena Corporation | Signatures for facilitating hot upgrades of modular software components |
US7266595B1 (en) | 2000-05-20 | 2007-09-04 | Ciena Corporation | Accessing network device data through user profiles |
US7143153B1 (en) | 2000-11-09 | 2006-11-28 | Ciena Corporation | Internal network device dynamic health monitoring |
US20020001307A1 (en) * | 2000-05-20 | 2002-01-03 | Equipe Communications Corporation | VPI/VCI availability index |
US7240364B1 (en) | 2000-05-20 | 2007-07-03 | Ciena Corporation | Network device identity authentication |
US7222147B1 (en) | 2000-05-20 | 2007-05-22 | Ciena Corporation | Processing network management data in accordance with metadata files |
US7225244B2 (en) * | 2000-05-20 | 2007-05-29 | Ciena Corporation | Common command interface |
US7111053B1 (en) | 2000-05-20 | 2006-09-19 | Ciena Corporation | Template-driven management of telecommunications network via utilization of operations support services clients |
US20020116485A1 (en) * | 2001-02-21 | 2002-08-22 | Equipe Communications Corporation | Out-of-band network management channels |
US6654903B1 (en) | 2000-05-20 | 2003-11-25 | Equipe Communications Corporation | Vertical fault isolation in a computer system |
US6876652B1 (en) | 2000-05-20 | 2005-04-05 | Ciena Corporation | Network device with a distributed switch fabric timing system |
US6332198B1 (en) | 2000-05-20 | 2001-12-18 | Equipe Communications Corporation | Network device for supporting multiple redundancy schemes |
US7225240B1 (en) | 2000-05-20 | 2007-05-29 | Ciena Corporation | Decoupling processes from hardware with logical identifiers |
US6934749B1 (en) | 2000-05-20 | 2005-08-23 | Ciena Corporation | Tracking distributed data retrieval in a network device |
US7039046B1 (en) | 2000-05-20 | 2006-05-02 | Ciena Corporation | Network device including central and distributed switch fabric subsystems |
US6658579B1 (en) | 2000-05-20 | 2003-12-02 | Equipe Communications Corporation | Network device with local timing systems for automatic selection between redundant, synchronous central timing systems |
US6671699B1 (en) | 2000-05-20 | 2003-12-30 | Equipe Communications Corporation | Shared database usage in network devices |
US7349960B1 (en) | 2000-05-20 | 2008-03-25 | Ciena Corporation | Throttling distributed statistical data retrieval in a network device |
US7130870B1 (en) | 2000-05-20 | 2006-10-31 | Ciena Corporation | Method for upgrading embedded configuration databases |
US7020696B1 (en) | 2000-05-20 | 2006-03-28 | Ciena Corp. | Distributed user management information in telecommunications networks |
US6868092B1 (en) | 2000-05-20 | 2005-03-15 | Ciena Corporation | Network device with embedded timing synchronization |
US6658580B1 (en) | 2000-05-20 | 2003-12-02 | Equipe Communications Corporation | Redundant, synchronous central timing systems with constant master voltage controls and variable slave voltage controls |
US7062642B1 (en) | 2000-05-20 | 2006-06-13 | Ciena Corporation | Policy based provisioning of network device resources |
US6639910B1 (en) | 2000-05-20 | 2003-10-28 | Equipe Communications Corporation | Functional separation of internal and external controls in network devices |
US7051097B1 (en) | 2000-05-20 | 2006-05-23 | Ciena Corporation | Embedded database for computer system management |
US6760339B1 (en) | 2000-05-20 | 2004-07-06 | Equipe Communications Corporation | Multi-layer network device in one telecommunications rack |
US6708291B1 (en) | 2000-05-20 | 2004-03-16 | Equipe Communications Corporation | Hierarchical fault descriptors in computer systems |
US6715097B1 (en) | 2000-05-20 | 2004-03-30 | Equipe Communications Corporation | Hierarchical fault management in computer systems |
US6601186B1 (en) | 2000-05-20 | 2003-07-29 | Equipe Communications Corporation | Independent restoration of control plane and data plane functions |
US6742134B1 (en) | 2000-05-20 | 2004-05-25 | Equipe Communications Corporation | Maintaining a local backup for data plane processes |
US7054272B1 (en) | 2000-07-11 | 2006-05-30 | Ciena Corporation | Upper layer network device including a physical layer test port |
US7023845B1 (en) * | 2000-06-13 | 2006-04-04 | Ciena Corporation | Network device including multiple mid-planes |
US6906999B1 (en) * | 2000-06-30 | 2005-06-14 | Marconi Intellectual Property (Ringfence), Inc. | Receiver decoding algorithm to allow hitless N+1 redundancy in a switch |
US6973026B1 (en) * | 2000-06-30 | 2005-12-06 | Intel Corporation | Resilient chassis-based network switching |
US6473433B1 (en) * | 2000-06-30 | 2002-10-29 | Marconi Communications, Inc. | Queue resynch: synchronous real-time upgrade of a distributed switching system |
US6591324B1 (en) * | 2000-07-12 | 2003-07-08 | Nexcom International Co. Ltd. | Hot swap processor card and bus |
EP1195951A3 (en) * | 2000-08-10 | 2002-11-20 | Alcatel | Method and apparatus for maintaining data communication during a line card soft reset operation |
US6651131B1 (en) * | 2000-09-06 | 2003-11-18 | Sun Microsystems, Inc. | High bandwidth network and storage card |
DE60130082T2 (en) | 2000-09-20 | 2008-05-15 | Broadcom Corp., Irvine | Switching arrangement with several modules in one frame |
US7061907B1 (en) * | 2000-09-26 | 2006-06-13 | Dell Products L.P. | System and method for field upgradeable switches built from routing components |
AU2002236447A1 (en) | 2000-11-21 | 2002-06-03 | Transwitch Corporation | Methods and apparatus for switching atm, tdm, and packet data through a single communications switch |
US6996116B2 (en) * | 2000-11-22 | 2006-02-07 | International Business Machines Corporation | Switching nodes and interface modules for data networks |
US7200107B2 (en) * | 2001-01-06 | 2007-04-03 | Mindspeed Technologies, Inc. | Method and apparatus for lossless switchover in a redundant switch fabric |
US20020103921A1 (en) * | 2001-01-31 | 2002-08-01 | Shekar Nair | Method and system for routing broadband internet traffic |
US7263597B2 (en) * | 2001-04-19 | 2007-08-28 | Ciena Corporation | Network device including dedicated resources control plane |
US6839858B1 (en) * | 2001-05-14 | 2005-01-04 | Ciena Corporation | System for clock synchronization |
US6839866B2 (en) * | 2001-05-31 | 2005-01-04 | Sycamore Networks, Inc. | System and method for the use of reset logic in high availability systems |
US6721312B2 (en) * | 2001-06-01 | 2004-04-13 | Pluris, Inc. | Method and apparatus for improving data transmission in router fabric cards through pseudo-synchronous data switching |
US6980568B1 (en) * | 2001-07-17 | 2005-12-27 | Ciena Corporation | Method and apparatus for system clock synchronization |
US7227870B2 (en) * | 2001-11-20 | 2007-06-05 | Broadcom Corporation | Systems including packet interfaces, switches, and packet DMA circuits for splitting and merging packet streams |
US7313089B2 (en) * | 2001-12-21 | 2007-12-25 | Agere Systems Inc. | Method and apparatus for switching between active and standby switch fabrics with no loss of data |
EP1331769B1 (en) * | 2002-01-24 | 2005-08-31 | Alcatel Canada Inc. | Method and apparatus for providing redundant protocol processes in a network element |
US6856045B1 (en) * | 2002-01-29 | 2005-02-15 | Hamilton Sundstrand Corporation | Power distribution assembly with redundant architecture |
US6941487B1 (en) | 2002-03-07 | 2005-09-06 | Riverstone Networks, Inc. | Method, system, and computer program product for providing failure protection in a network node |
US7017074B2 (en) * | 2002-03-12 | 2006-03-21 | Sun Microsystems, Inc. | System architecture providing redundant components to improve die yields and system reliability |
WO2003077732A2 (en) * | 2002-03-14 | 2003-09-25 | Inovise Medical, Inc. | Method and system for detection of left ventricular hypertrophy |
US7170895B2 (en) * | 2002-03-29 | 2007-01-30 | Tropic Networks Inc. | Switch and a switching apparatus for a communication network |
US7430735B1 (en) | 2002-05-07 | 2008-09-30 | Lucent Technologies Inc. | Method, system, and computer program product for providing a software upgrade in a network node |
US7181567B2 (en) | 2002-06-04 | 2007-02-20 | Lucent Technologies Inc. | Hitless restart of access control module |
US7194652B2 (en) * | 2002-10-29 | 2007-03-20 | Brocade Communications Systems, Inc. | High availability synchronization architecture |
US7284236B2 (en) * | 2002-10-29 | 2007-10-16 | Brocade Communications Systems, Inc. | Mechanism to change firmware in a high availability single processor system |
US7188237B2 (en) * | 2002-10-29 | 2007-03-06 | Brocade Communication Systems, Inc. | Reboot manager usable to change firmware in a high availability single processor system |
JP2004287475A (en) * | 2003-01-27 | 2004-10-14 | Fujitsu Ten Ltd | Electronic controller and electronic driving device |
US7742401B2 (en) * | 2003-08-11 | 2010-06-22 | Netapp, Inc. | Network having switchover with no data loss |
CN1852456A (en) * | 2005-11-30 | 2006-10-25 | 华为技术有限公司 | System for realizing business switch-over and method therefor |
US7680034B2 (en) * | 2006-11-03 | 2010-03-16 | General Electric Company | Redundant control systems and methods |
US8355317B1 (en) * | 2007-10-31 | 2013-01-15 | World Wide Packets, Inc. | Transaction-based coordination of data object modification for primary and backup control circuitry |
US7839611B2 (en) * | 2007-11-14 | 2010-11-23 | General Electric Company | Programmable logic controller having micro-electromechanical system based switching |
US8244596B2 (en) * | 2008-01-02 | 2012-08-14 | Pure Verticals | Method and system for monetizing third-party content |
CN101272514B (en) * | 2008-05-09 | 2011-10-26 | 北京方天长久科技有限公司 | Hot-plug redundant communication device in railway communication |
CN101645779A (en) * | 2008-08-08 | 2010-02-10 | 鸿富锦精密工业(深圳)有限公司 | Network data transmission equipment |
US8990633B2 (en) * | 2009-04-21 | 2015-03-24 | Freescale Semiconductor, Inc. | Tracing support for interconnect fabric |
US8184648B2 (en) | 2009-06-18 | 2012-05-22 | Rockstar Bidco, LP | Method and apparatus for implementing control of multiple physically dual homed devices |
US8630287B2 (en) * | 2010-08-20 | 2014-01-14 | Marvell Israel (M.I.S.L) Ltd. | Multiple core network device with core redundancy |
DE102011082943A1 (en) * | 2011-09-19 | 2013-03-21 | Siemens Aktiengesellschaft | Network device and network arrangement |
DE102012000188B4 (en) * | 2012-01-09 | 2015-05-28 | Siemens Aktiengesellschaft | Method for operating a communication network and network arrangement |
US9229895B2 (en) * | 2012-09-13 | 2016-01-05 | Intel Corporation | Multi-core integrated circuit configurable to provide multiple logical domains |
US9526285B2 (en) | 2012-12-18 | 2016-12-27 | Intel Corporation | Flexible computing fabric |
JP6429188B2 (en) * | 2014-11-25 | 2018-11-28 | APRESIA Systems株式会社 | Relay device |
US11394643B2 (en) * | 2020-07-07 | 2022-07-19 | Ciena Corporation | In-service software upgrade systems and methods utilizing two router processors in a network element |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3303474A (en) * | 1963-01-17 | 1967-02-07 | Rca Corp | Duplexing system for controlling online and standby conditions of two computers |
FR2176279A5 (en) * | 1972-03-17 | 1973-10-26 | Materiel Telephonique | |
US3920977A (en) * | 1973-09-10 | 1975-11-18 | Gte Automatic Electric Lab Inc | Arrangement and method for switching the electronic subsystems of a common control communication switching system without interference to call processing |
US4442502A (en) * | 1981-03-30 | 1984-04-10 | Datapoint Corporation | Digital information switching system |
IT1194131B (en) * | 1981-12-23 | 1988-09-14 | Italtel Spa | CIRCUIT PROVISION SUITABLE TO CONNECT A PLURALITY OF COUPLES OF PROCESSORS TO AN ADDITIONAL COUPLE OF HIGHER HIERARCHY PROCESSORS |
US5251299A (en) * | 1985-12-28 | 1993-10-05 | Fujitsu Limited | System for switching between processors in a multiprocessor system |
US5291489A (en) * | 1987-11-13 | 1994-03-01 | Dsc Communications Corporation | Interprocessor switching network |
US5422880A (en) * | 1993-04-05 | 1995-06-06 | Stratacom, Inc. | Broadband switching fabric in a communication controller |
JPH0779233A (en) * | 1993-06-29 | 1995-03-20 | Synoptics Commun Inc | Apparatus for establishing topology, method and apparatus for communicating topology information |
-
1997
- 1997-08-28 US US08/919,828 patent/US5953314A/en not_active Expired - Lifetime
-
1998
- 1998-08-25 AU AU91183/98A patent/AU9118398A/en not_active Abandoned
- 1998-08-25 CA CA002302500A patent/CA2302500A1/en not_active Abandoned
- 1998-08-25 WO PCT/US1998/017535 patent/WO1999011002A1/en active Application Filing
- 1998-08-25 EP EP98943365A patent/EP1010277A4/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
US5953314A (en) | 1999-09-14 |
EP1010277A4 (en) | 2002-07-17 |
EP1010277A1 (en) | 2000-06-21 |
AU9118398A (en) | 1999-03-16 |
WO1999011002A1 (en) | 1999-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5953314A (en) | Control processor switchover for a telecommunications switch | |
US6275864B1 (en) | Matrix switch for a network management system | |
US4442502A (en) | Digital information switching system | |
US7293182B2 (en) | Methods and apparatus for powering a data communications port | |
TWI621022B (en) | Implementing cable failover in multiple cable pci express io interconnections | |
US7644215B2 (en) | Methods and systems for providing management in a telecommunications equipment shelf assembly using a shared serial bus | |
US6233635B1 (en) | Diagnostic/control system using a multi-level I2C bus | |
US6131169A (en) | Reliability of crossbar switches in an information processing system | |
US6148002A (en) | Shared auto-negotiation logic for multiple port network devices | |
US4961140A (en) | Apparatus and method for extending a parallel synchronous data and message bus | |
US6253269B1 (en) | Bus arbiter system and method for managing communication buses | |
EP0674274A1 (en) | Backplane unit isolation system | |
JPS6333945A (en) | Local area data distribution system | |
US5938728A (en) | Apparatus and method for selectively controlling clocking and resetting of a network interface | |
US4485467A (en) | Digital information switch matrix with on-line/off-line diagnostic features | |
US20040133819A1 (en) | System and method for providing a persistent power mask | |
US5831805A (en) | Local power failure detection and clock disabling circuit | |
US6715019B1 (en) | Bus reset management by a primary controller card of multiple controller cards | |
AU595712B2 (en) | Node for backplane bus | |
US20040162928A1 (en) | High speed multiple ported bus interface reset control system | |
US6564340B1 (en) | Fault tolerant virtual VMEbus backplane design | |
US6760849B1 (en) | Event initiation bus and associated fault protection for a telecommunications device | |
JP2001251328A (en) | Multiplex port ethernet (r) unit, and method and system for minimizing external pin | |
US6801973B2 (en) | Hot swap circuit module | |
US20040162927A1 (en) | High speed multiple port data bus interface architecture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FZDE | Dead |