CA2309820A1 - Content addressable memory (cam) engine - Google Patents

Content addressable memory (cam) engine Download PDF

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Publication number
CA2309820A1
CA2309820A1 CA002309820A CA2309820A CA2309820A1 CA 2309820 A1 CA2309820 A1 CA 2309820A1 CA 002309820 A CA002309820 A CA 002309820A CA 2309820 A CA2309820 A CA 2309820A CA 2309820 A1 CA2309820 A1 CA 2309820A1
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Prior art keywords
key
stored
presented
record
memory
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CA002309820A
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French (fr)
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CA2309820C (en
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Timothy A. Melchior
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Frontgrade Colorado Springs LLC
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Individual
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G06F16/90339—Query processing by using parallel associative memories or content-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y10S707/99933—Query processing, i.e. searching

Abstract

A content addressable memory ("CAM") engine (100) or controller interfaces between a host signal processor (e.g., a microprocessor) and a plurality of known, commercially-available random access memory ("RAM") devices. The CAM engine (100) configures the RAM as content addressable memory, thereby causing the normally location-addressd RAM to function as CAM. The CAM engine (100) thus allows for the benefits of both RAM and CAM devices, such as speed, density, cost and intuitiveness, without their inherent drawbacks. Further, the CAM engine (100) implements various flexible memory storage configurations for the keys and associations stored in RAM. Also, the CAM engine (100) implements certain algorithms that provide for the hashing of data, for table load and unload capabilities, for proximity matching, for dealing with overflow conditions, and for implementing hierarchical search capabilities.

Claims (14)

1. A memory controller adapted to interface with a plurality of normally location-addressed randomly-accessible memory cells, the memory controller comprising an integrated circuit having:
receiving means for receiving a plurality of command signals indicative of data storage and retrieval operations of the memory controller; and signal processing means responsive to the plurality of command signals, for partitioning the plurality of memory cells into at least one table having a first record capacity;
for storing data in certain ones of the plurality of memory cells of the at least one table, the data stored including a plurality of keys and a plurality of associations, wherein said storing comprises:
computing a hash value for each of the data stored; and ordering the table according to the hash values; and said signal processing means further for retrieving data stored in the certain ones of the plurality of memory cells.
2. The memory controller of Claim 1, wherein the signal processing means further comprises means for partitioning the plurality of memory cells into a second table having a second record capacity, wherein the first and second record capacities differ.
3. The memory controller of Claim 2, wherein each key is related to one of the plurality of associations.
4. The memory controller of Claim 3, wherein each one of the plurality of keys has a width comprising a number of data bits and wherein the width of the keys in the first table differs from the width of the keys in the second table.
5. The memory controller of Claim 3, wherein each one of the plurality of associations has a width comprising a number of data bits and wherein the width of the associations in the first table differs from the width of the associations in the second table.
6. The memory controller of Claim 2, wherein the signal processing means further comprises means for arranging at least two of the plurality of tables into a hierarchical relationship comprising a parent table and a child table.
7. A memory controller adapted to interface with a plurality of normally location-addressed randomly-accessible memory cells, the memory controller comprising:
receiving means for receiving a plurality of command signals indicative of data storage and retrieval operations of the memory controller; and signal processing means responsive to the command signal:
for partitioning the plurality of memory cells into at least two tables;
for storing data in certain ones of the plurality of memory cells of the tables, the data stored including a plurality of keys and a plurality of associations, wherein each key has a width and is related to one of the plurality of associations;
for arranging at least two of the plurality of tables into a hierarchical relationship comprising a parent table and a child table; and for retrieving data by searching the parent table for the desired key and if that key is not found in the parent table then searching the child table for the desired key, wherein if the width of the key searched for in the parent table is less than the width of the key searched for in the child table then the key searched for in the child table is masked to the number of data bits comprising the key stored in the child table.
8. The memory controller of Claim 2, wherein the signal processing means further comprises means for creating an overflow table when the signal processing means exceeds the record capacity of one of the tables as the signal processing means is storing data in the table.
9. The memory controller of Claim 1, wherein the signal processing means further comprises means for seeking an exact match between a key presented to the signal processing means and a key stored in certain ones of the plurality of memory cells.
10. The memory controller of Claim 1, wherein the signal processing means further comprises means for seeking the closest approximate match between a key presented to the signal processing means and a key stored in certain ones of the plurality of memory cells.
11. The memory controller of Claim 10, wherein the means for seeking the closest approximate match uses a Manhattan distance formula.
12. The memory controller of Claim 10, wherein the means for seeking the closest approximate match uses a Euclidian distance formula.
13. The memory controller of Claim 1, wherein the signal processing means further comprises means for storing a linking pointer in certain ones of the plurality of memory cells of the at least one table, wherein the linking pointer is indicative of the certain ones of the plurality of memory cells of the at least one table where the association is stored.
14. The memory controller of Claim 1, wherein the signal processing means further comprises means for storing the plurality of keys in a first bank comprising certain ones of the plurality of memory cells of the at least one table and for storing the plurality of associations in a second bank comprising certain ones of the plurality of memory cells of the at least one table.

17. A content addressable memory device comprising:
a memory controller comprising an integrated circuit having:
receiving means for receiving a plurality of command signals indicative of data storage and retrieval operations of the memory controller;
and signal processing means responsive to the plurality of command signals:

for partitioning the plurality of memory cells into at least one table having a first record capacity;
for storing data in certain ones of the plurality of memory cells of the at least one table, the data stored including a plurality of keys and a plurality of associations, wherein said storing comprises computing a hash value for each of the data stored and ordering the table according to the hash values; and for retrieving data stored in the certain ones of the plurality of memory cells; and a plurality of normally location-addressed randomly-accessible memory cells.
18. The memory controller of Claim 1, wherein the signal processing means further comprises means for unloading to a storage device a portion of the data stored in certain ones of the plurality of memory cells of the at least one table.

19. The memory controller of Claim 18, wherein the signal processing means further comprises means for loading data unloaded to the storage device into certain ones of the plurality of memory cells of the at least one table.

21. The memory controller of Claim 7, wherein the signal processing means further comprises means for seeking an exact match between a key presented to the signal processing means and a key stored in certain ones of the plurality of memory cells.

22. The memory controller of Claim 7, wherein the signal processing means further comprises means for seeking the closest approximate match between a key presented to the signal processing means and a key stored in certain ones of the plurality of memory cells.

23. The memory controller of Claim 17, wherein the signal processing means further comprises means for seeking an exact match between a key presented to the signal processing means and a key stored in certain ones of the plurality of memory cells.

24. The memory controller of Claim 17, wherein the signal processing means further comprises means for seeking the closest approximate match between a key presented to the signal processing means and a key stored in certain ones of the plurality of memory cells.

25. A method of storing a plurality of data records in a memory structure, wherein each data record has a key and a related association, the method comprising:
configuring a content addressable memory table in a random access memory device, wherein the content addressable memory table comprises storage for the plurality of keys and associations, and wherein the configuring comprises partitioning the content addressable memory table into a plurality of table records each having a table key;
initializing the content addressable memory table, the initializing comprising:
storing a first initialization value in the table key of the first table record; and storing a second initialization value in the table keys of all subsequent table records;
adding a plurality of data records to the content addressable memory table such that the data records are maintained in order according to hash values of the keys of the data records, the adding comprising:
calculating a hash value by applying a hash algorithm to the key of the data record to be stored; and if the table key at the location in the content addressable memory table which corresponds to the hash value contains the second initialization value, writing the data record into that location;
otherwise:
calculating a re-hash value by applying a hash algorithm to the key of the stored record at the location in the content addressable memory table which corresponds to the hash value;
comparing the re-hash value with the hash value; and if the re-hash value is greater than the hash value, pushing down any stored records between the next sequential table record with the second mitialization value in its table key and the stored record with a table key which would hash to a value greater than the hash value, wherein said pushing down continues until said next sequential table record with the second initialization value in the table key is overwritten; and writing the data record into the table record at the location opened by pushing down the stored records;
otherwise:
reading the next sequential table record;
repeating the calculating a re-hash value, comparing the re-hash value, and pushing down the stored records until the re-hash value is less than or equal to the hash; and writing the data record into the table record at the location opened by pushing down the stored records.
26. The method of claim 25, comprising calculating the re-hash value, comparing the re-hash value with the hash value, and reading the next sequential table record, in parallel.

27. The method of claim 25, further comprising retrieving a data record from the memory structure, the retrieving comprising:
calculating a presented hash value by applying a hash algorithm to a presented key;
reading, in address sequence, the keys stored in the content addressable memory table beginning at the address location which corresponds to the presented hash value;
checking for an exact match between the presented key and the stored key after each stored key is read; and continuing said reading and said checking until either the presented key matches the stored key, all address locations which correspond to the presented hash value have been read, or a table record with the second initialization value in the table key has been read.

28. The method of claim 27, comprising reading, checking for an exact match, determining whether all address locations which correspond to the presented hash value have been read, and determining whether a table record with the second initialization value in the table key has been read, in parallel.

29. The method of claim 25, further comprising retrieving a data record from the memory structure, the retrieving comprising:
reading, in address sequence, each key stored in the content addressable memory table;
comparing a presented key with the key stored in the content addressable memory table after each stored key is read, wherein said comparing includes applying a distance formula to the presented key and the stored key in order to determine the closest approximate match to a presented key; and returning the association corresponding to the stored key which is the closest approximate match to the presented key.

30. The method of claim 27, further comprising deleting a data record from the memory structure, the deleting comprising shuffling up all appropriate table keys until the stored key is overwritten if the presented key matches the stored key.

31. A memory controller comprising an integrated circuit including a means for storing a plurality of data records in a memory structure, wherein each data record has a key and a related association, the means for storing comprising:
means for configuring a content addressable memory table in a random access memory device, wherein the content addressable memory table comprises storage for the plurality of keys and associations, and the configuring comprises partitioning the content addressable memory table into a plurality of table records, each having a table key;
means for initializing the content addressable memory table, wherein the initializing comprises:

storing a first initialization value in the table key of the first table record; and storing a second initialization value in the table keys of all subsequent table records;
means for adding a plurality of data records to the content addressable memory table such that the data records are maintained in order according to hash values of the keys of the data records, wherein the adding comprises:
calculating a hash value by applying a hash algorithm to the key of the data record to be stored; and if the table key at the location in the content addressable memory table which corresponds to the hash value contains the second initialization value, writing the data record into that location;
otherwise:
calculating a re-hash value by applying a hash algorithm to the key of the stored record at the location in the content addressable memory table which corresponds to the hash value;
comparing the re-hash value with the hash value; and if the re-hash value is greater than the hash value, pushing down any stored records between the next sequential table record with the second initialization value in its table key and the stored record with a table key which would hash to a value greater than the hash value, wherein said pushing down continues until said next sequential table record with the second initialization value in the table key is overwritten, and writing the data record into the table record at the location opened by pushing down the stored records, otherwise:
reading the next sequential table record;
repeating the calculating a re-hash value, comparing the re-hash value, and pushing down the stored records until the re-hash value is less than or equal to the hash; and writing the data record into the table record at the location opened by pushing down the stored records.

32. The memory controller of claim 31, further comprising means for retrieving a data record from the memory structure, wherein the means for retrieving comprises:
means for calculating a presented hash value by applying a hash algorithm to a presented key;
means for reading, in address sequence, the keys stored in the content addressable memory table beginning at the address location which corresponds to the presented hash value;
means for checking for an exact match between the presented key and the stored key after each stored key is read; and means for continuing said reading and said checking until either the presented key matches the stored key, all address locations which correspond to the presented hash value have been read, or a table record with the second initialization value in the table key has been read.
33. The memory controller of claim 31, further comprising means for retrieving a data record from the memory structure, wherein the retrieving comprises:
means for reading, in address sequence, each key stored in the content addressable memory table;
means for comparing a presented key with the key stored in the content addressable memory table after each stored key is read, wherein said comparing includes applying a distance formula to the presented key and the stored key in order to determine the closest approximate match to a presented key; and means for returning the association corresponding to the stored key which is the closest approximate match to the presented key.

34. The memory controller of claim 32, further comprising means for deleting a data record from the memory structure, wherein the means for deleting comprises shuffling up all appropriate table keys until the stored key is overwritten if the presented key matches the stored key.

35. A method of storing a plurality of data records in a memory structure, wherein each data record has a key, the method comprising:
configuring a table in a random access memory device, wherein the table comprises storage for the plurality of keys, and wherein the configuring comprising partitioning the table into a plurality of table records each having a table key;
storing an initialization value in the table keys of a plurality of table records;
adding a plurality of data records to the table such that the data records are maintained in order according to hash values of the keys, the adding comprising:
calculating a hash value by applying a hash algorithm to the key of the data record to be stored; and writing the data record into that location if the table key at the location in the content addressable memory table which corresponds to the hash value contains the initialization value.

36. The method of claim 35, further comprising retrieving a data record from the memory structure, the retrieving comprising:
calculating a presented hash value by applying a hash algorithm to a presented key;
reading, in address sequence, the keys stored in the table beginning at the address location which corresponds to the presented hash value;
checking for an exact match between the presented key and the stored key after each stored key is read; and continuing said reading and said checking until either the presented key matches the stored key, all address locations which correspond to the presented hash value have been read, or a table record with the initialization value in the table key has been read.

37. The method of claim 36, comprising reading, checking for an exact match, determining whether all address locations which correspond to the presented hash value have been read, and determining whether a table record with the initialization value in the table key has been read, in parallel.

38. The method of claim 35, further comprising retrieving a data record from the memory structure, the retrieving comprising:
reading, in address sequence, each key stored in the table;
comparing a presented key with the key stored in the table after each stored key is read, wherein said comparing includes applying a distance formula to the presented key and the stored key in order to determine the closest approximate match to a presented key; and returning an association corresponding to the stored key which is the closest approximate match to the presented key.

39. The method of claim 36, further comprising deleting a data record from the memory structure, the deleting comprising shuffling up all appropriate table keys until the stored key is overwritten if the presented key matches the storey key.
CA002309820A 1997-11-14 1998-11-13 Content addressable memory (cam) engine Expired - Fee Related CA2309820C (en)

Applications Claiming Priority (3)

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US08/970,718 1997-11-14
US08/970,718 US6226710B1 (en) 1997-11-14 1997-11-14 Content addressable memory (CAM) engine
PCT/US1998/024288 WO1999026139A1 (en) 1997-11-14 1998-11-13 Content addressable memory (cam) engine

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CA2309820A1 true CA2309820A1 (en) 1999-05-27
CA2309820C CA2309820C (en) 2010-01-12

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EP (1) EP1029277A4 (en)
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WO (1) WO1999026139A1 (en)

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