CA2319938C - Graphic accellerator reducing and processing graphics data - Google Patents

Graphic accellerator reducing and processing graphics data Download PDF

Info

Publication number
CA2319938C
CA2319938C CA002319938A CA2319938A CA2319938C CA 2319938 C CA2319938 C CA 2319938C CA 002319938 A CA002319938 A CA 002319938A CA 2319938 A CA2319938 A CA 2319938A CA 2319938 C CA2319938 C CA 2319938C
Authority
CA
Canada
Prior art keywords
color difference
data
difference component
pixel information
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002319938A
Other languages
French (fr)
Other versions
CA2319938A1 (en
Inventor
Yoshifumi Azekawa
Osamu Chiba
Shohei Moriwaki
Kazuhiro Shimakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Design Corp
Mitsubishi Electric Corp
Original Assignee
Renesas Design Corp
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Design Corp, Mitsubishi Electric Corp filed Critical Renesas Design Corp
Publication of CA2319938A1 publication Critical patent/CA2319938A1/en
Application granted granted Critical
Publication of CA2319938C publication Critical patent/CA2319938C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T17/00Three dimensional [3D] modelling, e.g. data description of 3D objects
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00Aspects of display data processing
    • G09G2340/02Handling of images in compressed format, e.g. JPEG, MPEG

Abstract

A graphic accelerator includes a RGB/YUV conversion unit converting color information of the RGB format included in a drawing instruction into a format which includes luminance and color difference components, a drawing instruction execution unit for compressing the color difference component converted by the RGB/YUV conversion unit to generate pixel information according to the drawing instruction, a screen data output unit expanding pixel information generated by the drawing instruction execution unit, and a YUV/RGB conversion unit which converts the pixel information expanded by the screen data output unit into pixel information of the RGB format. Therefore, the data amounts of the color difference component can be reduced to improve the processing speed.

Description

TITLE OF THE INVENTION
Graphic Accelerator Reducing and Processing Graphics Data BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a graphic accelerator that carries out image display processing. More particularly, the present invention relates to a graphic accelerator that improves processing speed by reducing graphics data, and a drawing method thereof.
Description of the Background Art A graphic accelerator is a dedicated LSI (Large Scale Integrated Circuit) which executes the drawing process of images at high speed is employed in personal computers, video game machines and the like in order to output a fine image of visual realism.
Figure 1 is a block diagram of a typical computer or video game's graphics apparatus including a conventional graphic accelerator. This graphics apparatus includes a CPU (Central Processing Unit) 101 controlling the entire apparatus, a main memory 102, a graphic accelerator 103, a control circuit 104 controlling generation of a timing signal and data input/output with respect to main memory 102 and graphic accelerator 103, an image memory 105 used in processing graphics data, and a CRT (Cathode Ray Tube) 106 where an image is displayed.
Graphic accelerator 103 includes a drawing instruction execution unit 107 for processing the input drawing instruction and converting parameters into graphics data with pixels forming 2 0 the screen as the basic unit, an image memory control unit 108 for writing drawing images with pixels as the basic unit from drawing instruction execution unit 107 into image memory 105 and reading out graphics data from image memory 105, a screen data output unit 109 for converting graphics data read out from image memory 105 into data of the display format of CRT 106, and a DAC (Digital/Analog Converter) 110 converting digital signals output from screen data output 2 5 unit 109 into analog signals. The processing contents carried out by drawing instruction execution unit 107 and screen data output unit 109 are well known in the field of art. Therefore, a detailed description thereof will not be provided.
In the graphics apparatus of Figure 1, the data transfer speed of an image memory interface bus 1 I 1 between the image memory control unit 108 in graphic accelerator 103 and 3 0 image memory 105 often becomes a bottleneck in determining the drawing processing performance. This is because the data transfer speed between graphic accelerator 103 and image memory 105 is significantly low with respect to the processing speed of graphic accelerator 103, since graphic accelerator 103 and image memory 105 are formed of separate semiconductor components.
As a method of improving the data transfer speed between graphic accelerator 103 and image memory 105, the method of increasing the bus width of the image memory interface bus 111, and the method of improving the data transfer frequency of image memory 105 are known.
However, the method of increasing the bus width of image memory interface bus 111 induces the problem of increasing the area of the circuit substrate where graphic accelerator 103 is mounted, thus increasing the circuit complexity due to bus width expansion, and increasing the area for mounting image memory 105, and the like. The method of improving the data transfer frequency of image memory 105 is disadvantageous in that an image memory having a large capacity and a short access time is not available at low cost. Thus, there was a problem that it is difficult to provide a graphic accelerator with improved processing speed without increasing the cost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a graphic accelerator that can improve the processing speed of graphics processing.
Another obj ect of the present invention is to provide a graphic accelerator that can reduce the capacity of the image memory used in processing graphic data.
A further object of the present invention is to provide a graphic accelerator that can 2 0 reduce the circuit scale of the arithmetic unit and the like.
Still another object of the present invention is to provide a drawing method that can improve the speed of drawing processing.
A still further object of the present invention is to provide a drawing method that can reduce the capacity of the image memory used in processing graphics data.
2 5 Yet a further object of the present invention is to provide a drawing method that can reduce the circuit size of the arithmetic unit and the like.
According to an aspect of the present invention, a graphic accelerator includes a first conversion unit converting pixel information represented by the colorimetric system using stimulus values of the three primary colors such as the RGB format into pixel information of a 3 o format including a luminance component and a color difference component, a data compression unit compressing the color difference component of the pixel information converted by the first conversion unit, a drawing unit for interpreting a drawing instruction to generate graphics data according to the luminace component converted by the first conversion unit and the color difference component compressed by the data compression unit, a data expansion unit expanding the graphics data generated by the drawing unit, and a second conversion unit converting the graphics data expanded by the data expansion unit into graphics data represented by the aforementioned colorimetric system, wherein said data compression unit compresses data by sharing color difference components of pixels of the same coordinate in a plurality of frames.
Since the drawing unit generates graphics data according to the luminance component converted by the first conversion unit and the color difference component compressed by the data compression unit, the data transfer amount of the graphics data can be reduced to improve the 3 0 processing speed. Also, the capacity of the image memory storing graphics data can be reduced, since the amount of graphics data is reduced.
According to another aspect of the present invention, a drawing method includes the steps of converting pixel information represented by the colorimetric system using stimulus values of the three primary colors such as the RGB format into pixel information of a format including a luminance component and a color difference component, compressing the color difference component of the converted pixel information, interpreting a drawing instruction to generate graphics data according to the converted luminance component and the compressed color difference component, expanding the generated graphics data, and converting the expanded graphics data into graphics data represented by the aforementioned colorimetric system,wherein 2 0 said step of compressing the color difference component of said converted pixel information includes the step of compressing data by sharing the color difference components ofpixels of the same coordinate in a plurality of frames.
Since graphics data is generated according to the converted luminance component and the compressed color difference component, the data transfer amount of graphics data can be 2 5 reduced to improve the processing speed. Since the amount of graphics data is reduced, the capacity of the image memory storing graphics data can be reduced.
The foregoing and other obj ects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram showing a schematic structure of a graphics apparatus including a conventional graphic accelerator.
Figure 2 is a block diagram showing a schematic structure of a graphics apparatus including a graphic accelerator according to a first embodiment of the present invention.
Figure 3 is a block diagram to describe in further detail a drawing instruction execution 3a unit 11 in the graphic accelerator of Figure 2.
Figure 4A-4C are diagrams to describe the pixel information generation process by a graphics data generation unit 22 and a data compression method by a data compression unit 23.
Figure S is a diagram to describe in further detail the screen data output unit in the graphic accelerator of Figure 2.
Figure 6 is a diagram to describe the process of a data compression unit 23 a in the graphic accelerator according to a second embodiment of the present invention.
Figure 7 is a diagram to describe a pmcess of a data compression unit 23c in a graphic accelerator according to a fourth embodiment of the present invention.
Figure 8 is a block diagram showing a schematic structure of a graphics apparatus including a graphic accelerator according to a sixth embodiment of the present invention.
Figure 9 is a diagram to describe in further detail a drawing instruction execution unit 11 a and a RGB/YLTV conversion unit 10e of Figure 8.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
First Embodiment Referring to Figure 2, the apparatus with a graphic accelerator of the first embodiment includes a CPU 1 providing the overall control of the apparatus, a ROM (Read Only Memory) 2 storing the basic program of the apparatus, a RAM (Random Access Memory) 3 storing the 2 0 process data and program by CPU 1, a CD-ROM (Compact Disc-Read Only Memory) 4 storing a program, a CD-ROM device 5 reading CD-ROM 4, a hard disc device 6, a graphic accelerator 7, an image memory 8 used in processing graphics data, and a CRT 9 where an image is displayed.
Graphic accelerator 7 includes a RGB/YLJV conversion unit 10 converting color 2 5 information of the RGB format included in the drawing instruction into data of the YUV format, a drawing instruction execution unit 11 processing the drawing instruction including color information of the YUV format into pixel information and compressing the pixel information, an image memory control unit 12 writing into image memory 8 the pixel information generated by drawing instruction execution unit 11 and reading out pixel information from image memory 3 0 8, a screen data output unit 13 converting the pixel information read out from image memory 8 into display data of CTR 9, a YLJV/RGB conversion unit 14 converting display data of the YI1V
format into display data of the RGB format, and a DAC 15 converting the display data of the RGB digital format output from YUV/RGB conversion unit 14 into analog signals.
RGB/YW conversion unit 10 receives in the RGB format the color information included in the drawing instruction that is the object of the drawing processing via CPU 1 and converts the color information into the YUV format. This conversion process is carried out according to the following equations (1)-(3).
Y = 0.2998 + 0.5876 + 0.114B
_ (1/4+1/32+1/64)8 +(1/2+1/16+1/32)6 + (1/16+1/32+1/64)B ... (1) V=Cb - -0.16878 - 0.33136 + O.SOOB
- -(1/8+1/32+1/64)8 - (1/4+1/16+1/64)6 + 1/2B + 128 ... (2) U=Cr = O.SOOR - 0.41876 + 0.0813B
= 1/28 - (1/4+1/8+1/32+1/64)6 + (1/16+1/64)B + 128 ... (3) In the present embodiment, color information of the RGB format is converted into color information of the YUV format. However, the present invention provides similar advantages even if the color information is converted into another format constituted by a luminance component signal and a color difference component signal.
2 0 Figure 3 is a block diagram to describe in further detail drawing instruction execution unit 11 in graphic accelerator 7 of Figure 2. Drawing instruction execution unit 11 includes an instruction decoder 21 for interpreting the drawing instruction from CPU 1 via RGB/YUV
conversion unit 10, a graphics data generation unit 22 which converts parameters into pixel information of the YUV format according to the interpreted result from instruction decoder 21, 2 5 and a data compression unit 23 which compresses data by removing UV
information which is the color difference component from the pixel information of the YUV format generated by graphics data generation unit 22.
Here, the drawing instruction executed by drawing instruction execution unit 11 includes a straight line drawing instruction, a rectangle drawing instruction, a clear instruction, a filling 3 o instruction and a text drawing instruction for a two-dimensional image, and also polygon vertex coordinate data, texture coordinate data, blending color information for texture, transparency information, depth information value and the like for a three-dimensional image. Tnstruction decoder 21 decodes the received drawing instruction from CPU 1 to determine which of these instructions the current drawing instruction is.
Figures 4A-4C are diagrams to describe the pixel information generation process by graphics data generation unit 22 and the data compression method by data compression unit 23.
Graphics data generation unit 22 generates control data of the pixel information, forming a screen according to the interpreted result of the drawing instruction by instruction decoder 21. Here, pixel information refers to pixel color information determined by the combination of the three colors of RGB in the conventional art, which is represented by the YUV format in the present 1 o embodiment.
As a specific process by graphics data generation unit 22, pixels arranged as shown in Figure 4A are subjected to the filling instruction to result in the image of pixel information shown in Figure 4B. Control data of the pixel information indicated by the coordinates [0,0], [ 1,0], [0,1 ]. [ 1,1 ] are generated. Similarly, control data are also generated for pixels having the pixel information determined by the filling instruction (not shown).
Next, the data compression process by data compression unit 23 will be described. In general, human vision is sensitive to the change in luminance component Y and rather insensitive to the change in the color difference components U and V. Pixel information of the YUV format is compressed taking advantage of this feature in human vision.
2 0 Specifically, with regard to the control data of the pixel information generated by graphics data generation unit 22, the pixel information of four adjacent pixels [0,0], [1,0], [0,1], [1,1] are to be compressed. Since human vision is rather insensitive to the change in color difference components U and V, color difference components U~o,o~ and V~o,o~ of pixel [0,0] out of the four pixels are employed as the representative values of the color difference component, and other 2 5 color difference component information are deleted. Therefore, the pixel information of the four pixels is reduced to the luminance components of Y~o,o~, Y~,.o~, Yio.y and Y~m~, and the color difference components of U~o,o~ and V~o,o~.
Although color difference components U~o,o~ and V~o,o~ of pixel [0,0] are used as the representative values of the color difference components according to the above description, the 3 o color difference component value of another pixel can be used as the representative value of the color difference component. Alternatively, an average of the color difference component values of a plurality of pixels, for example the average of color difference components U~o,o~, U~,,o~, U~o,n and U~,,1~ and the average of color difference components V~o,o~, V~,,o~, V~o,,~, and V~~,,~ of four pixels, can be used as the representative values of the color difference components.
Regarding the data compression method , equal advantages can be obtained even by using the compression method of 4:2:2 or 4:2:0 and the like defined in ITU
(International Telecommunication Union) Recommendation 601. Also, although the pixel information of four adjacent pixels are compressed in the above description, the compression efficiency can be further improved by compressing more pixels according to a similar manner.
By virtue of compressing the control data of the pixel information in drawing instruction execution unit 11 and writing the data into image memory 8, the required memory capacity of 1 o image memory 8 can be reduced. Also, the amount of data transfer per unit time along the bus between graphic accelerator 7 and image memory 8 can be reduced. Therefore, the bottleneck caused by the data transfer speed of this bus can be eliminated.
Image memory control unit 12 sequentially writes the pixel information into image memory 8 according to the control data of the pixel information generated by drawing instruction execution unit 1. Image memory control unit 12 also reads out pixel information from image memory 8 at a predetermined timing for output to screen data output unit 13.
In the case where image memory 8 is a D-RAM (Dynamic-Random Access Memory), image memory control unit 12 refreshes image memory 8 at a predetermined timing.
Figure 5 is a block diagram to describe in further detail screen data output unit 13 of 2 o graphic accelerator 7 shown in Figure 2. Screen data output unit 13 includes a data expansion unit 31 expanding pixel information input via image memory control unit 12.
Data expansion unit 31 expands the compressed pixel information of the YUV
format and generates graphics data corresponding to each display pixel. For example, when four adjacent pixels are compressed as shown in Figure 4C, expansion is effected by assigning U~o,o~ and V~o,o~
2 5 to the color difference component information of pixels [0,1 ], [ 1,0] and [ 1,1 ].
YUV/RGB conversion unit 14 converts the graphics data ofthe YUV format output from screen data output unit 13 into graphics data of the RGB format. This conversion is carried out according to the following equations.
30 R=Y+ 1.403Cr = Y + (1 + 1/4 + 1/8 + 1/32)(Cr - 128) ... (4) G = Y - 0.714Cr-0.344Cb = Y - (1/4 + 1/16 + 1/32)(Cr - 128) - (1/2 + 1/8 + 1/16 + 1/32)(Cb - 128) ...
(5) B = Y + 1.773Cb = y + (1 + 1/2 +1/4 +1/64)(Cb - 128) ... (6) DAC 15 converts digital signals which are the graphics data of the RGB format converted by YUV/RGB conversion unit 14 into analog signals and provides the analog signals to CRT 9.
CRT 9 provides display according to the analog signals.
According to the graphic accelerator of the present embodiment, the recording format of the pixel data in image memory 8 is converted into the YUV format from the RGB
format, and data is compressed sharing color difference components U and V of adjacent pixels. Therefore, the capacity of image memory 8 can be reduced. Also, the processing speed of drawing instruction execution unit 11, and in turn the processing speed of graphic accelerator 7, can be improved since the number of accesses to image memory 8 by drawing instruction execution unit 11 is reduced in accordance with reduction of the pixel information.
Furthermore, an economic graphics apparatus can be provided since the bus width of image memory interface bus 16 of the graphic accelerator of the present embodiment can be reduced in the case of a data transfer speed identical to that of the conventional graphic accelerator.
Second Embodiment A graphic accelerator according to a second embodiment of the present invention differs from the graphic accelerator of the first embodiment in the function of data compression unit 23 2 0 shown in Figure 3 and data expansion unit 31 shown in Figure 5. Therefore, detailed description of the same structure and function will not be repeated. The data compression unit and the data expansion unit are labelled 23a and 31a, respectively, in the present embodiment.
Since the human vision is insensitive with respect to change in color difference components U and V, data is compressed by reducing the precision of color difference 2 5 components U and V in the present embodiment.
Figure 6 is a diagram to describe the process of data compression unit 23a in the graphic accelerator of the present embodiment. As to luminance components Y~o,o~, Y~o.a~ 1'~i.o~ ~d yo,m the luminance component Y subjected to the conversion to the YUV format is exactly employed without degrading the precision. As to color difference components U~o,o~, U~o,,~, U~l~o~ and U~~,1~, 3 0 only the predetermined higher order bits of color difference component U
subjected to conversion to the YUV format are used and the lower order bits are deleted for data compression.
Similarly, as to color difference components V~o,o~, V~o,,~, V~,,o~ and V~,,,~, only predetermined higher order bits of color difference component V subjected to conversion to the YUV format are used and the lower order bits are removed for data compression.
Data expansion unit 31 a sets predetermined data to the deleted lower order bits of color difference components U~o,o~, U~o,,~, U~~,o~ and U~,,,~, to expand data. For example, "0" is set for all the bits of the lower order bits for data expansion. Although data is compressed by deleting the lower order bits of the color difference component in data compression, the number of bits to be deleted can be appropriately set by an external register. The graphics apparatus can realize a display corresponding to the usage status by altering the number of bits to be deleted depending upon the resolution and number of colors of CRT 9.
According to the graphic accelerator of the present embodiment, data compression is carried out by deleting only the lower order bits of the color difference component. Therefore, the graphic accelerator can be implemented by a further simple structure in comparison to that of the graphic accelerator of the first embodiment.
Third Embodiment A graphic accelerator according to a third embodiment of the present invention differs from the graphic accelerator of the first embodiment in the function of data compression unit 23 shown in Figure 3 and data expansion unit 31 shown in Figure 5. Therefore, details of the same structure and function will not be repeated. The data compression unit and the data expansion unit are labelled 23b and 31b, respectively, in the present embodiment.
2 0 Data compression unit 23b of the present embodiment has the data compression method of the second embodiment of Figure 6 added to the data compression method of the first embodiment shown in Figure 4. More specifically, only color difference components U~o,o~ and V~o,o~ of pixel [0,0] which are representative values are left, and the color difference component information of the other pixels are removed from the color difference components U and V of 2 5 four adjacent pixels. Then, the lower order bits of color difference components U~o,o~ and V~o,o~
of pixel [0,0] are deleted for data compression.
Data expansion unit 31b assigns U~o,o~ and V~o,o~ to the color difference component information of pixels [0,1 ], [ 1,0] and [ 1,1 ]. Then, predetermined data is set to the lower order bits of each color difference component information to expand data.
3 0 According to the graphic accelerator of the present embodiment, data is compressed by sharing the color difference components of adjacent pixels and deleting the lower order bits of color difference component data for data compression. Therefore, the amount of data can be reduced by data compression in comparison to the graphic accelerator of the first and second embodiments.
Fourth Embodiment A graphic accelerator according to a fourth embodiment of the present embodiment differs from the graphic accelerator of the first embodiment in the function of data compression unit 23 shown in Figure 3 and data expansion unit 31 shown in Figure 5.
Therefore, details of the same structure and function will not be repeated. The data compression unit and the data expansion unit are labelled 23c and 31c, respectively, in the present embodiment.
Since human vision is insensitive with respect to change in color difference components U and V, data is compressed by sharing color difference components U and V
between frames in the present embodiment.
Figure 7 is a diagram to describe the process of a data compression unit 23c in the graphic accelerator of the present embodiment. As shown in Figure 7, the drawing process is carried out by sequentially writing the data of the frame into image memory 8. These frames are grouped for every several frames. The color difference component information of pixel information of the same coordinate are shared in this group of the plurality of frames.
In the drawing process of frame 17 shown in Figure 7, data compression unit 23c does not compress the pixel information converted into the YLJV format. Graphics data generation unit 22 carries out the drawing process using pixel information that is not compressed. As to the 2 0 frames included in frame group #1, data compression unit 23c deletes all the color difference component information in the drawing process of frames 17-A,17-B and 17-C.
Then, graphics data generation unit 22 processes only the luminance component information to generate graphics data. Image memory control unit 12 writes the luminance component information into the region of image memory 8 where the luminance component information is to be recorded.
As to frame 2 5 group # l, the luminance component information and color difference component information are manipulated only in the first frame 17 and written into image memory 8. For subsequent frames 17-A, 17-B and I7-C in frame group #l, only the luminance component information is manipulated and written into image memory 8. Therefore, the processing speed of drawing instruction execution unit 11 can be improved and the capacity of image memory 8 can be 3 o reduced.
In the present embodiment, four frames are taken as one group. By increasing the number of frames of which the color difference component information is shared, the processing speed of drawing instruction execution unit 11 can be further improved, and the capacity of image memory 8 can be further reduced. However, it is to be noted that the picture quality will be degraded by increasing the number of frames that share the color difference component information. The number of frames sharing the color difference component information can be set appropriately by an external-operable register.
According to the graphic accelerator of the present embodiment, a plurality of frames are taken as one group, and color difference component information shared by the plurality of frames. Therefore, the processing speed of drawing instruction execution unit 11 can be improved and the capacity of image memory 8 reduced without significantly degrading the picture quality of the image.
Fifth Embodiment A graphic accelerator according to a fifth embodiment of the present invention differs from the graphic accelerator of the first embodiment in the function of drawing instruction execution unit 11 and RGB/YUV conversion unit 10 of Figure 2. Therefore, a detailed description of the same structure and function will not be repeated. The drawing instruction execution unit, the RGB/YUV conversion unit, instruction decoder, graphics data generation unit and data compression unit are labelled 1 1e, 10e, 21e, 22e and 23e, respectively. A color space conversion unit 24 has a structure and function identical to those of the RGB/YUV conversion unit 10 of Figure 2.
2 0 The graphic accelerator of the present embodiment is directed to reduce circuit overhead by providing a RGB/YW conversion unit 10e between instruction decoder 21 a and graphics data generation unit 22e in drawing instruction execution unit 11 e, according to the structure of the graphic accelerator of the first embodiment of Figure 2, as shown in Figures 8 and 9.
More specifically, in the first embodiment, following the conversion of the drawing 2 5 instruction input from CPU 1 into pixel data of the RGB format by instruction decoder 21 and graphics data generation unit 22, the data is converted into pixel data of the YUV format by RGB/YUV conversion unit 10 and the color information is reduced by data compression unit 23.
However, this method has a disadvantage in that the circuit overhead is great since conversion into pixel data of the RGB format is carried out.
3 0 For the purpose of solving this problem, the present embodiment includes a process of reducing the color information within a range that does not alter the visual effect by RGB/YUV
conversion unit 1 Oe prior to processing of graphics data in pixel units by graphics data generation unit 22e. Reduction of color information carried out by data compression unit 23e in the present embodiment is implemented by reducing the lower order bits of the color difference component in the previous second embodiment.
According to the graphic accelerator of the present embodiment, color information is reduced prior to processing the drawing instruction into graphics data formed of a plurality of pixels. Therefore, the arithmetic unit and the like can be realized with lower circuit complexity than that of the graphic accelerator of the first embodiment.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims (8)

1. A graphic accelerator comprising:
a first conversion unit converting pixel information represented by a colorimetric system using stimulus values of the three primary colors into pixel information of a format including a luminance component and a color difference component;
a data compression unit compressing the color difference component of the pixel information converted by said first conversion unit;
a drawing unit for interpreting a drawing instruction to generate graphics data according to the luminance component converted by the first conversion unit and the color difference component compressed by said data compression unit;
a data expansion unit expanding graphics data generated by said drawing unit;
and a second conversion unit converting the graphics data expanded by said data expansion unit into graphics data represented by said colorimetric system, wherein said data compression unit compresses data by sharing color difference components of pixels of the same coordinate in a plurality of frames.
2. The graphic accelerator according to claim 1, wherein said data compression unit compresses data by determining a representative value of the color difference component according to pixel information of adjacent pixels, and deleting the color difference component other than the representative value.
3. The graphic accelerator according to claim 1, wherein said data compression unit compresses data by deleting a lower order bit of the color difference component.
4. The graphic accelerator according to claim 1, wherein said data compression unit compresses data by determining a representative value of the color difference component according to pixel information of adjacent pixels, deleting the color difference component other than the representative value, and deleting a lower order bit of said representative value of the color difference component.
5. A drawing method comprising the steps of:

converting pixel information represented by a colorimetric system using stimulus values of the three primary colors into pixel information of a format including a luminance component and a color difference component;

compressing the color difference component of said converted pixel information;
interpreting a drawing instruction to generate graphics data according to said converted luminance component and said compressed color difference component;
expanding said generated graphics data; and converting said expanded graphics data into graphics data represented by said colorimetric system, wherein said step of compressing the color difference component of said converted pixel information includes the step of compressing data by sharing the color difference components of pixels of the same coordinate in a plurality of frames.
6. The drawing method according to claim 5, wherein said step of compressing the color difference component of said converted pixel information comprises the step of compressing data by determining a representative value of the color difference component according to pixel information of adjacent pixels, and deleting the color difference component other than the representative value.
7. The drawing method according to claim 5, wherein said step of compressing the color difference component of said converted pixel information comprises the step of compressing data by deleting a lower order bit of the color difference component.
8. The drawing method according to claim 5, wherein said step of compressing the color difference component of said converted pixel information comprises the step of compressing data by determining a representative value of the color difference component according to pixel information of adjacent pixels, deleting the color difference component other than the representative value, and deleting the lower order bit of the representative value of said color difference component.
CA002319938A 1999-11-16 2000-09-20 Graphic accellerator reducing and processing graphics data Expired - Fee Related CA2319938C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP32521599 1999-11-16
JP11-325215 1999-11-16
JP2000-151101 2000-05-23
JP2000151101A JP2001209789A (en) 1999-11-16 2000-05-23 Graphic accelerator and plotting method

Publications (2)

Publication Number Publication Date
CA2319938A1 CA2319938A1 (en) 2001-05-16
CA2319938C true CA2319938C (en) 2004-08-03

Family

ID=26571767

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002319938A Expired - Fee Related CA2319938C (en) 1999-11-16 2000-09-20 Graphic accellerator reducing and processing graphics data

Country Status (4)

Country Link
US (1) US6693644B1 (en)
JP (1) JP2001209789A (en)
CA (1) CA2319938C (en)
DE (1) DE10052156A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030031298A (en) * 2001-10-13 2003-04-21 삼성전자주식회사 Method of analyze for digital image
US7916147B2 (en) 2002-03-01 2011-03-29 T5 Labs Ltd. Centralised interactive graphical application server
ITTO20020570A1 (en) * 2002-07-01 2004-01-02 St Microelectronics Srl PROCEDURE AND DEVICE FOR PROCESSING VIDEO SIGNALS FOR DISPLAYING ON A DISPLAY AND RELATED IT PRODUCT.
US20050024380A1 (en) * 2003-07-28 2005-02-03 Lin Lin Method for reducing random access memory of IC in display devices
US8155703B2 (en) * 2004-10-01 2012-04-10 Broadcom Corporation Wireless device having a configurable camera interface to support digital image processing
US7499051B1 (en) 2005-04-29 2009-03-03 Adobe Systems Incorporated GPU assisted 3D compositing
US8203564B2 (en) * 2007-02-16 2012-06-19 Qualcomm Incorporated Efficient 2-D and 3-D graphics processing
US8270773B2 (en) 2008-08-04 2012-09-18 Kabushiki Kaisha Toshiba Image processing apparatus and image processing method
US9679530B2 (en) * 2012-04-30 2017-06-13 Nvidia Corporation Compressing graphics data rendered on a primary computer for transmission to a remote computer
US9679348B2 (en) * 2014-05-15 2017-06-13 Disney Enterprises, Inc. Storage and compression methods for animated images
US11423588B2 (en) 2019-11-05 2022-08-23 Adobe Inc. Color transforms using static shaders compiled at initialization

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2849385B2 (en) 1987-05-29 1999-01-20 株式会社リコー Color image compression encoder
JPH02100465A (en) 1988-10-06 1990-04-12 Sharp Corp Image encoding system
JPH04307894A (en) 1991-04-05 1992-10-30 Matsushita Electric Ind Co Ltd Compression and display system for color picture data and compressing device for color picture data
US5262847A (en) 1992-10-20 1993-11-16 International Business Machines Corporation Method of converting luminance-color difference video signal to a three color component video signal
JP3523719B2 (en) 1995-04-04 2004-04-26 三菱電機株式会社 Image encoding device and image decoding device
JPH08294142A (en) 1995-04-24 1996-11-05 Omron Corp Image information compression method and image display device using this method
US5920322A (en) * 1996-05-22 1999-07-06 Digital Equipment Corporation Method and apparatus for providing 32-bit YUV to RGB color conversion

Also Published As

Publication number Publication date
CA2319938A1 (en) 2001-05-16
US6693644B1 (en) 2004-02-17
JP2001209789A (en) 2001-08-03
DE10052156A1 (en) 2001-05-23

Similar Documents

Publication Publication Date Title
US6825847B1 (en) System and method for real-time compression of pixel colors
US5625379A (en) Video processing apparatus systems and methods
US5896140A (en) Method and apparatus for simultaneously displaying graphics and video data on a computer display
CA2423497C (en) Method and apparatus for the anti-aliasing supersampling
EP1025558B1 (en) A method and apparatus for performing chroma key, transparency and fog operations
JP4234217B2 (en) System, apparatus and method for embedding transparent enable bits as part of resizing bit block transfer processing
IE60736B1 (en) Video display apparatus
JPH03120981A (en) Color television window enlargement and over-scan correction for high resolution raster graphic display
CA2319938C (en) Graphic accellerator reducing and processing graphics data
JP4971442B2 (en) Image processing apparatus and method for pixel data conversion
CN116453455A (en) Pixel multiplexing method, data transmission system and display screen control system and method
CN108694733B (en) MCU-based display system and display method for overlaying dynamic images on background image
JPH11259671A (en) Image displaying method and image display device executing the same
KR20060007054A (en) Method and system for supersampling rasterization of image data
JPH0660173A (en) Method and apparatus for reducing picture
JP3547250B2 (en) Drawing method
JPH07262367A (en) Apparatus and method for processing of digital image signal
KR100472464B1 (en) Apparatus and method for serial scaling
US6747661B1 (en) Graphics data compression method and system
US6720972B2 (en) Method and apparatus for remapping subpixels for a color display
US6509901B1 (en) Image generating apparatus and a method thereof
US6181350B1 (en) Apparatus for, and method of, interpolating between graphics and video pixels in an expanded image
JP2510019B2 (en) Image display method and device
JP2898482B2 (en) Computer game equipment
JP3533197B2 (en) Image processing device

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed