CA2321571C - A differential line driver - Google Patents
A differential line driver Download PDFInfo
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- CA2321571C CA2321571C CA002321571A CA2321571A CA2321571C CA 2321571 C CA2321571 C CA 2321571C CA 002321571 A CA002321571 A CA 002321571A CA 2321571 A CA2321571 A CA 2321571A CA 2321571 C CA2321571 C CA 2321571C
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
Abstract
A fully differential line driver, especially for twisted copper pairs. It comprises two current amplifiers (A p, A n), made in standard CMOS technique, each having an input (I inp, I inn) and an output (I op, I
on), which latter are connected via terminal resistors (R t) to a voltage source, which may be set to a larger voltage than that used for driving the CMOS amplifiers. With this invention, a low output impedance can be combined with a large swing. Further, feedback is not necessary, avoiding problems like potential instability. A preferred embodiment also has a very low-impedance input, making it appropriate for connecting to a DAC, thus reducing distortion of its output signal. The invention is suitable for very-high-speed-digital-subscriber-line modems.
on), which latter are connected via terminal resistors (R t) to a voltage source, which may be set to a larger voltage than that used for driving the CMOS amplifiers. With this invention, a low output impedance can be combined with a large swing. Further, feedback is not necessary, avoiding problems like potential instability. A preferred embodiment also has a very low-impedance input, making it appropriate for connecting to a DAC, thus reducing distortion of its output signal. The invention is suitable for very-high-speed-digital-subscriber-line modems.
Description
A differential line driver BACKGROUND OF THE IKV~TION
The invention regards a CMOS differential line driver, in particular for driving a line comprising a twisted copper pair, and havin' a differential input with two input terminals and a differential analog output with two output terminals, which are each provided with a terminal resistor. It is thouaht primarily for use with twisted copper pairs or the lz'ke as used for high speed applications like high speed internet access.
A traditional type of a fully differential line driver is shown schematically in Fig. 1.
The twisted copper pair 1 is fed with power via a transformer 2. In order to obtain impedance matching, the transformed impedance of the twisted copper pair must be matched by tPm-ination resistors R.
A full description of an embodiment of this prior art is given in the article by Khorramabadi, TEEE J. Solid-State Circuits, Vol. 27 No. 4, (1992) p. 539, which is hereby included by reference into the present disclosure. General problems with line drivers are exposed in Johns and Essig, Integrated Circuits for Data Transmission Over Twisted-Pair Channels, IEEE J. Solid-State Circuits, Vol. 32 No. 3 (1997) p.
398.
This known architecture has several drawbacks. The line driver must have a low output impedance and high common-mode rejection, since very high voltage in the copper wire may be coupled back as common mode signals via paxasitic capacitance. The input-dependent variation in the output impedance of the line driver must also be very small in order to have low distortion. Therefore, effective feedbacks are needed in the line driver. Improper compensation in the line driver may result in low signal bandwidth and/or instability.
To deliver a high power to the Iine driver, a high supply voltage is usually needed.
3 5 A line driver of the envisac-red type would usually be handling signals from a high speed digital-to-analog converter (DAC) for high speed internet access. It is normal for such high speed DACs to be airan~ed as current-output devices, meaning that the driving DAC would have a high output impedance. In order to minimi~e the distortion in the DAC, the input impedance of the line driver must be low.
It is an object of the invention to obtain a fuIlv differential line driver, which obviates the above-mentioned difficulties. Another object is to obtain such a driver which can be made with a standard 5-V CMOS process. This would even enable its integrating with a driving DAC on a single chip. A further object is to obtain very low distortion at high bandwidth without stability problems.
SUMMARY OF THE INVENTION
Said objects and other objects and advantages are obtained, according to the invention, with a line dri.ver of the kind mentioned, and which is provided such (i) that the said input is a current input, (ii) that the driver comprises two current amplifiers (Ap, An), each forming a said input terminal (Ii,Q, Ii,n) and a said output terminal ( LP, Ioõ) respectively, and provided for feeding with a drive voltage (V,) (iii) that said terniinal resistors (R,) are connected with first ends to said output terminals (Lp, LQ) and have second ends connectible to a drive voltage (Vddh).
Typical for the inventive solution is that amplifying circuits are used, which are current amplifying, enabling the obtaining of a low input impedance and a high output impedance. For obtaining high common-mode rejection and impedance matching, termination resistors are arranged.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention shall now be described with reference to the figures, which are to be considered as non-limiting.
Fig. 1, already mentioned, shows a prior-art line driver.
Fig. 2 shows schematically the inventive solution.
Fig. 3 shows an exemplaiy embodiment schematically drawn, and applied for the use of a standard 5-V CMOS manufacturing process.
DETAILED DESCRIPTION OF THE INVENTION
The general concept of the invention may be understood from Fig. 2. A line driver is provided with a pair of current inputs I;'P and I;nA , The line driver (inside the dashed rectana-le) has a pair of current outputs, which are provided with terminal resistors R, connected to drive voltages Vda and connected to a transformer winding, with another winding connected to a twisted copper pair. As is apparent, there is inside the dashed rectang.ie a set of two current amplifiers AP and A. In order to easily interface with a driving DAC, the line driver itself will have a very low input impedance. Unlike the traditional approach shown in Fig. 1, the proposed line driver has a very high output impedance. Having a low input impedance and a hia,h output impedance, this line driver thus is a current-mode line driver.
The ~
termination resistors at the outputs of the line drivers will give high common-mode rejection and impedance matching.
The effective impedance must be equal to the transformed line impedance Z, for D impedance matching. If we assume that the output impedance of the line driver is very large, we have the value of the termination resistor R, given by (1) Rt=2 x ZT= 2xZA2 where ZT is the transformed line impedance, Z, is the line impedance, and n is the turns ratio of the transforrner.
Since the DAC usualiv uses offset binarv codes, the outputs of the DAC, i.e.
the input currents to the Iine driver, can be represented as Iinp = Ios + iarl 2 (2) Iinn = Ias - ia~ / 2 t~ ) where TaS is constant and iar is the analog representation of the digital input sisaal of the DAC. Suppose that the line driver has a gain of A for both positive and negative branches, we have the output currents given by Iop = A X (+os + lac / 2) (4) L. = A X(I,,,, - i.,r / 2) (5) Suppose the output impedance of the line driver is very large, then the ac current flowing into the transfornier is given by . 30 iT = KxAxi.,r (6) where the constant K is determined by the transformed line impedance ZT and the termination resistance Rt, given by K = R, / (2 R~ + ZT ) (7) Notice that the constant current Ios disappears in equation (6). As a matter of fact, any common-mode signals have no influence on the current flowing into the transformer and equation (7) holds independent of any common-mode signals.
In order to obtain impedance matching, equation (1) must be satisfied.
Therefore, we have K=R4 / (2Rt + ZT) =2ZT/(4Zr +ZT)= 0,4 (8) ., -The power delivered to the line is equal to the power delivered to the transformer and is given by Pi =P, =iT'' x ZT = K' x A'"x iac 2 X Zi /n'' _ ' = 0,16 x A2 x i.' x Zi / n' (9) This makes it clear that the line driver can be realized by using current ampiifiers terminated by resistors. Several advantages are won with such a solution.
Current amplifiers have inherently high bandwidth due to low internal impedance, and therefore this approach is suitable for high speed application. Further, no global feedback is necessary in the current ampli.fiers, and the line driver may thus be unconditionally stable in the global sense. Another great advantage with the architecture shown in Fig. 2 is that the supply voltage for the termination resistors can be much higher than the supply voltage for the line driver, in order to accommodate voltage swing at the output. As long as the output voltage swing of the driver is not very large, such that all the transistors within the line driver do not break out, the li.ne driver can be integrated with the DAC in a component made in a standard CMOS
process.
It may be noted that the use of an extra supply voltage for the termination resistors is advantageous in that large common-mode sipals are directed to this extra supply voltage without disturbing the supply voltages for the DAC and current amplifiers.
A disadvantage would be the power efficiency, since some power is wasted on the termination resistors due to the matching requirement.
In the above discussion, it has been assumed that the output impedance of the current amplifiers are infinite. If the output impedance of the current amplifiers changes dependent on the input current, distortion results. In order to ensure low distortion, a very high output impedance is desirable for the current ampli.fiers. This can be ensured by proper design.
Preferred embodiment In Fig. 3 is shown an example for a current amplif er, forming one of the amplifiers Ap within the dashed rectangle in Fig. 2. As the amplifier Aõ may be rigorously similar, only the first-mentioned current amplifier is shown in Fig. 2, with inputs and outputs shown.
In order to have high signal bandwidth, it is preferable to use only NMOS
transistors in the signal path. For obtaining a large gain A, it is preferable to use several stages in cascade in order to maintain the high bandwidth.
The current amplifier consists of two stages, The first stage comprises transistors IVi l, IVL and M3, and the gain of this stage is determined by the dimension ratio of M2 and M1. The second stage comprises transistors M4, M5, M6 and M7, and the gain of this stage is determined by the dimension ratio of M5 and M4.
All the PMOS transistors M8 - M18 are used as bias current sources and provided with proper bias/source voltages. The parallel/serial configuration of PMOS
transistors e.g.
M 10 - M 18 is an effect of using a standard CMOS process with appropriate maskwork, which is also the feature of arranging the dimension ratios of M2-M1 and M5 -respectively, something which is immediately understood by the man of the art knowledgeable in CMOS construction.
Since the output impedance of MOS transistors decreases when the current is increased, double cascodes are used for enabling large currents, as shown in Fig. 3.
The input impedance is very low, determined by the transconductance of the input device Ml. The output impedance is very high, determined approximately by the product of the output impedance of transistor M5 and the gains of transistors M6 and M7.
It is seen in Fig. 3 that the only transistor that might be broken is M7. As long as its drain voltage is not so large that the gate-drain voltage or. drain-source voltage is smaller than its respective break-down voltage, transistor M7 is safe. The whole line driver may therefore be integrated in a standard CMOS process lilce the 5V
CMOS
process, and higher supply voltages can be used for the termination resistors.
As a numerical example, the twisted copper pair may have an impedance Z, of 100 .f2, with the terminal resistances Rt at 50 SZ and n 2.
The invention regards a CMOS differential line driver, in particular for driving a line comprising a twisted copper pair, and havin' a differential input with two input terminals and a differential analog output with two output terminals, which are each provided with a terminal resistor. It is thouaht primarily for use with twisted copper pairs or the lz'ke as used for high speed applications like high speed internet access.
A traditional type of a fully differential line driver is shown schematically in Fig. 1.
The twisted copper pair 1 is fed with power via a transformer 2. In order to obtain impedance matching, the transformed impedance of the twisted copper pair must be matched by tPm-ination resistors R.
A full description of an embodiment of this prior art is given in the article by Khorramabadi, TEEE J. Solid-State Circuits, Vol. 27 No. 4, (1992) p. 539, which is hereby included by reference into the present disclosure. General problems with line drivers are exposed in Johns and Essig, Integrated Circuits for Data Transmission Over Twisted-Pair Channels, IEEE J. Solid-State Circuits, Vol. 32 No. 3 (1997) p.
398.
This known architecture has several drawbacks. The line driver must have a low output impedance and high common-mode rejection, since very high voltage in the copper wire may be coupled back as common mode signals via paxasitic capacitance. The input-dependent variation in the output impedance of the line driver must also be very small in order to have low distortion. Therefore, effective feedbacks are needed in the line driver. Improper compensation in the line driver may result in low signal bandwidth and/or instability.
To deliver a high power to the Iine driver, a high supply voltage is usually needed.
3 5 A line driver of the envisac-red type would usually be handling signals from a high speed digital-to-analog converter (DAC) for high speed internet access. It is normal for such high speed DACs to be airan~ed as current-output devices, meaning that the driving DAC would have a high output impedance. In order to minimi~e the distortion in the DAC, the input impedance of the line driver must be low.
It is an object of the invention to obtain a fuIlv differential line driver, which obviates the above-mentioned difficulties. Another object is to obtain such a driver which can be made with a standard 5-V CMOS process. This would even enable its integrating with a driving DAC on a single chip. A further object is to obtain very low distortion at high bandwidth without stability problems.
SUMMARY OF THE INVENTION
Said objects and other objects and advantages are obtained, according to the invention, with a line dri.ver of the kind mentioned, and which is provided such (i) that the said input is a current input, (ii) that the driver comprises two current amplifiers (Ap, An), each forming a said input terminal (Ii,Q, Ii,n) and a said output terminal ( LP, Ioõ) respectively, and provided for feeding with a drive voltage (V,) (iii) that said terniinal resistors (R,) are connected with first ends to said output terminals (Lp, LQ) and have second ends connectible to a drive voltage (Vddh).
Typical for the inventive solution is that amplifying circuits are used, which are current amplifying, enabling the obtaining of a low input impedance and a high output impedance. For obtaining high common-mode rejection and impedance matching, termination resistors are arranged.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention shall now be described with reference to the figures, which are to be considered as non-limiting.
Fig. 1, already mentioned, shows a prior-art line driver.
Fig. 2 shows schematically the inventive solution.
Fig. 3 shows an exemplaiy embodiment schematically drawn, and applied for the use of a standard 5-V CMOS manufacturing process.
DETAILED DESCRIPTION OF THE INVENTION
The general concept of the invention may be understood from Fig. 2. A line driver is provided with a pair of current inputs I;'P and I;nA , The line driver (inside the dashed rectana-le) has a pair of current outputs, which are provided with terminal resistors R, connected to drive voltages Vda and connected to a transformer winding, with another winding connected to a twisted copper pair. As is apparent, there is inside the dashed rectang.ie a set of two current amplifiers AP and A. In order to easily interface with a driving DAC, the line driver itself will have a very low input impedance. Unlike the traditional approach shown in Fig. 1, the proposed line driver has a very high output impedance. Having a low input impedance and a hia,h output impedance, this line driver thus is a current-mode line driver.
The ~
termination resistors at the outputs of the line drivers will give high common-mode rejection and impedance matching.
The effective impedance must be equal to the transformed line impedance Z, for D impedance matching. If we assume that the output impedance of the line driver is very large, we have the value of the termination resistor R, given by (1) Rt=2 x ZT= 2xZA2 where ZT is the transformed line impedance, Z, is the line impedance, and n is the turns ratio of the transforrner.
Since the DAC usualiv uses offset binarv codes, the outputs of the DAC, i.e.
the input currents to the Iine driver, can be represented as Iinp = Ios + iarl 2 (2) Iinn = Ias - ia~ / 2 t~ ) where TaS is constant and iar is the analog representation of the digital input sisaal of the DAC. Suppose that the line driver has a gain of A for both positive and negative branches, we have the output currents given by Iop = A X (+os + lac / 2) (4) L. = A X(I,,,, - i.,r / 2) (5) Suppose the output impedance of the line driver is very large, then the ac current flowing into the transfornier is given by . 30 iT = KxAxi.,r (6) where the constant K is determined by the transformed line impedance ZT and the termination resistance Rt, given by K = R, / (2 R~ + ZT ) (7) Notice that the constant current Ios disappears in equation (6). As a matter of fact, any common-mode signals have no influence on the current flowing into the transformer and equation (7) holds independent of any common-mode signals.
In order to obtain impedance matching, equation (1) must be satisfied.
Therefore, we have K=R4 / (2Rt + ZT) =2ZT/(4Zr +ZT)= 0,4 (8) ., -The power delivered to the line is equal to the power delivered to the transformer and is given by Pi =P, =iT'' x ZT = K' x A'"x iac 2 X Zi /n'' _ ' = 0,16 x A2 x i.' x Zi / n' (9) This makes it clear that the line driver can be realized by using current ampiifiers terminated by resistors. Several advantages are won with such a solution.
Current amplifiers have inherently high bandwidth due to low internal impedance, and therefore this approach is suitable for high speed application. Further, no global feedback is necessary in the current ampli.fiers, and the line driver may thus be unconditionally stable in the global sense. Another great advantage with the architecture shown in Fig. 2 is that the supply voltage for the termination resistors can be much higher than the supply voltage for the line driver, in order to accommodate voltage swing at the output. As long as the output voltage swing of the driver is not very large, such that all the transistors within the line driver do not break out, the li.ne driver can be integrated with the DAC in a component made in a standard CMOS
process.
It may be noted that the use of an extra supply voltage for the termination resistors is advantageous in that large common-mode sipals are directed to this extra supply voltage without disturbing the supply voltages for the DAC and current amplifiers.
A disadvantage would be the power efficiency, since some power is wasted on the termination resistors due to the matching requirement.
In the above discussion, it has been assumed that the output impedance of the current amplifiers are infinite. If the output impedance of the current amplifiers changes dependent on the input current, distortion results. In order to ensure low distortion, a very high output impedance is desirable for the current ampli.fiers. This can be ensured by proper design.
Preferred embodiment In Fig. 3 is shown an example for a current amplif er, forming one of the amplifiers Ap within the dashed rectangle in Fig. 2. As the amplifier Aõ may be rigorously similar, only the first-mentioned current amplifier is shown in Fig. 2, with inputs and outputs shown.
In order to have high signal bandwidth, it is preferable to use only NMOS
transistors in the signal path. For obtaining a large gain A, it is preferable to use several stages in cascade in order to maintain the high bandwidth.
The current amplifier consists of two stages, The first stage comprises transistors IVi l, IVL and M3, and the gain of this stage is determined by the dimension ratio of M2 and M1. The second stage comprises transistors M4, M5, M6 and M7, and the gain of this stage is determined by the dimension ratio of M5 and M4.
All the PMOS transistors M8 - M18 are used as bias current sources and provided with proper bias/source voltages. The parallel/serial configuration of PMOS
transistors e.g.
M 10 - M 18 is an effect of using a standard CMOS process with appropriate maskwork, which is also the feature of arranging the dimension ratios of M2-M1 and M5 -respectively, something which is immediately understood by the man of the art knowledgeable in CMOS construction.
Since the output impedance of MOS transistors decreases when the current is increased, double cascodes are used for enabling large currents, as shown in Fig. 3.
The input impedance is very low, determined by the transconductance of the input device Ml. The output impedance is very high, determined approximately by the product of the output impedance of transistor M5 and the gains of transistors M6 and M7.
It is seen in Fig. 3 that the only transistor that might be broken is M7. As long as its drain voltage is not so large that the gate-drain voltage or. drain-source voltage is smaller than its respective break-down voltage, transistor M7 is safe. The whole line driver may therefore be integrated in a standard CMOS process lilce the 5V
CMOS
process, and higher supply voltages can be used for the termination resistors.
As a numerical example, the twisted copper pair may have an impedance Z, of 100 .f2, with the terminal resistances Rt at 50 SZ and n 2.
Claims (7)
1. A CMOS differential line driver having a differential input with two input terminals and a differential analog output with two output terminals, which are each provided with a termination resistor, wherein:
said input is a current input;
the driver comprises two current amplifiers each coupled to a respective one of said two input terminals, and to a respective one of said two input terminals, and to a respective one of said two output terminals and provided for feeding with a first drive voltage; and the termination resistors are connected with first ends to said output terminals and have second ends for connection to a second drive voltage, wherein each said current amplifier has an input stage comprising a first current source, a first NMOS transistor connected with its gate and drain to said first current source and its source to a common lead;
a second current source arranged to deliver a larger current than said first current source, a second NMOS transistor connected with its drain to second current source, with its gate to the gate of the first NMOS transistor and with its source to said common lead;
an output stage comprising a third NMOS transistor connected with its gate and drain to said second current source and its source to said common lead, a fourth NMOS
transistor connected with its source to said common lead, with its gate to the gate of said third NMOS transistor and with its drain to an output ; and said second NMOS transistor having a larger dimension in the ratio of W/L than said first NMOS transistor, and said fourth NMOS transistor having a larger dimension in the ratio of W/L than said third NMOS transistor.
said input is a current input;
the driver comprises two current amplifiers each coupled to a respective one of said two input terminals, and to a respective one of said two input terminals, and to a respective one of said two output terminals and provided for feeding with a first drive voltage; and the termination resistors are connected with first ends to said output terminals and have second ends for connection to a second drive voltage, wherein each said current amplifier has an input stage comprising a first current source, a first NMOS transistor connected with its gate and drain to said first current source and its source to a common lead;
a second current source arranged to deliver a larger current than said first current source, a second NMOS transistor connected with its drain to second current source, with its gate to the gate of the first NMOS transistor and with its source to said common lead;
an output stage comprising a third NMOS transistor connected with its gate and drain to said second current source and its source to said common lead, a fourth NMOS
transistor connected with its source to said common lead, with its gate to the gate of said third NMOS transistor and with its drain to an output ; and said second NMOS transistor having a larger dimension in the ratio of W/L than said first NMOS transistor, and said fourth NMOS transistor having a larger dimension in the ratio of W/L than said third NMOS transistor.
2. A driver according to claim 1, wherein the current amplifiers are provided for feeding with the first drive voltage, and the second ends of said termination resistors are for connection to the second drive voltage, the second drive voltage being higher than the first drive voltage.
6a
6a
3. A driver according to claim 1, further comprising a transformer having a first winding connected to said output terminals and a second winding having winding terminals for connecting to a symmetric line pair.
4. A driver according to claim 1, wherein said driver drives a line comprising a twisted copper pair.
5. The driver according to claim 1, wherein an input stage of each of the current amplifiers is a biased input stage.
6. The driver according to claim 5, wherein the biased input stage comprises a bias voltage input.
7. The driver according to claim 1, wherein each of the current amplifiers comprises a plurality of transistors.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9800635A SE511827C2 (en) | 1998-03-02 | 1998-03-02 | Differential line drive |
| SE9800635-6 | 1998-03-02 | ||
| PCT/SE1999/000299 WO1999045656A2 (en) | 1998-03-02 | 1999-03-02 | A differential line driver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2321571A1 CA2321571A1 (en) | 1999-09-10 |
| CA2321571C true CA2321571C (en) | 2008-10-07 |
Family
ID=20410357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002321571A Expired - Lifetime CA2321571C (en) | 1998-03-02 | 1999-03-02 | A differential line driver |
Country Status (13)
| Country | Link |
|---|---|
| US (1) | US6411136B1 (en) |
| EP (1) | EP1060574B1 (en) |
| JP (1) | JP2002506315A (en) |
| KR (1) | KR100626548B1 (en) |
| CN (1) | CN1186885C (en) |
| AU (1) | AU2756199A (en) |
| CA (1) | CA2321571C (en) |
| DE (1) | DE69931760T2 (en) |
| ES (1) | ES2263268T3 (en) |
| HK (1) | HK1038655B (en) |
| SE (1) | SE511827C2 (en) |
| TW (1) | TW494566B (en) |
| WO (1) | WO1999045656A2 (en) |
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| US6236238B1 (en) | 1999-05-13 | 2001-05-22 | Honeywell International Inc. | Output buffer with independently controllable current mirror legs |
| US7339997B2 (en) * | 2001-03-09 | 2008-03-04 | Agere Systems Inc. | Line driver and method of operating the same |
| US6970515B1 (en) * | 2001-06-08 | 2005-11-29 | Lsi Logic Corporation | Line driver for asymmetric digital subscriber line system |
| DE10135113B4 (en) * | 2001-07-19 | 2009-04-09 | Infineon Technologies Ag | Pseudo-differential power driver for amplifying a differential input current |
| US6498521B1 (en) * | 2001-11-29 | 2002-12-24 | Lsi Logic Corporation | Dynamic supply control for line driver |
| JP2005051496A (en) * | 2003-07-28 | 2005-02-24 | Kanji Otsuka | Signal transmission system and signal transmission line |
| US7394857B2 (en) * | 2003-10-31 | 2008-07-01 | Analog Devices, Inc. | Flexible versatile low-cost wireline transmit driver |
| JP4957495B2 (en) * | 2007-10-03 | 2012-06-20 | 株式会社豊田自動織機 | Signal transmission circuit |
| US8008944B2 (en) * | 2008-11-25 | 2011-08-30 | Qualcomm Incorporated | Low voltage differential signaling driver with programmable on-chip resistor termination |
| CN105610404B (en) * | 2015-12-23 | 2018-02-16 | 武汉邮电科学研究院 | A kind of distributed CD-ROM driver for realizing high amplitude of oscillation high bandwidth output |
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| US3825682A (en) | 1973-06-27 | 1974-07-23 | Rca Corp | Balanced line driver, line receiver system |
| US5204880A (en) | 1991-04-23 | 1993-04-20 | Level One Communications, Inc. | Differential line driver employing predistortion |
| JP2672721B2 (en) * | 1991-05-27 | 1997-11-05 | 株式会社東芝 | Sense amplifier circuit |
| US5235617A (en) * | 1991-06-11 | 1993-08-10 | Digital Equipment Corporation | Transmission media driving system |
| US5418478A (en) | 1993-07-30 | 1995-05-23 | Apple Computer, Inc. | CMOS differential twisted-pair driver |
| US5381112A (en) | 1993-09-22 | 1995-01-10 | Motorola, Inc. | Fully differential line driver circuit having common-mode feedback |
| SE502429C2 (en) * | 1994-02-21 | 1995-10-16 | Ellemtel Utvecklings Ab | Signal receiving and signal processing circuit |
| FR2724072A1 (en) * | 1994-08-25 | 1996-03-01 | Philips Composants | POWER AMPLIFIER STAGE, OF FOLLOWER TYPE. |
| US5598119A (en) * | 1995-04-05 | 1997-01-28 | Hewlett-Packard Company | Method and apparatus for a load adaptive pad driver |
| US5684429A (en) * | 1995-09-14 | 1997-11-04 | Ncr Corporation | CMOS gigabit serial link differential transmitter and receiver |
| US5796278A (en) * | 1996-04-26 | 1998-08-18 | Delco Electronics Corporaiton | Circuitry for controlling load current |
| US6008682A (en) * | 1996-06-14 | 1999-12-28 | Sun Microsystems, Inc. | Circuit and method for selectively enabling ECL type outputs |
| US5781040A (en) * | 1996-10-31 | 1998-07-14 | Hewlett-Packard Company | Transformer isolated driver for power transistor using frequency switching as the control signal |
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-
1998
- 1998-03-02 SE SE9800635A patent/SE511827C2/en not_active IP Right Cessation
- 1998-03-10 TW TW087103496A patent/TW494566B/en not_active IP Right Cessation
-
1999
- 1999-03-01 US US09/259,342 patent/US6411136B1/en not_active Expired - Lifetime
- 1999-03-02 EP EP99908046A patent/EP1060574B1/en not_active Expired - Lifetime
- 1999-03-02 ES ES99908046T patent/ES2263268T3/en not_active Expired - Lifetime
- 1999-03-02 CA CA002321571A patent/CA2321571C/en not_active Expired - Lifetime
- 1999-03-02 JP JP2000535102A patent/JP2002506315A/en active Pending
- 1999-03-02 AU AU27561/99A patent/AU2756199A/en not_active Abandoned
- 1999-03-02 DE DE69931760T patent/DE69931760T2/en not_active Expired - Lifetime
- 1999-03-02 KR KR1020007009668A patent/KR100626548B1/en not_active IP Right Cessation
- 1999-03-02 CN CNB998036196A patent/CN1186885C/en not_active Expired - Fee Related
- 1999-03-02 WO PCT/SE1999/000299 patent/WO1999045656A2/en active IP Right Grant
-
2002
- 2002-01-10 HK HK02100173.7A patent/HK1038655B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| HK1038655B (en) | 2005-09-16 |
| WO1999045656A3 (en) | 1999-10-14 |
| HK1038655A1 (en) | 2002-03-22 |
| SE511827C2 (en) | 1999-12-06 |
| CN1304585A (en) | 2001-07-18 |
| SE9800635D0 (en) | 1998-03-02 |
| KR100626548B1 (en) | 2006-09-22 |
| AU2756199A (en) | 1999-09-20 |
| KR20010041500A (en) | 2001-05-25 |
| WO1999045656A2 (en) | 1999-09-10 |
| EP1060574A2 (en) | 2000-12-20 |
| DE69931760T2 (en) | 2007-06-14 |
| TW494566B (en) | 2002-07-11 |
| EP1060574B1 (en) | 2006-06-07 |
| DE69931760D1 (en) | 2006-07-20 |
| CN1186885C (en) | 2005-01-26 |
| JP2002506315A (en) | 2002-02-26 |
| US6411136B1 (en) | 2002-06-25 |
| SE9800635L (en) | 1999-09-03 |
| ES2263268T3 (en) | 2006-12-01 |
| CA2321571A1 (en) | 1999-09-10 |
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| EEER | Examination request | ||
| MKEX | Expiry |
Effective date: 20190304 |