CA2326686A1 - Method and apparatus for controlling switching of connections among data processing devices - Google Patents
Method and apparatus for controlling switching of connections among data processing devices Download PDFInfo
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- CA2326686A1 CA2326686A1 CA002326686A CA2326686A CA2326686A1 CA 2326686 A1 CA2326686 A1 CA 2326686A1 CA 002326686 A CA002326686 A CA 002326686A CA 2326686 A CA2326686 A CA 2326686A CA 2326686 A1 CA2326686 A1 CA 2326686A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
Abstract
Multiple data processing devices may be interconnected through a switching mechanism while simultaneously conveying flow control information over the interconnect. Mechanisms are provided to ensure that the flow of data to and from interconnected devices has completed prior to changing the configuration of the switch. The switch may be a circuit switch, such as a crossbar switch, or a packet switch or a memory. The switch may be a separate device or may be part of either an input section or an output section of a data processing device. The configuration of the switch may be defined by command data loaded from a central controller, host computer, or other device connected to the switch, such as a sending device or a receiving device with a full duplex connection to the switch. The loading of a new configuration in the switch may be controlled by command data from a sending device, receiving device, or host computer, or by a controller that is responsive to a boundary signal transmitted over the interconnect. In a packet switch, a packet is directed to an output port specified in an address field in the packet. The packet switch directs both requests for data and the data between processing devices. In a memory switch, data may be written into or read from different areas of a memory by different devices. Through a separate channel, devices communicate about the information stored into and read from the memory. Switching is performed by a device selecting a memory into which data is written or from which data is read.
Description
METHOD AND APPARATUS FOR CONTROLLING SWITCHING OF CONNECTIONS
AMONG DATA PROCESSING DEVICES
FIELD OF THE INVENTION
The present invention is related to mechanisms for controlling the switching of connections among data processing devices, particularly video processing devices.
BACKGROUND
Analog motion video signals, such as those used in common television sets, video to tape recorders and other analog video systems, are temporally continuous and synchronous signals requiring various elements in a video system to be synchronized in order to be used.
In other words, analog motion video signals have a predetermined and fixed rate to which all of the elements in the video system are synchronized. Any element in the video system is designed with the assumption that there will be a constant rate for input and output of motion 15 video information.
More recently, it has been possible to store digital motion video data in data files on a computer. There are several methods for playing back such motion video data.
One method is called "pushing" or "streaming" of the motion video data. Streaming is based on an assumption that a system can provide an average data flow rate that is the same as the ultimate 2o data flow rate needed to ensure temporally continuous output of analog motion video images to a viewer. Sufficient buffering is used to account for expected latencies in data transfer between elements. In some cases, both the temporal and spatial resolution of the motion video information may need to be reduced. Such systems typically are designed with the assumption that transfer of audio and video data from a source through several processing 25 elements to its ultimate destination can neither be delayed nor stopped.
When a general purpose digital computer is used to process motion video information, a constant rate of flow of data generally cannot be maintained.
There may be variations in data flow rates due to various latencies in the computer system due to, for example, disk or memory read latency, interrupts from other processing elements in the 3o computer, etc. In addition, in some systems, such as editing systems, the ability to stop and restart playback is desirable. In order to overcome such problems, one method which has been used is to provide sufficient buffering in combination with an ability for data transfer to be stalled, such as shown in U.S. Patent No. 5,045,940 (Peters, et al.) which is hereby 25-04-2000 , , US 009907000 . . .. .... .. . .. ..
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incorporated by reference. These principles are used in a computer network as described in published European Patent Application No. 0674414A2. An extension of this combination to special effects processing is disclosed in PCT Publications W094/24815 and which are incorporated by reference. In this system, a data decompressor outputs data into a first buffer, from which it is transferred to a second buffer associated with a special effects processor. The first buffer indicates whether valid data is available. In addition, the special effects processor indicates to a controller associated with the decompressor whether it can receive data based on memory in the second buffer.
For example, a switching architecture is shown in "Effects of cascading on the to Performance of a Switching Subsystem," by Y. Doganata et al., in Communication for Global Users, Orlando, Dec. 6, 1992, Vol. 3, pp. 1493-1497.
One drawback of these systems is that they use a significant amount of buffering to accommodate for delays in data transfer between elements. They also are designed for use with a single predetermined format of media. Such video processing devices also generally are designed to provide a single output stream based on a combination of inputs. In order to provide connectivity among multiple devices, such interconnections generally are provided statically by a computer network or video switcher. Such mechanisms generally do not provide a way to control data flow through the switch for multiple dynamically configured connections.
SUMMARY
Multiple data processing devices may be interconnected through a switching mechanism while simultaneously conveying flow control information over the interconnect.
Mechanisms are provided to ensure that the flow of data to and from interconnected devices has completed prior to changing the configuration of the switch. The switch may be a circuit switch, such as a crossbar switch, or a packet switch or a memory. The switch may be a separate device or may be part of either an input section or an output section of a data processing device. The configuration of the switch may be defined by command data loaded from a central controller, host computer, or other device connected to the switch, such as a 3o sending device or a receiving device with a full duplex connection to the switch. The loading of a new configuration in the switch may be controlled by command data from a sending device, receiving device, or host computer, or by a controller that is responsive to a boundary signal transmitted over the interconnect. In a packet switch, a packet is directed to an output AMENDED SHEET
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AMONG DATA PROCESSING DEVICES
FIELD OF THE INVENTION
The present invention is related to mechanisms for controlling the switching of connections among data processing devices, particularly video processing devices.
BACKGROUND
Analog motion video signals, such as those used in common television sets, video to tape recorders and other analog video systems, are temporally continuous and synchronous signals requiring various elements in a video system to be synchronized in order to be used.
In other words, analog motion video signals have a predetermined and fixed rate to which all of the elements in the video system are synchronized. Any element in the video system is designed with the assumption that there will be a constant rate for input and output of motion 15 video information.
More recently, it has been possible to store digital motion video data in data files on a computer. There are several methods for playing back such motion video data.
One method is called "pushing" or "streaming" of the motion video data. Streaming is based on an assumption that a system can provide an average data flow rate that is the same as the ultimate 2o data flow rate needed to ensure temporally continuous output of analog motion video images to a viewer. Sufficient buffering is used to account for expected latencies in data transfer between elements. In some cases, both the temporal and spatial resolution of the motion video information may need to be reduced. Such systems typically are designed with the assumption that transfer of audio and video data from a source through several processing 25 elements to its ultimate destination can neither be delayed nor stopped.
When a general purpose digital computer is used to process motion video information, a constant rate of flow of data generally cannot be maintained.
There may be variations in data flow rates due to various latencies in the computer system due to, for example, disk or memory read latency, interrupts from other processing elements in the 3o computer, etc. In addition, in some systems, such as editing systems, the ability to stop and restart playback is desirable. In order to overcome such problems, one method which has been used is to provide sufficient buffering in combination with an ability for data transfer to be stalled, such as shown in U.S. Patent No. 5,045,940 (Peters, et al.) which is hereby 25-04-2000 , , US 009907000 . . .. .... .. . .. ..
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incorporated by reference. These principles are used in a computer network as described in published European Patent Application No. 0674414A2. An extension of this combination to special effects processing is disclosed in PCT Publications W094/24815 and which are incorporated by reference. In this system, a data decompressor outputs data into a first buffer, from which it is transferred to a second buffer associated with a special effects processor. The first buffer indicates whether valid data is available. In addition, the special effects processor indicates to a controller associated with the decompressor whether it can receive data based on memory in the second buffer.
For example, a switching architecture is shown in "Effects of cascading on the to Performance of a Switching Subsystem," by Y. Doganata et al., in Communication for Global Users, Orlando, Dec. 6, 1992, Vol. 3, pp. 1493-1497.
One drawback of these systems is that they use a significant amount of buffering to accommodate for delays in data transfer between elements. They also are designed for use with a single predetermined format of media. Such video processing devices also generally are designed to provide a single output stream based on a combination of inputs. In order to provide connectivity among multiple devices, such interconnections generally are provided statically by a computer network or video switcher. Such mechanisms generally do not provide a way to control data flow through the switch for multiple dynamically configured connections.
SUMMARY
Multiple data processing devices may be interconnected through a switching mechanism while simultaneously conveying flow control information over the interconnect.
Mechanisms are provided to ensure that the flow of data to and from interconnected devices has completed prior to changing the configuration of the switch. The switch may be a circuit switch, such as a crossbar switch, or a packet switch or a memory. The switch may be a separate device or may be part of either an input section or an output section of a data processing device. The configuration of the switch may be defined by command data loaded from a central controller, host computer, or other device connected to the switch, such as a 3o sending device or a receiving device with a full duplex connection to the switch. The loading of a new configuration in the switch may be controlled by command data from a sending device, receiving device, or host computer, or by a controller that is responsive to a boundary signal transmitted over the interconnect. In a packet switch, a packet is directed to an output AMENDED SHEET
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port specified in an address field in the packet. The packet switch directs both requests for data and the data between processing devices. In a memory switch, data may be written into AMENDED SHEET
port specified in an address field in the packet. The packet switch directs both requests for data and the data between processing devices. In a memory switch, data may be written into AMENDED SHEET
or read from different areas of a memory by different devices. Through a separate channel, devices communicate about the information stored into and read from the memory. Switching is performed by a device selecting a memory into which data is written or from which data is read.
Accordingly, in one aspect, a switching system dynamically configures connections between devices which control flow of data between the devices. The switching system includes an input for receiving data and a plurality of outputs to which data received through the input is directed. A switch directs data from the input to one of the plurality of outputs in response to command data. Flow control information is directed between the devices for 1o controlling the flow of data between connected devices. The switching system ensures that flow of data between connected devices completes prior to changing connections between the devices by the switch.
In another aspect, the switching system has a plurality of inputs for receiving data and an output to which data received through the inputs is directed. A switch directs data 15 from one of the inputs to the output in response to command data. Flow control information is directed between the devices for controlling the flow of data between connected devices.
The switching system ensures that flow of data between interconnected devices completes prior to changing connections between the devices by the switch.
In one embodiment, the switch is a circuit switch. The flow control information 2o between the devices includes a request signal from a first device, which is directed to a second device. A valid data signal may be received from the second device, which is directed to the first device. Connections between the devices are changed by the switch in response to a signal from the first device or the second device.
In another embodiment, the switch is a packet switch. Flow control information is 25 directed between the devices by conveying a request packet from a first device to a second device for indicating a channel and an amount of data requested from the second device, and by conveying a data packet from the second device to the first device indicating an amount of valid data. Connections among the devices are established by conveying data packets with an indication of a destination device and by routing data packets among devices according to the 3o indication of the destination device in the packet.
In another embodiment, the switch is a memory device. Flow control information is directed between the devices by using a first flow control channel connected between a first device and a second device, and a second flow control channel connected between the first device and a third device.
It should be understood that other aspects of the invention include processes for controlling switching such as performed by the switching system, and the various embodiments of the process. Systems of interconnected devices using switching systems in the various embodiments also are aspects of the invention. Another aspect of the invention is a video processing system in which different video processing devices are interconnected using a switching system to provide routing of video data for different and dynamically configurable video processing functions.
BRIEF DESCRIPTION OF THE DRAWING
In the drawing, Fig. 1 is a schematic diagram illustrating data transferred between a sending device and a receiving device over an interconnect;
Fig. 2 is a block diagram of a system using a switch to connect multiple sender and receiver devices;
Fig. 3 is a block diagram of a system in which multiple devices are connected through time division multiplexing and a switch;
Fig. 4 is a block diagram of an example configuration of devices interconnected 2o through multiple switches;
Figs. SA-SC are block diagrams of example packet transceivers used in a switching configuration;
Fig. 6 is a block diagram of one embodiment of a memory switch;
Fig. 7 is a block diagram of one embodiment of an adaptive delay memory switch;
and Fig. 8 is a block diagram of one embodiment using a memory subsystem as a switch.
DETAILED DESCRIPTION
An interconnect for connecting two data processing devices is shown in Fig. 1.
The diagram in Fig. 1 is general and illustrates the kind of data that is transferred between a 3o sending device 10 and receiving device 12 over an interconnect 14. The kind of information includes data 16, a valid data signal (DVAL) 18, an optional valid command signal (CVAL) 20 and a request signal (REQ) 22. The sending device also may transmit a reference clock 25-04-2000 , . U S 009907000 .. .... .. . .. ..
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Accordingly, in one aspect, a switching system dynamically configures connections between devices which control flow of data between the devices. The switching system includes an input for receiving data and a plurality of outputs to which data received through the input is directed. A switch directs data from the input to one of the plurality of outputs in response to command data. Flow control information is directed between the devices for 1o controlling the flow of data between connected devices. The switching system ensures that flow of data between connected devices completes prior to changing connections between the devices by the switch.
In another aspect, the switching system has a plurality of inputs for receiving data and an output to which data received through the inputs is directed. A switch directs data 15 from one of the inputs to the output in response to command data. Flow control information is directed between the devices for controlling the flow of data between connected devices.
The switching system ensures that flow of data between interconnected devices completes prior to changing connections between the devices by the switch.
In one embodiment, the switch is a circuit switch. The flow control information 2o between the devices includes a request signal from a first device, which is directed to a second device. A valid data signal may be received from the second device, which is directed to the first device. Connections between the devices are changed by the switch in response to a signal from the first device or the second device.
In another embodiment, the switch is a packet switch. Flow control information is 25 directed between the devices by conveying a request packet from a first device to a second device for indicating a channel and an amount of data requested from the second device, and by conveying a data packet from the second device to the first device indicating an amount of valid data. Connections among the devices are established by conveying data packets with an indication of a destination device and by routing data packets among devices according to the 3o indication of the destination device in the packet.
In another embodiment, the switch is a memory device. Flow control information is directed between the devices by using a first flow control channel connected between a first device and a second device, and a second flow control channel connected between the first device and a third device.
It should be understood that other aspects of the invention include processes for controlling switching such as performed by the switching system, and the various embodiments of the process. Systems of interconnected devices using switching systems in the various embodiments also are aspects of the invention. Another aspect of the invention is a video processing system in which different video processing devices are interconnected using a switching system to provide routing of video data for different and dynamically configurable video processing functions.
BRIEF DESCRIPTION OF THE DRAWING
In the drawing, Fig. 1 is a schematic diagram illustrating data transferred between a sending device and a receiving device over an interconnect;
Fig. 2 is a block diagram of a system using a switch to connect multiple sender and receiver devices;
Fig. 3 is a block diagram of a system in which multiple devices are connected through time division multiplexing and a switch;
Fig. 4 is a block diagram of an example configuration of devices interconnected 2o through multiple switches;
Figs. SA-SC are block diagrams of example packet transceivers used in a switching configuration;
Fig. 6 is a block diagram of one embodiment of a memory switch;
Fig. 7 is a block diagram of one embodiment of an adaptive delay memory switch;
and Fig. 8 is a block diagram of one embodiment using a memory subsystem as a switch.
DETAILED DESCRIPTION
An interconnect for connecting two data processing devices is shown in Fig. 1.
The diagram in Fig. 1 is general and illustrates the kind of data that is transferred between a 3o sending device 10 and receiving device 12 over an interconnect 14. The kind of information includes data 16, a valid data signal (DVAL) 18, an optional valid command signal (CVAL) 20 and a request signal (REQ) 22. The sending device also may transmit a reference clock 25-04-2000 , . U S 009907000 .. .... .. . .. ..
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(REF CLK) to the receiving device. The data may be data to be processed or command data and also may include a boundary signal which is a delimiter of the data being transferred, such as the end of an image for video data. Various implementations for the interconnect 14 and a protocol for controlling data flow over the interconnect are described in: International Publication No. W098/59494, published December 30, 1998, International Publication No.
W099/52289, published October 14, 1999, Inten~ational Publication No.
W099/52290, published October 14, 1999 and International Publication No. W099/52293, published October 14, 1999.
Several devices having such an interconnect may be connected in the manner shown to in Fig. 2. Fig. 2 shows a device 20 connected to devices 22 and 24 through a switch 26. A
device 28 also is connected to devices 22 and 24 through switch 28. The switch may be a circuit switch, a packet switch or a memory. A switch may be part of either an input section or an output section of a data processing device. In the different methods for configuring the different kinds of switches, mechanisms are provided to ensure that the flow of data to and from interconnected devices completes prior to changing the switching configuration provided by the switch. As a result, multiple processing devices may be interconnected through a switch while simultaneously conveying flow control information through the switch. Processing devices also may be provided with multiple input ports and/or multiple output ports to which data may be directed under dynamic control. A connection between an 2o output port and an input port may be selected within the device using a switch.
A circuit switch may have data buffering and may provide flow control signals on each port, or may be a simple crossbar switch. Using a circuit switch such as a crossbar switch, the pathways between connected devices are independent and separate, i.e., not shared, so that the behavior of one device does not directly affect the behavior of another device on the interconnect. Such a switch 26 can transport constant flow or a controlled flow data Any device connected to the switch 26 is able to connect to any other device attached to the switch.
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Fig. 3 illustrates the use of a switch to connect devices which are connected by a time division multiplexed interconnect Such time division multiplexing is described in more detail in International Publication No. W099/52289, published October 14, 1999. In this system, two devices 30 and 32 are connected to a time division multiplexing (TDM) transceiver 34 by a single interconnect. The TDM transceiver 34 is connected over a time division multiplexed connection to another TDM transceiver 36. The TDM
transceiver 36 demultiplexes the data from devices from 30 and 32 and provides a single stream connection for each device through a switch 38. The switch 38 in turn directs the data streams to another TDM transceiver 40. TDM transceiver 40 multiplexes its input streams from the crossbar 1o switch 38 onto a time division multiplexed interconnect to another TDM
transceiver 42 which demultiplexes the data to provide the data to devices 44 and 46.
Transceiver 48 operates in a manner similar to transceiver 40. Transceiver 50 similarly connects devices 52 and 54 to the transceiver 48. Devices 56 and 58 also connect to a transceiver 60 similar to transceiver 34 which is in turn connected to a transceiver 62 in order to connect the data flow 1s from devices 56 and 58 to switch 38. The use of the switch 38 in combination with time division multiplexing thus involves first decomposing the time division multiplexed data stream into individual data streams before directing them through the switch 38. The streams output by the switch are combined in TDM transceivers for transmission to the devices. The switch 38 creates any desired connectivity among devices 30, 32, 56, 58, 44, 46, 52 and 54.
2o There are several ways to control the configuration of a switch such as switch 26 in Fig. 2 or switch 38 in Fig. 3. The switch configuration may be controlled through a separate port under software control or by devices sending command data in the data transmitted over the interconnect. Both a sender and a receiver of data may have the ability to communicate connection information directly to the switch. Various methods for controlling a circuit-25 based switch, a packet switch and memory as a switch are described below.
Generally, a switch configuration may be changed either statically or dynamically during system operation if data. ordering is maintained. The data ordering is maintained for dynamic configuration of a switch because data flow devices are decoupled from each other in time, and the tasks they execute are allowed to complete at different times, at digerent 3o rates. A control system for dynamic configuration thus may introduce overhead and reduce data AMENDED SHEET
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throughput. In general, the switch connection configuration may change after the flow of data to and from previous connections is completed.
One way to control a circuit switch is by including in the switch a double-buffered register or queue of switch configurations which may be loaded by a central controller, host computer, or other device such as either a sending device or a receiving device. A new configuration may be loaded by the switch from the registers or queue at a time specified by a sender, or by a controller or by a receiver.
A field advance counter, described in International Publication No.
W098/59494, published December 30, 1998, may be used to control loading of a switch configuration in one embodiment. A field advance counter tracks data flow through a device by tracking the boundary signal. The counter is loaded with a value indicating the amount of data for which the configuration is valid. The counter is decremented in response to a boundary signal. The device being controlled by the field advance counter is the switch and possibly other devices in the same context. The command data provided to the switch is its configuration. The i5 switch uses the boundary signal to detect data boundaries at which a reconfiguration of switch parameters may occur. When the last component of data for a connection passes the switch, as indicated by the boundary signal, the switch loads its new connection if the field advance counter is at zero. The field advance counter in the switch tracks the boundary signal at the target device connection port rather than at the input device connection port.
2o Any new field advance counter value is loaded at the same time a new connection is made. A
system in which such a switch may be used is described in International Publication No.
W099/52276, published October 14, 1999 and International Publication No.
W099/52277, published October 14, 1999.
Instead of using a field advance counter to control loading of a switch configuration 25 from a double-buffered register or queue, command data embedded in the data sent by a sender through the switch to a receiver may be used to indicate the end of a connection sequence. This command data is termed herein a "fence." The fence may be defined using a AMENDED SHEET
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packet encoded through use of the valid command signal and valid data signal in conjunction with the data on the interconnect. Such packet encoding is described in International Publication No. W099/52289, published October 14, 1999 and International Publication No.
W099/52290, published October 14, 1999. Using a fence eliminates any field advance counter logic in the switch. In this embodiment, an output port on the switch has a "current connection" indicating an input port to which it is connected, and a next connection in the queue. When the switch detects a fence in an input data. stream, the switch is configured according to the next input port specified for the output port of the connection for the data in which the fence was detected.
to In order to relax the timing of the switch interface by allowing a connection to be made over several clock cycles, a gap may be introduced in the data. flow. For example, the sender may stop sending data over the interconnect for a period of time following the last component of the data, i.e., after the boundary signal is asserted. This period of time may be programmable in a sender. The duration of such a gap may be defined by any latency in controlling the data flow in response to handshake signals between the receiver and sender and any latency through intervening switches between the sender and receiver.
In the absence of a gap in the data flow, additional buffering may be used in the switch. The gap in the data flow also permits a phase-lock loop enough time to lock to any reference clock that accompanies the data over the interconnect from one device to the other through a switch 2o after a dynamic switch of a data connection.
In another embodiment, the receiver, rather than the sender, may control the loading a new configuration in the switch from the register or queue. In particular, the receiver in this embodiment has a duplex connection. One connection provides a path for receiving data from the switch. The other connection provides a path for transmitting command data to the switch. The command data may be encoded using the valid command signal, the valid data signal and data in the same manner that a sender encodes a fence sent to the switch. In this embodiment, the receiver may send the command data to the switch, for example, in response to a boundary signal. Although the sender still may have data available, the receiver de-asserts the request signal before changing the switch configuration, forcing the sender to wait AMENDED SHEET
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until the receiver requests data. In this manner, a receiving device may select from several sender devices and may cause switching to occur at the data boundary as identified by the boundary signal.
In some systems in which the sender or receiver controls the establishment of a new configuration at a switch, synchronizaxion or acknowledgment of the connections helps to avoid data loss. For example, referring now to Fig. 4, a system is shown including a device 70 connected to switch 72 to device 74. Device 76 also is connected to device 74 through switch 72, but the switch is not configured to maintain that connection.
Device 74 is connected through switch 78 to device 76, but the switch 78 is not configured to allow data l0 flow from device 74 to device 76. Device 80 is presently connected to provide data through switch 78 to device 76. Device 74 may be connected to device 76 after the connection between device 80 and device 76 terminates. Device 76 may be connected to device 74 through switch 72 after the connection to device 70 terminates. Device 74 instructs switch 78 to change the configuration, and device 76 instructs switch 72 to change to the configuration.
The switches wait for a fence to be received before establishing the new connection.
In some embodiments, command data may be present on an interconnect which is not flow controlled. In such an embodiment, a sending device, such as device 74 or 76, may attempt to issue command data to a receiver before the switch configuration is established if the configuration is requested by a receiver. In order to avoid this situation, the switch may 2o be configured to signal to a device that the receiver connection is established. A sending device may wait for this signal from the switch before issuing any command data. The switch waits until the end of a current connection, i.e., a fence, before signaling the sender of a new connection. Alternatively, a duplex connection may be provided to the receiver. A
device may send command data to the other device until an acknowledgment is received to confirm the establishment of a connection. A switch also may be used in a similar manner to indicate to a receiver using a command data. that a new connection has been made.
Another way to control switching between devices is by using a packet switch.
A
packet switch dynamically routes each packet of data to an output port which is specified in some way by data within the packet. A packet switch through which data. flow is controlled by the sender and receiver uses a packet protocol. One kind of packet protocol for this purpose is described in more detail in International Publication No.
W099/52290, published October 14, 1999.
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A packet switch generally receives data that incorporates an indication of a destination device, for example by indicating a network address of the device or an output port of the switch. In the embodiment shown in the last application cited above, the address is defined by a sequence of output ports on a series of interconnected devices. The packet switch sends command, interrupt and data packets from a sending device to a receiving device and sends request packets for controlling the flow of data from a receiving device to a sender device. An example embodiment of a switch, in combination with a transceiver to generate packet data from data interconnects will now be described in connection with Fig. 5.
Fig. SA illustrates a packet transceiver 300 which is connected to receive data from to one or more devices 302. The connection at 304 may be direct data link over which data flow is controlled by a protocol such as described in International Publication No.
W099/52289, published October 14, 1999. Transceiver 300 also is connected to one or more devices 306 through a similar port 308. Transceiver 300 sends data to devices 306. Ports 304 and 308 are connected through a dynamically configured switch 310, which may be configured using methods described above. Switch 310 may connect devices 302 either to devices 306 or to the transceiver 300. For each port of transceiver 300 that may receive data from a device 302, the transceiver 300 has a transmit buffer 312, which may be implemented as a FIFO. If the FIFO 312 is not full, a signal is generated by request logic 314, which issues a request signal to device 302. Similarly, transceiver 300 may send data to device 306 2o by sending daxa. from a receive buffer 316, which may be implemented as a FIFO. A request signal from device 306 is processed by request logic 318 to issue a read command to the receive buffer 316. Other similar transmit buffers and receive buffers (not shown) corresponding to other similar devices are connected through respective switches 320 and 322.
The flow of data between devices 306 and 302 and the transceiver 300 is regulated by the state of the FIFOs 312 and 316. The transceiver 300 tries to maintain a constant flow of data between FIFOs 312 and 316 and devices 302 and 306 by issuing packet requests to AMENDED SHEET
(REF CLK) to the receiving device. The data may be data to be processed or command data and also may include a boundary signal which is a delimiter of the data being transferred, such as the end of an image for video data. Various implementations for the interconnect 14 and a protocol for controlling data flow over the interconnect are described in: International Publication No. W098/59494, published December 30, 1998, International Publication No.
W099/52289, published October 14, 1999, Inten~ational Publication No.
W099/52290, published October 14, 1999 and International Publication No. W099/52293, published October 14, 1999.
Several devices having such an interconnect may be connected in the manner shown to in Fig. 2. Fig. 2 shows a device 20 connected to devices 22 and 24 through a switch 26. A
device 28 also is connected to devices 22 and 24 through switch 28. The switch may be a circuit switch, a packet switch or a memory. A switch may be part of either an input section or an output section of a data processing device. In the different methods for configuring the different kinds of switches, mechanisms are provided to ensure that the flow of data to and from interconnected devices completes prior to changing the switching configuration provided by the switch. As a result, multiple processing devices may be interconnected through a switch while simultaneously conveying flow control information through the switch. Processing devices also may be provided with multiple input ports and/or multiple output ports to which data may be directed under dynamic control. A connection between an 2o output port and an input port may be selected within the device using a switch.
A circuit switch may have data buffering and may provide flow control signals on each port, or may be a simple crossbar switch. Using a circuit switch such as a crossbar switch, the pathways between connected devices are independent and separate, i.e., not shared, so that the behavior of one device does not directly affect the behavior of another device on the interconnect. Such a switch 26 can transport constant flow or a controlled flow data Any device connected to the switch 26 is able to connect to any other device attached to the switch.
AMENDED SHEET
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Fig. 3 illustrates the use of a switch to connect devices which are connected by a time division multiplexed interconnect Such time division multiplexing is described in more detail in International Publication No. W099/52289, published October 14, 1999. In this system, two devices 30 and 32 are connected to a time division multiplexing (TDM) transceiver 34 by a single interconnect. The TDM transceiver 34 is connected over a time division multiplexed connection to another TDM transceiver 36. The TDM
transceiver 36 demultiplexes the data from devices from 30 and 32 and provides a single stream connection for each device through a switch 38. The switch 38 in turn directs the data streams to another TDM transceiver 40. TDM transceiver 40 multiplexes its input streams from the crossbar 1o switch 38 onto a time division multiplexed interconnect to another TDM
transceiver 42 which demultiplexes the data to provide the data to devices 44 and 46.
Transceiver 48 operates in a manner similar to transceiver 40. Transceiver 50 similarly connects devices 52 and 54 to the transceiver 48. Devices 56 and 58 also connect to a transceiver 60 similar to transceiver 34 which is in turn connected to a transceiver 62 in order to connect the data flow 1s from devices 56 and 58 to switch 38. The use of the switch 38 in combination with time division multiplexing thus involves first decomposing the time division multiplexed data stream into individual data streams before directing them through the switch 38. The streams output by the switch are combined in TDM transceivers for transmission to the devices. The switch 38 creates any desired connectivity among devices 30, 32, 56, 58, 44, 46, 52 and 54.
2o There are several ways to control the configuration of a switch such as switch 26 in Fig. 2 or switch 38 in Fig. 3. The switch configuration may be controlled through a separate port under software control or by devices sending command data in the data transmitted over the interconnect. Both a sender and a receiver of data may have the ability to communicate connection information directly to the switch. Various methods for controlling a circuit-25 based switch, a packet switch and memory as a switch are described below.
Generally, a switch configuration may be changed either statically or dynamically during system operation if data. ordering is maintained. The data ordering is maintained for dynamic configuration of a switch because data flow devices are decoupled from each other in time, and the tasks they execute are allowed to complete at different times, at digerent 3o rates. A control system for dynamic configuration thus may introduce overhead and reduce data AMENDED SHEET
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throughput. In general, the switch connection configuration may change after the flow of data to and from previous connections is completed.
One way to control a circuit switch is by including in the switch a double-buffered register or queue of switch configurations which may be loaded by a central controller, host computer, or other device such as either a sending device or a receiving device. A new configuration may be loaded by the switch from the registers or queue at a time specified by a sender, or by a controller or by a receiver.
A field advance counter, described in International Publication No.
W098/59494, published December 30, 1998, may be used to control loading of a switch configuration in one embodiment. A field advance counter tracks data flow through a device by tracking the boundary signal. The counter is loaded with a value indicating the amount of data for which the configuration is valid. The counter is decremented in response to a boundary signal. The device being controlled by the field advance counter is the switch and possibly other devices in the same context. The command data provided to the switch is its configuration. The i5 switch uses the boundary signal to detect data boundaries at which a reconfiguration of switch parameters may occur. When the last component of data for a connection passes the switch, as indicated by the boundary signal, the switch loads its new connection if the field advance counter is at zero. The field advance counter in the switch tracks the boundary signal at the target device connection port rather than at the input device connection port.
2o Any new field advance counter value is loaded at the same time a new connection is made. A
system in which such a switch may be used is described in International Publication No.
W099/52276, published October 14, 1999 and International Publication No.
W099/52277, published October 14, 1999.
Instead of using a field advance counter to control loading of a switch configuration 25 from a double-buffered register or queue, command data embedded in the data sent by a sender through the switch to a receiver may be used to indicate the end of a connection sequence. This command data is termed herein a "fence." The fence may be defined using a AMENDED SHEET
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packet encoded through use of the valid command signal and valid data signal in conjunction with the data on the interconnect. Such packet encoding is described in International Publication No. W099/52289, published October 14, 1999 and International Publication No.
W099/52290, published October 14, 1999. Using a fence eliminates any field advance counter logic in the switch. In this embodiment, an output port on the switch has a "current connection" indicating an input port to which it is connected, and a next connection in the queue. When the switch detects a fence in an input data. stream, the switch is configured according to the next input port specified for the output port of the connection for the data in which the fence was detected.
to In order to relax the timing of the switch interface by allowing a connection to be made over several clock cycles, a gap may be introduced in the data. flow. For example, the sender may stop sending data over the interconnect for a period of time following the last component of the data, i.e., after the boundary signal is asserted. This period of time may be programmable in a sender. The duration of such a gap may be defined by any latency in controlling the data flow in response to handshake signals between the receiver and sender and any latency through intervening switches between the sender and receiver.
In the absence of a gap in the data flow, additional buffering may be used in the switch. The gap in the data flow also permits a phase-lock loop enough time to lock to any reference clock that accompanies the data over the interconnect from one device to the other through a switch 2o after a dynamic switch of a data connection.
In another embodiment, the receiver, rather than the sender, may control the loading a new configuration in the switch from the register or queue. In particular, the receiver in this embodiment has a duplex connection. One connection provides a path for receiving data from the switch. The other connection provides a path for transmitting command data to the switch. The command data may be encoded using the valid command signal, the valid data signal and data in the same manner that a sender encodes a fence sent to the switch. In this embodiment, the receiver may send the command data to the switch, for example, in response to a boundary signal. Although the sender still may have data available, the receiver de-asserts the request signal before changing the switch configuration, forcing the sender to wait AMENDED SHEET
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until the receiver requests data. In this manner, a receiving device may select from several sender devices and may cause switching to occur at the data boundary as identified by the boundary signal.
In some systems in which the sender or receiver controls the establishment of a new configuration at a switch, synchronizaxion or acknowledgment of the connections helps to avoid data loss. For example, referring now to Fig. 4, a system is shown including a device 70 connected to switch 72 to device 74. Device 76 also is connected to device 74 through switch 72, but the switch is not configured to maintain that connection.
Device 74 is connected through switch 78 to device 76, but the switch 78 is not configured to allow data l0 flow from device 74 to device 76. Device 80 is presently connected to provide data through switch 78 to device 76. Device 74 may be connected to device 76 after the connection between device 80 and device 76 terminates. Device 76 may be connected to device 74 through switch 72 after the connection to device 70 terminates. Device 74 instructs switch 78 to change the configuration, and device 76 instructs switch 72 to change to the configuration.
The switches wait for a fence to be received before establishing the new connection.
In some embodiments, command data may be present on an interconnect which is not flow controlled. In such an embodiment, a sending device, such as device 74 or 76, may attempt to issue command data to a receiver before the switch configuration is established if the configuration is requested by a receiver. In order to avoid this situation, the switch may 2o be configured to signal to a device that the receiver connection is established. A sending device may wait for this signal from the switch before issuing any command data. The switch waits until the end of a current connection, i.e., a fence, before signaling the sender of a new connection. Alternatively, a duplex connection may be provided to the receiver. A
device may send command data to the other device until an acknowledgment is received to confirm the establishment of a connection. A switch also may be used in a similar manner to indicate to a receiver using a command data. that a new connection has been made.
Another way to control switching between devices is by using a packet switch.
A
packet switch dynamically routes each packet of data to an output port which is specified in some way by data within the packet. A packet switch through which data. flow is controlled by the sender and receiver uses a packet protocol. One kind of packet protocol for this purpose is described in more detail in International Publication No.
W099/52290, published October 14, 1999.
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A packet switch generally receives data that incorporates an indication of a destination device, for example by indicating a network address of the device or an output port of the switch. In the embodiment shown in the last application cited above, the address is defined by a sequence of output ports on a series of interconnected devices. The packet switch sends command, interrupt and data packets from a sending device to a receiving device and sends request packets for controlling the flow of data from a receiving device to a sender device. An example embodiment of a switch, in combination with a transceiver to generate packet data from data interconnects will now be described in connection with Fig. 5.
Fig. SA illustrates a packet transceiver 300 which is connected to receive data from to one or more devices 302. The connection at 304 may be direct data link over which data flow is controlled by a protocol such as described in International Publication No.
W099/52289, published October 14, 1999. Transceiver 300 also is connected to one or more devices 306 through a similar port 308. Transceiver 300 sends data to devices 306. Ports 304 and 308 are connected through a dynamically configured switch 310, which may be configured using methods described above. Switch 310 may connect devices 302 either to devices 306 or to the transceiver 300. For each port of transceiver 300 that may receive data from a device 302, the transceiver 300 has a transmit buffer 312, which may be implemented as a FIFO. If the FIFO 312 is not full, a signal is generated by request logic 314, which issues a request signal to device 302. Similarly, transceiver 300 may send data to device 306 2o by sending daxa. from a receive buffer 316, which may be implemented as a FIFO. A request signal from device 306 is processed by request logic 318 to issue a read command to the receive buffer 316. Other similar transmit buffers and receive buffers (not shown) corresponding to other similar devices are connected through respective switches 320 and 322.
The flow of data between devices 306 and 302 and the transceiver 300 is regulated by the state of the FIFOs 312 and 316. The transceiver 300 tries to maintain a constant flow of data between FIFOs 312 and 316 and devices 302 and 306 by issuing packet requests to AMENDED SHEET
another device, or by sending data in response to requests from other devices when data is available.
In order to transmit data from device 302 through transceiver 300, when data is available in buffer 312, a packet ready signal is sent to packet send logic 324. Packet send logic 324 provides a data ready signal 326 to switch selector 328. When data for this channel is authorized to be transmitted, the switch selector 328 sets the state of switch 320 and sends a send data signal 330 to the packet send logic 324. In turn, the packet send logic 324 instructs the FIFO 312 to read data which is transmitted to a packet wrapper 332. The packet wrapper forms the data into a packet and supplies it to a buffer 334 which outputs the packet. The to packet buffer 334 may be a double buffer to overlap packet transmission with packet assembly. Each port, e.g. 304 and 308, has a unique stream identifier (SID) associated with it.
Data and data requests are directed to the ports as identified by the SID. The SID also may be used to identify a packet context which is provided for each stream as indicated at 336. The packet context 336 is used in the construction of packet headers including target addressing, 15 stream identifier, etc.
The transmission of data from a device 302 is performed in response to a request packet received by the transceiver 300. The packet is received in a buffer 338 that also may be implemented as a double buffer. The stream identifier in a packet is used by stream selection circuit 340 to select a device 306 using switch 322. The packet unwrapper 342 2o transforms the header and data portions of the packet into a request signal 344 or data 346.
The request signal 344 is provided to the switch selector 328 in order to create a send data signal 330 to the indicated channel. When receiving data, packet request logic 348 generates a packet request 350 when the FIFO 316 is not full. The packet request signal 350 prompts the switch selector 328 to issue a send packet request 352 to the packet wrapper 332. The 25 transceiver 300 also may be used to generate command packets in response to command data.
The rate at which the data is sent by transceiver 300 also may be controlled in response to a packet rate control value identified in a request for data. The packet rate control value may be provided through request signal 344 to the switch selector 328.
The switch selector 328 includes a counter as described above which controls the rate at which packets 3o are output by the packet wrapper 332.
Fig. SB illustrates an example interconnection of devices using transceivers such as transceiver 300 in Fig. SA. In this example, system 400 is connected to system 402 through a packet protocol interconnect 404. Transceivers 406 and 408 provide a connection to the interconnect 404 and are implemented as shown in Fig. SA. System 402 includes devices 410, 412, 414 and 416 which are connected to the transceiver 408 in the same manner that devices 302 and 306 are connected to transceiver 300 in Fig. SA. Devices 418, 420, 422 and 424 similarly are connected to transceiver 406. Device 420 is a time division multiplexed interface that connects two devices 426 and 428 to the transceiver 406. Data streams in the system may be routed between devices using the transceivers 406 and 408 and even between devices within the same system because transceivers 406 and 408 include a dynamically configured switch 310 (Fig. SA). In addition to providing switching among devices, this 1 o transceiver switch enables multiple stream copies to be created from a single stream of data.
Another example system is shown in Fig. SC. In Fig. SC, systems 450 and 452 are interconnected by a packet protocol interface 454. The connection is provided by transceivers 456 and 458 which are implemented using the transceiver shown in Fig. SA.
System 452 includes a first device 460 which uses three data channels connected to the transceiver 458.
Such a device may be a high definition televisional (HDTV) device using 4:2:2 video and an alpha channel. A similar device 462 is found in system 450. Device 464 uses one channel and may provide a standard definition television signal (SDTV) defining 4:4:4:4 video and an alpha channel. A similar device 466 is shown in system 450. In this embodiment, the transceiver 456 combines multiple input streams, e.g. from devices 462 and 460 into a single 2o high speed connection 454. The single stream of data from connection 454 is divided into multiple streams to the devices 460, 462, 464 and 466. This capability is useful when transferring data streams that operate at a rate above that of a single port.
In these embodiments, the combination of a FIFO buffer and flow control protocols for each port on the transceiver enables the transceiver to maintain maximum data throughput when connecting devices across a packet protocol interface, e.g., 454, and through the transceiver. The high throughput and efficient interconnect utilization is provided with a flexible routing method.
The packet switch may be provided with buffering at its input and output ports to avoid underrun and ovemm conditions. The buffer may be implemented as a first-in/first-out 3o memory. The buffer should be large enough to sustain a target data throughput of the switch where multiple devices contend for the same destination port.
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Another kind of switch that may be used is a memory-based switch. Such a switch may be used in circumstances where several devices are interconnected by a memory. One embodiment of such as switch is shown in International Publication No.
W099/52293, published October 14, 1999.
Referring to Fig. 6, a memory 81 has three buffers, 82, 84 and 86. A first sending device 88 sends data to buffer 86. A second sending device 90 sends data to buffer 84. A
third sending device 92 sends data to buffer 82. The receiving device 94 may read data from any of the buffers 82, 84 and 86. In this figure, receiving device 94 is shown receiving data from sending device 92 through buffer 83. The sending devices 88, 90 and 92 send flow 1o control information over a flow control channel 96 to the device 94. The receiving device 94 sends flow control information back to any of the sending devices 88, 90 and 92 over control channel 96 according to the buffer from which it reads the data. If the memory 80 is host memory and the devices 88, 90, 92 and 94 are PCI devices, this system uses host memory as a flow controlled switch among the PCI devices. In this embodiment, the data flow passes through the memory. Flow control information is passed through a separate link. The flow control information also may have an associated switch, or flow control information from all senders may be received by each destination.
The control channel also may communicate auxiliary switching information between connected DMA devices. This auxiliary switching information permits remote devices to 2o implement dynamic packet switching through memory. Such auxiliary switching information may include the starting address of the data buger and memory, the buffer size and configuration, and the source address of the device connection at the destination end. The auxiliary information may include a memory address into which data is to be written or a device address to which data should be routed. The switching information also may be provided by a field advance counter.
In one embodiment, shown in Fig. 7, a fast memory is used as a multiport data switch with built in time-base correction and buffering. This embodiment allows multiple data stream copies to be created from a single input stream by allocating a separate buffer for each destination device. In Fig. 7, a memory 100 is accessed through a memory controller 102 by 3o a first memory access engine 104 and a second memory access engine 106.
Either device 108 or 110 write data into the memory 100 through DMA engine 106. Device 112 and AMENDED SHEET
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device 114 read data from the memory 100 through DMA 104. DMA engine 106 maintains a context for devices 108 and I 10. Similarly, DMA engine 104 maintains a context for devices 112 and 114. A flow control channel 116 is used between DMA engines 104 and 106, for each pair of contexts. In this embodiment, the devices implement switching by controlling the address into which data is written in the memory 100. Such techniques are described in more detail in International Publication No. W099/52292, published October 14, 1999. A
switch also may be connected between the devices 108, 110, 112 and 114 and the memory access engines 106 and 104.
A memory may be used as a switch into which packet data is assembled and to disassembled for further processing. In a packet system, the memory in which such an operation occurs should be the destination specified for the packet in its header. If the packet indicates that the memory is not the final destination of the packet, the entire packet is treated as data. When the data is read from the memory, the header may be modified before sending the packet to the next destination. The unified memory 120 also may be implemented using host memory.
Another embodiment shown in Fig. 8 for using a memory as a switch will now be described. In this embodiment, a large unified memory 120 is connected to a host interface 122 via a memory arbiter 124. The host interface 122 may connect the memory arbiter 124 to a local bus 126 and a host bus 128. Multiple ports for providing flow controlled data are 2o shown at 130 and 132. The number of ports is limited by the available bandwidth to the memory 120. Some inter-interface communications may be provided at block 134.
Each port 130, 132 has two multi-context direct memory access (DMA) engines, one for reading and one for writing. The number of contexts supported equals the number of active stream identifiers for the port. A DMA engine includes data and address FIFOs for accessing the memory 120. Broadcast interrupt packets or signals may be used to convey status of one port 130 to other ports and interfaces via the inter-interface communications block 134. The host interface also may have two multicontext DMA engines with FIFO
memories for reading and writing data to the memory in a similar connection to the inter-interface communications block 134. A host interface 122 may access the control and status registers in the memory subsystem. The local bus may be used to communicate with other subsystem components.
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The inter-interface communications block 134 gathers broadcast interrupts and status signals from the interfaces and distributes them to the other devices connected to the memory. Passing of these signals corresponds to the flow controlled channel described above in connection with Fig. 6. The arbiter 124 selects one of the interfaces, whether the host interface 122 or ports 130 or 132.
Switches may support transport of both constant flow and controlled flow streams of data. Although data streams arrive at devices with no specified alignment, a constant flow data stream may require alignment. A constant flow stream also is switched at synchronization points, such as the vertical SYNC signal. In order to account for time-base 1o delays between devices, and to ensure that these delays are compensated prior to creating a new connection, time-base correction may be used. A time-base corrector usually employs a frame buffer to store and synchronize the data. A controlled flow application may provide alignment using a small memory, such as a small first-in/first-out memory which stores a few components of video data.
is By providing mechanisms that ensure that the flow of data to and from interconnected devices has completed prior to changing the switching configuration of the switch, multiple processing devices may be interconnected while simultaneously conveying flow control information between interconnected devices. The various methods for controlling the configuration of the switch enable circuit switches, packet switches and memory switches to 2o be used and to be dynamically configured.
Having now described a few embodiments, it should be apparent to those skilled in the art that the foregoing is merely illustrative and not limiting, having been presented by way of example only. Numerous modifications and other embodiments are within the scope of one of ordinary skill in the art and are contemplated as falling within the scope of the 2s invention.
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In order to transmit data from device 302 through transceiver 300, when data is available in buffer 312, a packet ready signal is sent to packet send logic 324. Packet send logic 324 provides a data ready signal 326 to switch selector 328. When data for this channel is authorized to be transmitted, the switch selector 328 sets the state of switch 320 and sends a send data signal 330 to the packet send logic 324. In turn, the packet send logic 324 instructs the FIFO 312 to read data which is transmitted to a packet wrapper 332. The packet wrapper forms the data into a packet and supplies it to a buffer 334 which outputs the packet. The to packet buffer 334 may be a double buffer to overlap packet transmission with packet assembly. Each port, e.g. 304 and 308, has a unique stream identifier (SID) associated with it.
Data and data requests are directed to the ports as identified by the SID. The SID also may be used to identify a packet context which is provided for each stream as indicated at 336. The packet context 336 is used in the construction of packet headers including target addressing, 15 stream identifier, etc.
The transmission of data from a device 302 is performed in response to a request packet received by the transceiver 300. The packet is received in a buffer 338 that also may be implemented as a double buffer. The stream identifier in a packet is used by stream selection circuit 340 to select a device 306 using switch 322. The packet unwrapper 342 2o transforms the header and data portions of the packet into a request signal 344 or data 346.
The request signal 344 is provided to the switch selector 328 in order to create a send data signal 330 to the indicated channel. When receiving data, packet request logic 348 generates a packet request 350 when the FIFO 316 is not full. The packet request signal 350 prompts the switch selector 328 to issue a send packet request 352 to the packet wrapper 332. The 25 transceiver 300 also may be used to generate command packets in response to command data.
The rate at which the data is sent by transceiver 300 also may be controlled in response to a packet rate control value identified in a request for data. The packet rate control value may be provided through request signal 344 to the switch selector 328.
The switch selector 328 includes a counter as described above which controls the rate at which packets 3o are output by the packet wrapper 332.
Fig. SB illustrates an example interconnection of devices using transceivers such as transceiver 300 in Fig. SA. In this example, system 400 is connected to system 402 through a packet protocol interconnect 404. Transceivers 406 and 408 provide a connection to the interconnect 404 and are implemented as shown in Fig. SA. System 402 includes devices 410, 412, 414 and 416 which are connected to the transceiver 408 in the same manner that devices 302 and 306 are connected to transceiver 300 in Fig. SA. Devices 418, 420, 422 and 424 similarly are connected to transceiver 406. Device 420 is a time division multiplexed interface that connects two devices 426 and 428 to the transceiver 406. Data streams in the system may be routed between devices using the transceivers 406 and 408 and even between devices within the same system because transceivers 406 and 408 include a dynamically configured switch 310 (Fig. SA). In addition to providing switching among devices, this 1 o transceiver switch enables multiple stream copies to be created from a single stream of data.
Another example system is shown in Fig. SC. In Fig. SC, systems 450 and 452 are interconnected by a packet protocol interface 454. The connection is provided by transceivers 456 and 458 which are implemented using the transceiver shown in Fig. SA.
System 452 includes a first device 460 which uses three data channels connected to the transceiver 458.
Such a device may be a high definition televisional (HDTV) device using 4:2:2 video and an alpha channel. A similar device 462 is found in system 450. Device 464 uses one channel and may provide a standard definition television signal (SDTV) defining 4:4:4:4 video and an alpha channel. A similar device 466 is shown in system 450. In this embodiment, the transceiver 456 combines multiple input streams, e.g. from devices 462 and 460 into a single 2o high speed connection 454. The single stream of data from connection 454 is divided into multiple streams to the devices 460, 462, 464 and 466. This capability is useful when transferring data streams that operate at a rate above that of a single port.
In these embodiments, the combination of a FIFO buffer and flow control protocols for each port on the transceiver enables the transceiver to maintain maximum data throughput when connecting devices across a packet protocol interface, e.g., 454, and through the transceiver. The high throughput and efficient interconnect utilization is provided with a flexible routing method.
The packet switch may be provided with buffering at its input and output ports to avoid underrun and ovemm conditions. The buffer may be implemented as a first-in/first-out 3o memory. The buffer should be large enough to sustain a target data throughput of the switch where multiple devices contend for the same destination port.
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Another kind of switch that may be used is a memory-based switch. Such a switch may be used in circumstances where several devices are interconnected by a memory. One embodiment of such as switch is shown in International Publication No.
W099/52293, published October 14, 1999.
Referring to Fig. 6, a memory 81 has three buffers, 82, 84 and 86. A first sending device 88 sends data to buffer 86. A second sending device 90 sends data to buffer 84. A
third sending device 92 sends data to buffer 82. The receiving device 94 may read data from any of the buffers 82, 84 and 86. In this figure, receiving device 94 is shown receiving data from sending device 92 through buffer 83. The sending devices 88, 90 and 92 send flow 1o control information over a flow control channel 96 to the device 94. The receiving device 94 sends flow control information back to any of the sending devices 88, 90 and 92 over control channel 96 according to the buffer from which it reads the data. If the memory 80 is host memory and the devices 88, 90, 92 and 94 are PCI devices, this system uses host memory as a flow controlled switch among the PCI devices. In this embodiment, the data flow passes through the memory. Flow control information is passed through a separate link. The flow control information also may have an associated switch, or flow control information from all senders may be received by each destination.
The control channel also may communicate auxiliary switching information between connected DMA devices. This auxiliary switching information permits remote devices to 2o implement dynamic packet switching through memory. Such auxiliary switching information may include the starting address of the data buger and memory, the buffer size and configuration, and the source address of the device connection at the destination end. The auxiliary information may include a memory address into which data is to be written or a device address to which data should be routed. The switching information also may be provided by a field advance counter.
In one embodiment, shown in Fig. 7, a fast memory is used as a multiport data switch with built in time-base correction and buffering. This embodiment allows multiple data stream copies to be created from a single input stream by allocating a separate buffer for each destination device. In Fig. 7, a memory 100 is accessed through a memory controller 102 by 3o a first memory access engine 104 and a second memory access engine 106.
Either device 108 or 110 write data into the memory 100 through DMA engine 106. Device 112 and AMENDED SHEET
25-04-2000 . . US 009907000 .. .... .. . .. ..
.. .. . .. . .. . ..
. . . .... . .. . . ..
. . . . .... . . . .
. . . . . ..
-1~~. ... .. . .. ..
device 114 read data from the memory 100 through DMA 104. DMA engine 106 maintains a context for devices 108 and I 10. Similarly, DMA engine 104 maintains a context for devices 112 and 114. A flow control channel 116 is used between DMA engines 104 and 106, for each pair of contexts. In this embodiment, the devices implement switching by controlling the address into which data is written in the memory 100. Such techniques are described in more detail in International Publication No. W099/52292, published October 14, 1999. A
switch also may be connected between the devices 108, 110, 112 and 114 and the memory access engines 106 and 104.
A memory may be used as a switch into which packet data is assembled and to disassembled for further processing. In a packet system, the memory in which such an operation occurs should be the destination specified for the packet in its header. If the packet indicates that the memory is not the final destination of the packet, the entire packet is treated as data. When the data is read from the memory, the header may be modified before sending the packet to the next destination. The unified memory 120 also may be implemented using host memory.
Another embodiment shown in Fig. 8 for using a memory as a switch will now be described. In this embodiment, a large unified memory 120 is connected to a host interface 122 via a memory arbiter 124. The host interface 122 may connect the memory arbiter 124 to a local bus 126 and a host bus 128. Multiple ports for providing flow controlled data are 2o shown at 130 and 132. The number of ports is limited by the available bandwidth to the memory 120. Some inter-interface communications may be provided at block 134.
Each port 130, 132 has two multi-context direct memory access (DMA) engines, one for reading and one for writing. The number of contexts supported equals the number of active stream identifiers for the port. A DMA engine includes data and address FIFOs for accessing the memory 120. Broadcast interrupt packets or signals may be used to convey status of one port 130 to other ports and interfaces via the inter-interface communications block 134. The host interface also may have two multicontext DMA engines with FIFO
memories for reading and writing data to the memory in a similar connection to the inter-interface communications block 134. A host interface 122 may access the control and status registers in the memory subsystem. The local bus may be used to communicate with other subsystem components.
AMENDED SHEET
25-04-2000 , . US 009907000 ww ~~~~ ~~ ~ ww ww w ~ s w ~ w ~ ~ w ~
~ www ~ ~ w w w ~ w ~
~ wwww ~ ~ ~ w w w ~
- ~ ww ww~ ww ~ w~ w~
The inter-interface communications block 134 gathers broadcast interrupts and status signals from the interfaces and distributes them to the other devices connected to the memory. Passing of these signals corresponds to the flow controlled channel described above in connection with Fig. 6. The arbiter 124 selects one of the interfaces, whether the host interface 122 or ports 130 or 132.
Switches may support transport of both constant flow and controlled flow streams of data. Although data streams arrive at devices with no specified alignment, a constant flow data stream may require alignment. A constant flow stream also is switched at synchronization points, such as the vertical SYNC signal. In order to account for time-base 1o delays between devices, and to ensure that these delays are compensated prior to creating a new connection, time-base correction may be used. A time-base corrector usually employs a frame buffer to store and synchronize the data. A controlled flow application may provide alignment using a small memory, such as a small first-in/first-out memory which stores a few components of video data.
is By providing mechanisms that ensure that the flow of data to and from interconnected devices has completed prior to changing the switching configuration of the switch, multiple processing devices may be interconnected while simultaneously conveying flow control information between interconnected devices. The various methods for controlling the configuration of the switch enable circuit switches, packet switches and memory switches to 2o be used and to be dynamically configured.
Having now described a few embodiments, it should be apparent to those skilled in the art that the foregoing is merely illustrative and not limiting, having been presented by way of example only. Numerous modifications and other embodiments are within the scope of one of ordinary skill in the art and are contemplated as falling within the scope of the 2s invention.
AMENDED SHEET
Claims (10)
1. A switching system for dynamically configuring connections between devices which control flow of data between the devices, the switching system comprising an input for receiving data and a plurality of outputs to which data received through the input is directed, and a switch for directing data from the input to one of the plurality of outputs in response to command data, wherein the improvement comprises:
means for directing flow control information between the devices for controlling the flow of data between connected devices; and means for ensuring that flow of data between connected devices completes prior to changing connections between the devices by the switch.
means for directing flow control information between the devices for controlling the flow of data between connected devices; and means for ensuring that flow of data between connected devices completes prior to changing connections between the devices by the switch.
2. The switching system of claim 1, wherein the switch is a circuit switch, and wherein the means for directing flow control information between the devices includes an input for receiving a request signal from a first device and for directing the request signal to a second device, and an input for receiving a valid data signal from the second device and for directing the valid data signal to the first device, and wherein the means for ensuring includes means for changing connections between the devices by the switch in response to a signal from the first device or the second device.
3. The switching system of claim 1, wherein the switch is a packet switch, and wherein the means for directing flow control information between the devices includes means for conveying a request packet from a first device to a second device for indicating a channel and an amount of data requested from the second device, and for conveying a data packet from the second device to the first device indicating an amount of valid data, and wherein the means for ensuring includes means for conveying data packets with an indication of a destination device and means for routing data packets among devices according to the indication of the destination device in the packet.
4. The switching system of claim 1, wherein the switch is a memory device, wherein the means for directing flow control information between the devices includes a first flow control channel connected between a first device and a second device, and a second flow control channel connected between the first device and a third device.
5. A video processing system comprising two or more video processing devices interconnected using the switching system of any of claims 1-4.
6. A switching system for dynamically configuring connections between devices which control the flow of data between the devices, the switching system comprising, a plurality of inputs for receiving data and an output to which data received through the inputs is directed, and a switch for directing data from one of the inputs to the output in response to command data, wherein the improvement comprises:
means for directing flow control information between the devices for controlling the flow of data between connected devices; and means for ensuring that flow of data. between interconnected devices completes prior to changing connections between the devices by the switch.
means for directing flow control information between the devices for controlling the flow of data between connected devices; and means for ensuring that flow of data. between interconnected devices completes prior to changing connections between the devices by the switch.
7. The switching system of claim 6, wherein the switch is a circuit switch, and wherein the means for directing flow control information between the devices includes an input for receiving a request signal from a first device and for directing the request signal to a second device, and an input for receiving a valid data signal from the second device and for directing the valid data signal to the first device, and wherein the means for ensuring includes means for changing connections between the devices by the switch in response to a signal from the first device or the second device.
8. The switching system of claim 6, wherein the switch is a packet switch, and wherein the means for directing flow control information between the devices includes means for conveying a request packet from a first device to a second device for indicating a channel and an amount of data requested from the second device, and for conveying a data packet from the second device to the first device indicating an amount of valid data, and wherein the means for ensuring includes means for conveying data packets with an indication of a destination device and means for routing data packets among devices according to the indication of the destination device in the packet.
9. The switching system of claim 6, wherein the switch is a memory device, wherein the means for directing flow control information between the devices includes a first flow control channel connected between a first device and a second device, and a second flow control channel connected between the first device and a third device.
10. A video processing system comprising two or more video processing devices interconnected by the switching system of any of claim 6-9.
Applications Claiming Priority (3)
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| US09/054,863 | 1998-04-03 | ||
| US09/054,863 US6327253B1 (en) | 1998-04-03 | 1998-04-03 | Method and apparatus for controlling switching of connections among data processing devices |
| PCT/US1999/007000 WO1999052246A1 (en) | 1998-04-03 | 1999-03-30 | Method and apparatus for controlling switching of connections among data processing devices |
Publications (1)
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| CA2326686A1 true CA2326686A1 (en) | 1999-10-14 |
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| CA002326686A Abandoned CA2326686A1 (en) | 1998-04-03 | 1999-03-30 | Method and apparatus for controlling switching of connections among data processing devices |
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| US20030133448A1 (en) * | 1998-04-03 | 2003-07-17 | Craig R. Frink | Packet protocol for encoding and decoding video data and data flow signals and devices for implementing the packet protocol |
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| US6731809B1 (en) * | 1998-04-28 | 2004-05-04 | Brother Kogyo Kabushiki Kaisha | Moving picture data compression device |
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| US20020172197A1 (en) * | 2001-05-18 | 2002-11-21 | Dale Michele Zampetti | System interconnect with minimal overhead suitable for real-time applications |
| US7035294B2 (en) * | 2001-06-04 | 2006-04-25 | Calix Networks, Inc. | Backplane bus |
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| US7190412B2 (en) * | 2003-08-28 | 2007-03-13 | The Boeing Company | Video switching systems and methods |
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| CN114201428A (en) * | 2020-09-18 | 2022-03-18 | 高创(苏州)电子有限公司 | Electronic device and USB interface switching method |
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1999
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- 1999-03-30 WO PCT/US1999/007000 patent/WO1999052246A1/en not_active Application Discontinuation
- 1999-03-30 EP EP99917321A patent/EP1068701A1/en not_active Withdrawn
- 1999-03-30 AU AU35470/99A patent/AU3547099A/en not_active Abandoned
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| AU3547099A (en) | 1999-10-25 |
| US6327253B1 (en) | 2001-12-04 |
| EP1068701A1 (en) | 2001-01-17 |
| WO1999052246A1 (en) | 1999-10-14 |
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