CA2326894A1 - Voice and data apparatus comprising a selective tapping digital signal processing resource - Google Patents

Voice and data apparatus comprising a selective tapping digital signal processing resource Download PDF

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Publication number
CA2326894A1
CA2326894A1 CA002326894A CA2326894A CA2326894A1 CA 2326894 A1 CA2326894 A1 CA 2326894A1 CA 002326894 A CA002326894 A CA 002326894A CA 2326894 A CA2326894 A CA 2326894A CA 2326894 A1 CA2326894 A1 CA 2326894A1
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bus
protocol
data
coupled
circuit
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CA002326894A
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French (fr)
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CA2326894C (en
Inventor
Scott K. Pickett
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Vertical Networks Inc
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Vertical Networks Inc.
Scott K. Pickett
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Priority claimed from US09/055,072 external-priority patent/US6181694B1/en
Priority claimed from US09/161,550 external-priority patent/US6208658B1/en
Priority claimed from US09/163,596 external-priority patent/US6343074B1/en
Priority claimed from US09/167,408 external-priority patent/US6154465A/en
Priority claimed from US09/283,101 external-priority patent/US6266340B1/en
Application filed by Vertical Networks Inc., Scott K. Pickett filed Critical Vertical Networks Inc.
Publication of CA2326894A1 publication Critical patent/CA2326894A1/en
Application granted granted Critical
Publication of CA2326894C publication Critical patent/CA2326894C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H04L12/2854—Wide area networks, e.g. public data networks
    • H04L12/2856—Access arrangements, e.g. Internet access
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    • H04M7/1295—Details of dual tone multiple frequency signalling
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Abstract

Systems (Figs. 1 and 2) for transmitting voice/data using multiprotocols.

Claims (15)

1. A processing system providing voice and data communications over a wideband communication network, comprising:
a computing system;
a multi-protocol framing/deframing circuit coupled to the computing system over a first bus and receiving data over the first bus of two or more communication protocols, wherein the multi-protocol framing/deframing circuit comprises at least a first protocol framing/deframing circuit and a second protocol framing/deframing circuit and a switch coupled to receive data from, and transmit data to, the first bus, wherein the switch selectively couples data between the first bus and the first and second protocol framing/deframing circuits;
a multiplexing circuit coupled to the multi-protocol framing/deframing circuit and receiving commands from the computing system, wherein the multiplexing circuit selectively transmits data to and receives data from the multi-protocol framing/deframing circuit and selectively transmits data to and receives data from a second bus in a time division multiplexed mode utilizing a plurality of frames, each of the frames comprising a plurality of slots, wherein the multiplexing circuit, under control of the computing system, selectively couples data to and from particular slots of the frames;
a plurality of interface cards coupled to the second bus and receiving commands from the computing system, wherein the termination cards are coupled to the wideband communication network, wherein the termination cards selectively transmit data to and receive data from the second bus under control of the computing system; and a packet bus coupled to the computer, wherein data communications over the packet bus are coupled to the wideband communications network through the computer, multi-protocol framing/deframing circuit, multiplexing circuit, and the second bus, wherein voice communications simultaneously occur over the second bus.
2. The system of claim 1, wherein the second bus comprises an MVIP bus.
3. The system of claim 1, wherein the packet bus comprises an Ethernet bus.
4. The system of claim 1, wherein the data communications occur via the HDLC
protocol, wherein the framing/deframing circuit frames and deframes the data communications to and from the HDLC protocol.
5. A system comprising:
a TDM bus coupled to a wide area network;
a multiplexer coupled to the TDM bus, wherein the multiplexer maps data to predetermined slots of frames of the TDM bus;
a framer/deframer circuit coupled to the multiplexer, wherein the framer/deframer circuit comprises at least a first framer/deframer of a first protocol and a second framer/deframer of a second protocol;
a digital signal processor circuit coupled to the framer/deframer; and a computer coupled to the digital signal processor and the framer/deframer circuit;
wherein, the computer selectively couples data to the digital signal processor circuit for processing, wherein data communications over the wide area network in accordance with the first protocol occur through the first framer, multiplexer and TDM bus, wherein data communications over the wide area network in accordance with the second protocol occur through the second framer, multiplexer and TDM bus.
6. The system of claim 5, wherein the first protocol comprises HDLC.
7. The system of claim 5, wherein the second protocol comprises ATM.
8. The system of claim 5, wherein the first and second protocols each comprise HDLC.
9. The system of claim 5, further comprising a packet bus coupled to the computer.
10. The system of claim 5, further comprising a packet bus coupled to the computer, wherein packet data communications occur over the packet bus and voice communications occur simultaneously over the TDM bus.
11. The system of claim 9, wherein a packet data stream is coupled from the packet bus to the computer, wherein the packet data stream is converted to a first protocol data stream by the first framer/deframer, wherein the first protocol data stream is coupled to the wide area network via the multiplexer and TDM bus.
12. The system of claim 11, wherein the first protocol comprises HDLC.
13. In a communications system having interfaces for being coupled to a WAN
network, a plurality of telecommunication devices, a LAN network, and a plurality of computing devices, a method comprising the steps of:

monitoring inputs to the communications system, wherein the inputs include the status or availability of, or requests from, WAN network resources, or include requests from or existing connections to the telecommunications devices or computing devices;
in response to a first monitoring of the inputs, allocating the WAN network resources with a processor in the communications system based on a set of rules, and, in response to a second monitoring of the inputs, re-allocating the WAN network resources with the processor in the communications system based on the set of rules.
14. The method of claim 14, wherein the rules comprise least cost routing or best quality of service rules.
15. The method of claim 14, wherein the rules comprise a table or algorithm.
CA2326894A 1998-04-03 1999-04-05 Voice and data apparatus comprising a selective tapping digital signal processing resource Expired - Fee Related CA2326894C (en)

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
US5503698A 1998-04-03 1998-04-03
US09/055,036 1998-04-03
US09/055,072 1998-04-03
US09/055,072 US6181694B1 (en) 1998-04-03 1998-04-03 Systems and methods for multiple mode voice and data communciations using intelligently bridged TDM and packet buses
US09/161,550 1998-09-25
US09/161,550 US6208658B1 (en) 1998-09-25 1998-09-25 Systems and methods for multiple mode voice and data communications using intelligently bridged TDM and packet buses and methods for performing telephony and data functions using the same
US09/163,596 1998-09-29
US09/163,596 US6343074B1 (en) 1998-09-29 1998-09-29 Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses and methods for performing telephony and data functions using the same
US09/167,408 1998-10-06
US09/167,408 US6154465A (en) 1998-10-06 1998-10-06 Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses and methods for performing telephony and data functions using the same
US09/283,101 US6266340B1 (en) 1998-04-03 1999-03-31 Systems and methods for multiple voice data communication which includes interface cards including configurable clocks that are dynamically coupled to a TDS bus
US09/283,101 1999-03-31
PCT/US1999/007587 WO1999052237A1 (en) 1998-04-03 1999-04-05 System and method for transmitting voice and data using intelligent bridged tdm and packet buses

Publications (2)

Publication Number Publication Date
CA2326894A1 true CA2326894A1 (en) 1999-10-14
CA2326894C CA2326894C (en) 2010-07-13

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CA2326894A Expired - Fee Related CA2326894C (en) 1998-04-03 1999-04-05 Voice and data apparatus comprising a selective tapping digital signal processing resource

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US (1) US6366578B1 (en)
EP (1) EP1068693B1 (en)
JP (1) JP4243019B2 (en)
CA (1) CA2326894C (en)
WO (1) WO1999052237A1 (en)

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CA2326894C (en) 2010-07-13
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