CA2337172C - Method and apparatus for allocating functional units in a multithreaded vliw processor - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
Abstract
A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional VLIW architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes a compiler to detect parallelism. The disclosed multithreaded VLIW architecture exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supports multiple program sequencers, as in simultaneous multithreading. Instructions are allocated to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units. The allocate stage determines how to group the instructions together to maximize efficiency, by selecting appropriate instructions and assigning the instructions to the FUs. The criteria for selection are thread priority or resource availability or both. Under the thread priority criteria, different threads can have different priorities. The allocate stage selects and forwards the packets (or instructions from packets) for execution belonging to the thread with the highest priority according to the priority policy implemented.
Under the resource availability criteria, a packet (having up to K instructions) can be allocated only if the resources (functional units) required by the packet are available for the next cycle. Functional units report their availability to the allocate stage.
Under the resource availability criteria, a packet (having up to K instructions) can be allocated only if the resources (functional units) required by the packet are available for the next cycle. Functional units report their availability to the allocate stage.
Description
METHOD AND APPARATUS FOR ALLOCATING FUNCTIONAL UNITS
IN A MULTITHREADED VLIW PROCESSOR
Field of the Invention The present invention relates generally to multithreaded processors, and, more particularly, to a method and apparatus for allocating functional units in such multithreaded processors.
Background of the Invention Computer architecture designs attempt to complete workloads more quickly. A number of architecture designs have been proposed or suggested for exploiting program parallelism. Generally, an architecture that can issue more than one operation at a time is capable of executing a program faster than an architecture that can only issue one operation at a time. Most recent advances in computer architecture have been directed towards methods of issuing more than one operation at a time and thereby speed up the operation of programs. FIG. 1 illustrates a conventional microprocessor architecture 100. Specifically, the microprocessor 100 includes a program counter (PC) 110, a register set 120 and a number of functional units (FUs) AD Berenbaum 7-2-3-3 2 130-N. The redundant functional units (FUs) 130-1 through 130-N provide the illustrative microprocessor architecture 100 with sufficient hardware resources to perform a corresponding number of operations in parallel.
An architecture that exploits parallelism in a program issues operands to more than one functional unit at a time to speed up the program execution. A
number of architectures have been proposed or suggested with a parallel architecture, including superscalar processors, very long instruction word (VLIW) processors and multithreaded processors, each discussed below in conjunction with FIGS. 2, 4 and 5, respectively. Generally, a superscalar processor utilizes hardware at run-time to 1o dynamically determine if a number of operations from a single instruction stream are independent, and if so, the processor executes the instructions using parallel arithmetic and logic units (ALUs). Two instructions are said to be independent if none of the source operands are dependent on the destination operands of any instruction that precedes them. A very long instruction word (VLIW) processor evaluates the instructions during compilation and groups the operations appropriately, for parallel execution, based on dependency information. A multithreaded processor, on the other hand, executes more than one instruction stream in parallel, rather than attempting to exploit parallelism within a single instruction stream.
A superscalar processor architecture 200, shown in FIG. 2, has a 2o number of functional units that operate independently, in the event each is provided with valid data. For example, as shown in FIG. 2, the superscalar processor 200 has three functional units embodied as arithmetic and logic units (ALUs) 230-N, each of which can compute a result at the same time. The superscalar processor 200 includes a front-end section 208 having an instruction fetch block 210, an instruction decode block 215, and an instruction sequencing unit 220 (issue block). The instruction fetch block 210 obtains instructions from an input queue 205 of a single threaded instruction stream. The instruction sequencing unit 220 identifies independent instructions that can be executed simultaneously in the available arithmetic and logic units (ALUs) 230-N, in a known manner. The refine block 250 allows the instructions to complete, and also provides buffering and reordering for writing results back to the register set 240.
In the program fragment 310 shown in FIG. 3, instructions in locations L 1, L2 and L3 are independent, in that none of the source operands in instructions L2 and L3 are dependent on the destination operands of any instruction that precedes them. When the program counter (PC) is set to location Ll, the instruction sequencing unit 220 will look ahead in the instruction stream and detect that the instructions at L2 and L3 are independent, and thus all three can be issued simultaneously to the three available functional units 230-N. For a more detailed discussion of superscalar processors, see, for example, James. E. Smith and Gurindar. S. Sohi, "The Microarchitecture of Superscalar Processors," Proc. of the IEEE (Dec. 1995).
As previously indicated, a very long instruction word (VLIW) processor 400, shown in FIG.4, relies on software to detect data parallelism at compile time from a single instruction stream, rather than using hardware to dynamically detect parallelism at run time. A VLIW compiler, when presented with the source code that was used to generate the code fragment 310 in FIG. 3, would detect the instruction independence and construct a single, very long instruction comprised of all three operations. At run time, the issue logic of the processor 400 would issue this wide instruction in one cycle, directing data to all available functional units 43 0-N. As shown in FIG. 4, the very long instruction word (VLI~ processor 400 includes an integrated fetch/decode block 420 that obtains the previously grouped instructions 410 from memory. For a more detailed discussion of very long instruction word (VLIV~ processors, see, for example, Burton J. Smith, "Architecture and Applications of the HEP Multiprocessor Computer System," SPIE Real Time Signal Procesing IV, 241-248 (1981).
One variety of VLIW processors, for example, represented by the Multiflow architecture, discussed in Robert P. Colwell et al., "A VLIW
Architecture AD Berenbaum 7-2-3-3 4 for a Trace Scheduling Compiler," IEEE Transactions on Computers (August 1988), uses a fixed-width instruction, in which predefined fields direct data to all functional units 430-N at once. When all operations specified in the wide instruction are completed, the processor issues a new, mufti-operation instruction. Some more recent VLIW processors, such as the C6x processor commercially available from Texas Instruments, of Dallas, TX and the EPIC IA-64 processor commercially available from Intel Corp, of Santa Clara, CA, instead use a variable-length instruction packet, which contains one or more operations bundled together.
A multithreaded processor 500, shown in FIG. 5, gains performance improvements by executing more than one instruction stream in parallel, rather than attempting to exploit parallelism within a single instruction stream. The multithreaded processor 500 shown in FIG. 5 includes a program counter 510-N, a register set and a functional unit 530-N, each dedicated to a corresponding instruction stream N.
Alternate implementations of the multithreaded processor 500 have utilized a single functional unit 530, with several register sets 520-N and program counters 510-N.
Such alternate multithreaded processors 500 are designed in such a way that the processor 500 can switch instruction issue from one program counter/register set 510-N/520-N to another program counter/register set 510-N/520-N in one or two cycles.
A long latency instruction, such as a LOAD instruction, can thus be overlapped with shorter operations from other instruction streams. The TERA MTA architecture, commercially available from Tera Computer Company, of Seattle, WA, is an example of this type.
An extension of the multithreaded architecture 500, referred to as Simultaneous Multithreading, combines the superscalar architecture, discussed above in conjunction with FIG. 2, with the multithreaded designs, discussed above in conjunction with FIG. 5. For a detailed discussion of Simultaneous Multithreading techniques, see, for example, Dean Tullsen et al., "Simultaneous Multithreading:
Maximizing On-Chip Parallelism," Proc. of the 22nd Annual Int'1 Symposium on Computer Architecture, 392-403 (Santa Margherita Ligure, Italy, June 1995). Generally, in a Simultaneous Multithreading architecture, there is a pool of functional units, any number of which may be dynamically assigned to an instruction which can issue from any one of a number of 5 program counter/register set structures. By sharing the functional units among a number of program threads, the Simultaneous Multithreading architecture can make more efficient use of hardware than that shown in FIG. 5.
While the combined approach of the Simultaneous Multithreading architecture provides improved efficiency over the individual approaches of the 1o superscalar architecture or the multithreaded architecture, Simultaneous Multithreaded architectures still require elaborate issue logic to dynamically examine instruction streams in order to detect potential parallelism. A need therefore exists for a multithreaded processor architecture that does not require a dynamic determination of whether or not two instruction streams are independent. A further need exists for a multithreaded architecture that provides simultaneous multithreading. Yet another need exists for a multithreaded architecture that allocates functional units in such multithreaded processors in real-time.
Summary of the Invention Generally, a method and apparatus are disclosed for allocating 2o functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIV~ architectures and conventional multithreaded architectures. The combined architecture of the present invention reduces execution time within an individual program, as well as across a workload.
The present invention utilizes a compiler to detect parallelism in a multithreaded processor architecture. Thus, a multithreaded VLIW architecture is disclosed that exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supporting multiple program sequencers, as in simultaneous multithreading, but with reduced complexity in the issue logic, since a dynamic determination is not required.
The present invention allocates instructions to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage before arguments are dispatched to functional units. Generally, the allocate stage determines how to group the instructions together to maximize efficiency, by selecting appropriate instructions, based on thread priorities or resource availability, or both, and assigning the instructions to the functional units.
The allocate stage selects the appropriate M instructions for execution from the (up to) N * K instructions that were fetched and decoded in the pipeline. The criteria for instruction selection are thread priority or resource availability or both.
Under the thread priority criteria, different threads can have different priorities. The allocate stage selects and forwards the packets (or instructions from packets) for execution belonging to the thread with the highest priority according to the priority policy implemented. Under the resource availability criteria, a packet (having up to K
instructions) can be allocated only if the resources (such as functional units) required by the packet are available for the next cycle. Functional units report their availability to 2o the allocate stage.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
6a In accordance with one aspect of the present invention there is provided a multithreaded very large instruction word processor, comprising; a plurality of functional units for executing a plurality of instructions from an instruction stream having a plurality of threads, one or more of said threads having a an individual priority; and an allocator that selects instructions fiom said instruction stream and forwards said instructions to said plurality of functional units, said allocator selecting said instructions based on said thread priority and independently allocating said fvmctional units to any thread in said multithreaded instruction stream.
In accordance with another aspect of the present invention there is provided a method of processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising the steps of: executing said instructions using a plurality of functional units, said threads having a priority; selecting insti°uctions from said instruction stream based on said thread priority; and forwarding said selected instructions to said l5 plurality of functional units, wherein said functional ants can be allocated independently to any tlwead in said multithreaded instruction stream.
In accordance with yet another aspect of the present invention there is provided an article of manufacture for processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising: a computer readable medium having computer readable program code means embodied thereon, said computer readable program code means comprising program code means for causing a computer to: execute said instructions using a plurality of functional units, said threads having a priority; select instructions from said instruction stream based on said thread priority; and forward said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
Brief Description of the Drawings FIG. 1 illustrates a conventional generalized microprocessor architecture;
FIG. 2 is a schematic block diagram of a conventional superscalar processor architeetme;
AD Berenbaum 7-2-3-3 7 FIG. 3 is a program fragment illustrating the independence of operations;
FIG. 4 is a schematic block diagram of a conventional very long instruction word (VLI~ processor architecture;
FIG. 5 is a schematic block diagram of a conventional multithreaded processor;
FIG. 6 illustrates a multithreaded VLIW processor in accordance with the present invention;
FIG. 7A illustrates a conventional pipeline for a multithreaded 1o processor;
FIG. 7B illustrates a pipeline for a multithreaded processor in accordance with the present invention; and FIG. 8 is a schematic block diagram of an implementation of the allocate stage of FIG. 7B.
Detailed Descriution FIG. 6 illustrates a multithreaded VLIW processor 600 in accordance with the present invention. As shown in FIG. 6, there are three instruction threads, namely, thread A (TA), thread B (TB) and thread C (TC), each operating at instruction number n. In addition, the illustrative Multithreaded VLIW processor 600 includes 2o nine fiznctional units 620-1 through 620-9, which can be allocated independently to any thread TA-TC. Since the number of instructions across the illustrative three threads TA-TC is nine and the illustrative number of available fiznctional units 620 is also nine, then each of the instructions from all three threads TA-TC can issue their instruction packets in one cycle and move onto instruction n+I on the subsequent cycle.
It is noted that there is generally a one-to-one correspondence between instructions and the operation specified thereby. Thus, such terms are used interchangeably herein. It is further noted that in the situation where an instruction specifies multiple operations, it is assumed that the multithreaded VLIW
processor 600 AD Berenbaum 7-2-3-3 8 includes one or more multiple-operation functional units 620 to execute the instruction specifying multiple operations. An example of an architecture where instructions specifying multiple operations may be processed is complex instruction set computer (CISC).
The present invention allocates instructions to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units. Thus, FIG. 7A illustrates a conventional pipeline 700 comprised of a fetch stage 710, where a packet is obtained from memory, a decode stage 720, where the required functional units and registers are identified for the fetched instructions, and an execute stage 730, where the specified operations are performed and the results are processed.
Thus, in a conventional VLIW architecture, a packet containing up to K
instructions is fetched each cycle (in the fetch stage 710). Up to K
instructions are decoded in the decode stage 720 and sent to (up to) K functional units (FUs).
The registers corresponding to the instructions are read, the fiznctional units operate on them and the results are written back to registers in the execute stage 730.
It is assumed that up to three registers can be read and up to one register can be written per functional unit.
2o FIG. 7B illustrates a pipeline 750 in accordance with the present invention, where an allocate stage 780, discussed further below in conjunction with FIG. 8, is added for the implementation of multithreaded VLIW processors.
Generally, the allocate stage 780 determines how to group the operations together to maximize ei~ciency. Thus, the pipeline 750 includes a fetch stage 760, where up to N
packets are obtained from memory, a decode stage 770, where the functional units and registers are identified for the fetched instructions (up to N*K instructions), an allocate stage 780, where the appropriate instructions are selected and assigned to the FUs, and an AD Berenbaum 7-2-3-3 9 execute stage 790, where the specified operations are performed and the results are processed.
In the multithreaded VLIW processor 600 of the present invention, up to N threads are supported in hardware. N thread contexts exist and contain all possible registers of a single thread and all status information required. A
multithreaded VLIW processor 600 has M functional units, where M is greater than or equal to K.
The modified pipeline stage 750, shown in FIG. 7B, works in the following manner. In each cycle, up to N packets (each containing up to K instructions) are fetched at the fetch stage 760. The decode stage 770 decodes up to N*K instructions and determines 1o their requirements and the registers read and written. The allocate stage 780 selects M
out of (up to) N*K instructions and forwards them to the M functional units.
It is assumed that each functional unit can read up to 3 registers and write one register. In the execute stage 790, up to M functional units read up to 3 *M registers and write up to M registers.
The allocate stage 780 selects for execution the appropriate M
instructions from the (up to) N * K instructions that were fetched and decoded at stages 760 and 770. The criteria for selection are thread priority or resource availability or both. Under the thread priority criteria, different threads can have different priorities. The allocate stage 780 selects and forwards the packets (or instructions from 2o packets) for execution belonging to the thread with the highest priority according to the priority policy implemented. A multitude of priority policies can be implemented. For example, a priority policy for a multithreaded VLIW processor supporting N
contexts (N hardware threads) can have N priority levels. The highest priority thread in the processor is allocated before any other thread. Among threads with equal priority, the thread that waited the longest for allocation is preferred.
Under the resource availability criteria, a packet (having up to K
instructions) can be allocated only if the resources (functional units) required by the AD Berenbaum 7-2-3-3 10 packet are available for the next cycle. Functional units report their availability to the allocate stage 780.
FIG. 8 illustrates a schematic block diagram of an implementation of the allocate stage 780. As shown in FIG. 8, the hardware needed to implement the allocate stage 780 includes a priority encoder 810 and two crossbar switches 820, 830.
Generally, the priority encoder 810 examines the state of the multiple operations in each thread, as well as the state of the available functional units. The priority encoder 810 selects the packets that are going to execute and sets up the first crossbar switch 820 so that the appropriate register contents are transferred to the functional units at 1o the beginning of the next cycle. The output of the priority encoder 810 configures the first crossbar switch 820 to route data from selected threads to the appropriate functional units. This can be accomplished, for example, by sending the register identifiers (that include a thread identifier) to the functional units and letting the functional units read the register contents via a separate data network and using the crossbar switch 810 to move the appropriate register contents to latches that are read by the functional units at the beginning of the next cycle Out of the N packets that are fetched by the fetch stage 760 (FIG. 7B), the priority encoder 810 selects up to N packets for execution according to priority and resource availability. In other words, the priority encoder selects the highest priority 2o threads that do not request unavailable resources for execution. It then sets up the first crossbar switch 810. The input crossbar switch 810 routes up to 3K*N inputs to up to 3 *M outputs. The first crossbar switch 810 has the ability to transfer the register identifiers (or the contents of the appropriate registers) of each packet to the appropriate functional units.
Since there are up to N threads that can be selected in the same cycle and each thread can issue a packet of up to K instructions and each instruction can read up to 3 registers there are 3K*N register identifiers to select from. Since there are only M functional units and each functional unit can accept a single instruction, there are AD Berenbaum 7-2-3-3 11 only 3M register identifiers to be selected. Therefore, the crossbar switch implements a 3K*N to 3M routing of register identifiers (or register contents).
The output crossbar switch 830 routes M inputs to N*M or N*K
outputs. The second crossbar switch 830 is set up at the appropriate time to transfer the results of the functional units back to the appropriate registers. The second crossbar switch 830 can be implemented as a separate network by sending the register identifiers (that contain a thread identifier) to the functional units. When a functional unit computes a result, the fi~nctional unit routes the result to the given register identifier. There are M results that have to be routed to up to N threads.
Each thread 1o can accept up to K results. The second crossbar switch 830 routes M results to N*K
possible destinations. The second crossbar switch 830 can be implemented as M
buses that are connected to all N register files. In this case, the routing becomes M results to N*M possible destinations (if the register files have the ability to accept M
results).
It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.
IN A MULTITHREADED VLIW PROCESSOR
Field of the Invention The present invention relates generally to multithreaded processors, and, more particularly, to a method and apparatus for allocating functional units in such multithreaded processors.
Background of the Invention Computer architecture designs attempt to complete workloads more quickly. A number of architecture designs have been proposed or suggested for exploiting program parallelism. Generally, an architecture that can issue more than one operation at a time is capable of executing a program faster than an architecture that can only issue one operation at a time. Most recent advances in computer architecture have been directed towards methods of issuing more than one operation at a time and thereby speed up the operation of programs. FIG. 1 illustrates a conventional microprocessor architecture 100. Specifically, the microprocessor 100 includes a program counter (PC) 110, a register set 120 and a number of functional units (FUs) AD Berenbaum 7-2-3-3 2 130-N. The redundant functional units (FUs) 130-1 through 130-N provide the illustrative microprocessor architecture 100 with sufficient hardware resources to perform a corresponding number of operations in parallel.
An architecture that exploits parallelism in a program issues operands to more than one functional unit at a time to speed up the program execution. A
number of architectures have been proposed or suggested with a parallel architecture, including superscalar processors, very long instruction word (VLIW) processors and multithreaded processors, each discussed below in conjunction with FIGS. 2, 4 and 5, respectively. Generally, a superscalar processor utilizes hardware at run-time to 1o dynamically determine if a number of operations from a single instruction stream are independent, and if so, the processor executes the instructions using parallel arithmetic and logic units (ALUs). Two instructions are said to be independent if none of the source operands are dependent on the destination operands of any instruction that precedes them. A very long instruction word (VLIW) processor evaluates the instructions during compilation and groups the operations appropriately, for parallel execution, based on dependency information. A multithreaded processor, on the other hand, executes more than one instruction stream in parallel, rather than attempting to exploit parallelism within a single instruction stream.
A superscalar processor architecture 200, shown in FIG. 2, has a 2o number of functional units that operate independently, in the event each is provided with valid data. For example, as shown in FIG. 2, the superscalar processor 200 has three functional units embodied as arithmetic and logic units (ALUs) 230-N, each of which can compute a result at the same time. The superscalar processor 200 includes a front-end section 208 having an instruction fetch block 210, an instruction decode block 215, and an instruction sequencing unit 220 (issue block). The instruction fetch block 210 obtains instructions from an input queue 205 of a single threaded instruction stream. The instruction sequencing unit 220 identifies independent instructions that can be executed simultaneously in the available arithmetic and logic units (ALUs) 230-N, in a known manner. The refine block 250 allows the instructions to complete, and also provides buffering and reordering for writing results back to the register set 240.
In the program fragment 310 shown in FIG. 3, instructions in locations L 1, L2 and L3 are independent, in that none of the source operands in instructions L2 and L3 are dependent on the destination operands of any instruction that precedes them. When the program counter (PC) is set to location Ll, the instruction sequencing unit 220 will look ahead in the instruction stream and detect that the instructions at L2 and L3 are independent, and thus all three can be issued simultaneously to the three available functional units 230-N. For a more detailed discussion of superscalar processors, see, for example, James. E. Smith and Gurindar. S. Sohi, "The Microarchitecture of Superscalar Processors," Proc. of the IEEE (Dec. 1995).
As previously indicated, a very long instruction word (VLIW) processor 400, shown in FIG.4, relies on software to detect data parallelism at compile time from a single instruction stream, rather than using hardware to dynamically detect parallelism at run time. A VLIW compiler, when presented with the source code that was used to generate the code fragment 310 in FIG. 3, would detect the instruction independence and construct a single, very long instruction comprised of all three operations. At run time, the issue logic of the processor 400 would issue this wide instruction in one cycle, directing data to all available functional units 43 0-N. As shown in FIG. 4, the very long instruction word (VLI~ processor 400 includes an integrated fetch/decode block 420 that obtains the previously grouped instructions 410 from memory. For a more detailed discussion of very long instruction word (VLIV~ processors, see, for example, Burton J. Smith, "Architecture and Applications of the HEP Multiprocessor Computer System," SPIE Real Time Signal Procesing IV, 241-248 (1981).
One variety of VLIW processors, for example, represented by the Multiflow architecture, discussed in Robert P. Colwell et al., "A VLIW
Architecture AD Berenbaum 7-2-3-3 4 for a Trace Scheduling Compiler," IEEE Transactions on Computers (August 1988), uses a fixed-width instruction, in which predefined fields direct data to all functional units 430-N at once. When all operations specified in the wide instruction are completed, the processor issues a new, mufti-operation instruction. Some more recent VLIW processors, such as the C6x processor commercially available from Texas Instruments, of Dallas, TX and the EPIC IA-64 processor commercially available from Intel Corp, of Santa Clara, CA, instead use a variable-length instruction packet, which contains one or more operations bundled together.
A multithreaded processor 500, shown in FIG. 5, gains performance improvements by executing more than one instruction stream in parallel, rather than attempting to exploit parallelism within a single instruction stream. The multithreaded processor 500 shown in FIG. 5 includes a program counter 510-N, a register set and a functional unit 530-N, each dedicated to a corresponding instruction stream N.
Alternate implementations of the multithreaded processor 500 have utilized a single functional unit 530, with several register sets 520-N and program counters 510-N.
Such alternate multithreaded processors 500 are designed in such a way that the processor 500 can switch instruction issue from one program counter/register set 510-N/520-N to another program counter/register set 510-N/520-N in one or two cycles.
A long latency instruction, such as a LOAD instruction, can thus be overlapped with shorter operations from other instruction streams. The TERA MTA architecture, commercially available from Tera Computer Company, of Seattle, WA, is an example of this type.
An extension of the multithreaded architecture 500, referred to as Simultaneous Multithreading, combines the superscalar architecture, discussed above in conjunction with FIG. 2, with the multithreaded designs, discussed above in conjunction with FIG. 5. For a detailed discussion of Simultaneous Multithreading techniques, see, for example, Dean Tullsen et al., "Simultaneous Multithreading:
Maximizing On-Chip Parallelism," Proc. of the 22nd Annual Int'1 Symposium on Computer Architecture, 392-403 (Santa Margherita Ligure, Italy, June 1995). Generally, in a Simultaneous Multithreading architecture, there is a pool of functional units, any number of which may be dynamically assigned to an instruction which can issue from any one of a number of 5 program counter/register set structures. By sharing the functional units among a number of program threads, the Simultaneous Multithreading architecture can make more efficient use of hardware than that shown in FIG. 5.
While the combined approach of the Simultaneous Multithreading architecture provides improved efficiency over the individual approaches of the 1o superscalar architecture or the multithreaded architecture, Simultaneous Multithreaded architectures still require elaborate issue logic to dynamically examine instruction streams in order to detect potential parallelism. A need therefore exists for a multithreaded processor architecture that does not require a dynamic determination of whether or not two instruction streams are independent. A further need exists for a multithreaded architecture that provides simultaneous multithreading. Yet another need exists for a multithreaded architecture that allocates functional units in such multithreaded processors in real-time.
Summary of the Invention Generally, a method and apparatus are disclosed for allocating 2o functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIV~ architectures and conventional multithreaded architectures. The combined architecture of the present invention reduces execution time within an individual program, as well as across a workload.
The present invention utilizes a compiler to detect parallelism in a multithreaded processor architecture. Thus, a multithreaded VLIW architecture is disclosed that exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supporting multiple program sequencers, as in simultaneous multithreading, but with reduced complexity in the issue logic, since a dynamic determination is not required.
The present invention allocates instructions to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage before arguments are dispatched to functional units. Generally, the allocate stage determines how to group the instructions together to maximize efficiency, by selecting appropriate instructions, based on thread priorities or resource availability, or both, and assigning the instructions to the functional units.
The allocate stage selects the appropriate M instructions for execution from the (up to) N * K instructions that were fetched and decoded in the pipeline. The criteria for instruction selection are thread priority or resource availability or both.
Under the thread priority criteria, different threads can have different priorities. The allocate stage selects and forwards the packets (or instructions from packets) for execution belonging to the thread with the highest priority according to the priority policy implemented. Under the resource availability criteria, a packet (having up to K
instructions) can be allocated only if the resources (such as functional units) required by the packet are available for the next cycle. Functional units report their availability to 2o the allocate stage.
A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
6a In accordance with one aspect of the present invention there is provided a multithreaded very large instruction word processor, comprising; a plurality of functional units for executing a plurality of instructions from an instruction stream having a plurality of threads, one or more of said threads having a an individual priority; and an allocator that selects instructions fiom said instruction stream and forwards said instructions to said plurality of functional units, said allocator selecting said instructions based on said thread priority and independently allocating said fvmctional units to any thread in said multithreaded instruction stream.
In accordance with another aspect of the present invention there is provided a method of processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising the steps of: executing said instructions using a plurality of functional units, said threads having a priority; selecting insti°uctions from said instruction stream based on said thread priority; and forwarding said selected instructions to said l5 plurality of functional units, wherein said functional ants can be allocated independently to any tlwead in said multithreaded instruction stream.
In accordance with yet another aspect of the present invention there is provided an article of manufacture for processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising: a computer readable medium having computer readable program code means embodied thereon, said computer readable program code means comprising program code means for causing a computer to: execute said instructions using a plurality of functional units, said threads having a priority; select instructions from said instruction stream based on said thread priority; and forward said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
Brief Description of the Drawings FIG. 1 illustrates a conventional generalized microprocessor architecture;
FIG. 2 is a schematic block diagram of a conventional superscalar processor architeetme;
AD Berenbaum 7-2-3-3 7 FIG. 3 is a program fragment illustrating the independence of operations;
FIG. 4 is a schematic block diagram of a conventional very long instruction word (VLI~ processor architecture;
FIG. 5 is a schematic block diagram of a conventional multithreaded processor;
FIG. 6 illustrates a multithreaded VLIW processor in accordance with the present invention;
FIG. 7A illustrates a conventional pipeline for a multithreaded 1o processor;
FIG. 7B illustrates a pipeline for a multithreaded processor in accordance with the present invention; and FIG. 8 is a schematic block diagram of an implementation of the allocate stage of FIG. 7B.
Detailed Descriution FIG. 6 illustrates a multithreaded VLIW processor 600 in accordance with the present invention. As shown in FIG. 6, there are three instruction threads, namely, thread A (TA), thread B (TB) and thread C (TC), each operating at instruction number n. In addition, the illustrative Multithreaded VLIW processor 600 includes 2o nine fiznctional units 620-1 through 620-9, which can be allocated independently to any thread TA-TC. Since the number of instructions across the illustrative three threads TA-TC is nine and the illustrative number of available fiznctional units 620 is also nine, then each of the instructions from all three threads TA-TC can issue their instruction packets in one cycle and move onto instruction n+I on the subsequent cycle.
It is noted that there is generally a one-to-one correspondence between instructions and the operation specified thereby. Thus, such terms are used interchangeably herein. It is further noted that in the situation where an instruction specifies multiple operations, it is assumed that the multithreaded VLIW
processor 600 AD Berenbaum 7-2-3-3 8 includes one or more multiple-operation functional units 620 to execute the instruction specifying multiple operations. An example of an architecture where instructions specifying multiple operations may be processed is complex instruction set computer (CISC).
The present invention allocates instructions to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units. Thus, FIG. 7A illustrates a conventional pipeline 700 comprised of a fetch stage 710, where a packet is obtained from memory, a decode stage 720, where the required functional units and registers are identified for the fetched instructions, and an execute stage 730, where the specified operations are performed and the results are processed.
Thus, in a conventional VLIW architecture, a packet containing up to K
instructions is fetched each cycle (in the fetch stage 710). Up to K
instructions are decoded in the decode stage 720 and sent to (up to) K functional units (FUs).
The registers corresponding to the instructions are read, the fiznctional units operate on them and the results are written back to registers in the execute stage 730.
It is assumed that up to three registers can be read and up to one register can be written per functional unit.
2o FIG. 7B illustrates a pipeline 750 in accordance with the present invention, where an allocate stage 780, discussed further below in conjunction with FIG. 8, is added for the implementation of multithreaded VLIW processors.
Generally, the allocate stage 780 determines how to group the operations together to maximize ei~ciency. Thus, the pipeline 750 includes a fetch stage 760, where up to N
packets are obtained from memory, a decode stage 770, where the functional units and registers are identified for the fetched instructions (up to N*K instructions), an allocate stage 780, where the appropriate instructions are selected and assigned to the FUs, and an AD Berenbaum 7-2-3-3 9 execute stage 790, where the specified operations are performed and the results are processed.
In the multithreaded VLIW processor 600 of the present invention, up to N threads are supported in hardware. N thread contexts exist and contain all possible registers of a single thread and all status information required. A
multithreaded VLIW processor 600 has M functional units, where M is greater than or equal to K.
The modified pipeline stage 750, shown in FIG. 7B, works in the following manner. In each cycle, up to N packets (each containing up to K instructions) are fetched at the fetch stage 760. The decode stage 770 decodes up to N*K instructions and determines 1o their requirements and the registers read and written. The allocate stage 780 selects M
out of (up to) N*K instructions and forwards them to the M functional units.
It is assumed that each functional unit can read up to 3 registers and write one register. In the execute stage 790, up to M functional units read up to 3 *M registers and write up to M registers.
The allocate stage 780 selects for execution the appropriate M
instructions from the (up to) N * K instructions that were fetched and decoded at stages 760 and 770. The criteria for selection are thread priority or resource availability or both. Under the thread priority criteria, different threads can have different priorities. The allocate stage 780 selects and forwards the packets (or instructions from 2o packets) for execution belonging to the thread with the highest priority according to the priority policy implemented. A multitude of priority policies can be implemented. For example, a priority policy for a multithreaded VLIW processor supporting N
contexts (N hardware threads) can have N priority levels. The highest priority thread in the processor is allocated before any other thread. Among threads with equal priority, the thread that waited the longest for allocation is preferred.
Under the resource availability criteria, a packet (having up to K
instructions) can be allocated only if the resources (functional units) required by the AD Berenbaum 7-2-3-3 10 packet are available for the next cycle. Functional units report their availability to the allocate stage 780.
FIG. 8 illustrates a schematic block diagram of an implementation of the allocate stage 780. As shown in FIG. 8, the hardware needed to implement the allocate stage 780 includes a priority encoder 810 and two crossbar switches 820, 830.
Generally, the priority encoder 810 examines the state of the multiple operations in each thread, as well as the state of the available functional units. The priority encoder 810 selects the packets that are going to execute and sets up the first crossbar switch 820 so that the appropriate register contents are transferred to the functional units at 1o the beginning of the next cycle. The output of the priority encoder 810 configures the first crossbar switch 820 to route data from selected threads to the appropriate functional units. This can be accomplished, for example, by sending the register identifiers (that include a thread identifier) to the functional units and letting the functional units read the register contents via a separate data network and using the crossbar switch 810 to move the appropriate register contents to latches that are read by the functional units at the beginning of the next cycle Out of the N packets that are fetched by the fetch stage 760 (FIG. 7B), the priority encoder 810 selects up to N packets for execution according to priority and resource availability. In other words, the priority encoder selects the highest priority 2o threads that do not request unavailable resources for execution. It then sets up the first crossbar switch 810. The input crossbar switch 810 routes up to 3K*N inputs to up to 3 *M outputs. The first crossbar switch 810 has the ability to transfer the register identifiers (or the contents of the appropriate registers) of each packet to the appropriate functional units.
Since there are up to N threads that can be selected in the same cycle and each thread can issue a packet of up to K instructions and each instruction can read up to 3 registers there are 3K*N register identifiers to select from. Since there are only M functional units and each functional unit can accept a single instruction, there are AD Berenbaum 7-2-3-3 11 only 3M register identifiers to be selected. Therefore, the crossbar switch implements a 3K*N to 3M routing of register identifiers (or register contents).
The output crossbar switch 830 routes M inputs to N*M or N*K
outputs. The second crossbar switch 830 is set up at the appropriate time to transfer the results of the functional units back to the appropriate registers. The second crossbar switch 830 can be implemented as a separate network by sending the register identifiers (that contain a thread identifier) to the functional units. When a functional unit computes a result, the fi~nctional unit routes the result to the given register identifier. There are M results that have to be routed to up to N threads.
Each thread 1o can accept up to K results. The second crossbar switch 830 routes M results to N*K
possible destinations. The second crossbar switch 830 can be implemented as M
buses that are connected to all N register files. In this case, the routing becomes M results to N*M possible destinations (if the register files have the ability to accept M
results).
It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.
Claims (16)
1. A multithreaded very large instruction word processor, comprising:
a plurality of functional units for executing a plurality of instructions from an instruction stream having a plurality of threads, one or more of said threads having a an individual priority; and an allocator that selects instructions from said instruction stream and forwards said instructions to said plurality of functional units, said allocator selecting said instructions based on said thread priority and independently allocating said functional units to any thread in said multithreaded instruction stream.
a plurality of functional units for executing a plurality of instructions from an instruction stream having a plurality of threads, one or more of said threads having a an individual priority; and an allocator that selects instructions from said instruction stream and forwards said instructions to said plurality of functional units, said allocator selecting said instructions based on said thread priority and independently allocating said functional units to any thread in said multithreaded instruction stream.
2. The multithreaded very large instruction word processor of claim 1, wherein said thread priority allows different threads to have different priorities.
3. The multithreaded very large instruction word processor of claim 1, wherein said allocator selects and forwards said instructions for execution belonging to the thread with the highest priority.
4. The multithreaded very large instruction word processor of claim 1, wherein said allocator selects and forwards said instructions based on said thread priority and on a resource availability.
5. A multithreaded very large instruction word processor, comprising:
a plurality of functional units for executing a plurality of instructions from a multithreaded instruction stream; and an allocator that selects instructions from said instruction stream and forwards said instructions to said plurality of functional units, said allocator selecting said instructions based on resource availability and independently allocating said functional units to any thread in said multithreaded instruction stream.
a plurality of functional units for executing a plurality of instructions from a multithreaded instruction stream; and an allocator that selects instructions from said instruction stream and forwards said instructions to said plurality of functional units, said allocator selecting said instructions based on resource availability and independently allocating said functional units to any thread in said multithreaded instruction stream.
6. The multithreaded very large instruction word processor of claim 5, wherein said resource availability allows said instructions to be allocated only if the resources required by the instructions are available for the next cycle.
7. The multithreaded very large instruction word processor of claim 5, wherein said resources comprise; said functional units.
8. The multithreaded very large instruction word processor of claim 5, wherein said allocator selects and forwards said instructions based on said resource availability and on a priority assigned to said threads.
9. A method of processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising the steps of:
executing said instructions using a plurality of functional units, said threads having a priority;
selecting instructions from said instruction stream based on said thread priority; and forwarding said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
executing said instructions using a plurality of functional units, said threads having a priority;
selecting instructions from said instruction stream based on said thread priority; and forwarding said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
10. The method of claim 9, wherein said thread priority allows different threads to have different priorities.
11. The method of claim 9, wherein said selection step selects said instructions for execution belonging to the thread with the highest priority.
12. A method of processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising the steps of:
executing said instructions using a plurality of functional units;
selecting instructions from said instruction stream based on resource availability; and forwarding said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
executing said instructions using a plurality of functional units;
selecting instructions from said instruction stream based on resource availability; and forwarding said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
13. The method of claim 12, wherein said resource availability allows said instructions to be allocated only if the resources required by the instructions are available for the next cycle.
14 14. The method of claim 12, wherein said resources comprise said functional units.
15. An article of manufacture for processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising:
a computer readable medium having computer readable program code means embodied thereon, said computer readable program code means comprising program code means for causing a computer to:
execute said instructions using a plurality of functional units, said threads having a priority;
select instructions from said instruction stream based on said thread priority; and forward said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
a computer readable medium having computer readable program code means embodied thereon, said computer readable program code means comprising program code means for causing a computer to:
execute said instructions using a plurality of functional units, said threads having a priority;
select instructions from said instruction stream based on said thread priority; and forward said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
16. An article of manufacture for processing instructions from an instruction stream having a plurality of threads in a multithreaded very large instruction word processor, comprising:
a computer readable medium having computer readable program code means embodied thereon, said computer readable program code means comprising program code means for causing a computer to:
execute said instructions using a plurality of functional units;
select instructions from said instruction stream based on resource availability; and forward said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
a computer readable medium having computer readable program code means embodied thereon, said computer readable program code means comprising program code means for causing a computer to:
execute said instructions using a plurality of functional units;
select instructions from said instruction stream based on resource availability; and forward said selected instructions to said plurality of functional units, wherein said functional units can be allocated independently to any thread in said multithreaded instruction stream.
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| US7096343B1 (en) | 2000-03-30 | 2006-08-22 | Agere Systems Inc. | Method and apparatus for splitting packets in multithreaded VLIW processor |
| AU2002241767A1 (en) * | 2000-10-23 | 2002-06-18 | Xyron Corporation | Concurrent-multitasking processor |
| US6934951B2 (en) * | 2002-01-17 | 2005-08-23 | Intel Corporation | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
| US7401208B2 (en) | 2003-04-25 | 2008-07-15 | International Business Machines Corporation | Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor |
| US7401207B2 (en) | 2003-04-25 | 2008-07-15 | International Business Machines Corporation | Apparatus and method for adjusting instruction thread priority in a multi-thread processor |
| US7360062B2 (en) | 2003-04-25 | 2008-04-15 | International Business Machines Corporation | Method and apparatus for selecting an instruction thread for processing in a multi-thread processor |
| GB0407384D0 (en) | 2004-03-31 | 2004-05-05 | Ignios Ltd | Resource management in a multicore processor |
| US8533716B2 (en) | 2004-03-31 | 2013-09-10 | Synopsys, Inc. | Resource management in a multicore architecture |
| US7631130B2 (en) * | 2005-02-04 | 2009-12-08 | Mips Technologies, Inc | Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor |
| US7506140B2 (en) * | 2005-02-04 | 2009-03-17 | Mips Technologies, Inc. | Return data selector employing barrel-incrementer-based round-robin apparatus |
| US7613904B2 (en) * | 2005-02-04 | 2009-11-03 | Mips Technologies, Inc. | Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler |
| US7490230B2 (en) * | 2005-02-04 | 2009-02-10 | Mips Technologies, Inc. | Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor |
| US7681014B2 (en) * | 2005-02-04 | 2010-03-16 | Mips Technologies, Inc. | Multithreading instruction scheduler employing thread group priorities |
| US7657891B2 (en) | 2005-02-04 | 2010-02-02 | Mips Technologies, Inc. | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency |
| US7853777B2 (en) * | 2005-02-04 | 2010-12-14 | Mips Technologies, Inc. | Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions |
| US7752627B2 (en) | 2005-02-04 | 2010-07-06 | Mips Technologies, Inc. | Leaky-bucket thread scheduler in a multithreading microprocessor |
| US7657883B2 (en) * | 2005-02-04 | 2010-02-02 | Mips Technologies, Inc. | Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor |
| US7664936B2 (en) * | 2005-02-04 | 2010-02-16 | Mips Technologies, Inc. | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages |
| US7395414B2 (en) * | 2005-02-11 | 2008-07-01 | International Business Machines Corporation | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions |
| US7254697B2 (en) * | 2005-02-11 | 2007-08-07 | International Business Machines Corporation | Method and apparatus for dynamic modification of microprocessor instruction group at dispatch |
| US7760748B2 (en) * | 2006-09-16 | 2010-07-20 | Mips Technologies, Inc. | Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch |
| US7773621B2 (en) * | 2006-09-16 | 2010-08-10 | Mips Technologies, Inc. | Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch |
| US7961745B2 (en) * | 2006-09-16 | 2011-06-14 | Mips Technologies, Inc. | Bifurcated transaction selector supporting dynamic priorities in multi-port switch |
| US7990989B2 (en) * | 2006-09-16 | 2011-08-02 | Mips Technologies, Inc. | Transaction selector employing transaction queue group priorities in multi-port switch |
| GB2466984B (en) | 2009-01-16 | 2011-07-27 | Imagination Tech Ltd | Multi-threaded data processing system |
| CN101901130B (en) * | 2010-07-26 | 2014-01-08 | 清华大学 | Instruction distributing and instruction decode preprocessing device |
| KR102177871B1 (en) * | 2013-12-20 | 2020-11-12 | 삼성전자주식회사 | Function unit for supporting multithreading, processor comprising the same, and operating method thereof |
| CN106030519A (en) * | 2014-03-27 | 2016-10-12 | 英特尔公司 | Processor logic and method for dispatching instructions from multiple strands |
| US11068274B2 (en) * | 2017-12-15 | 2021-07-20 | International Business Machines Corporation | Prioritized instructions in an instruction completion table of a simultaneous multithreading processor |
| CN109491798A (en) * | 2018-11-27 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of method and device of resource allocation |
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| WO1994027216A1 (en) * | 1993-05-14 | 1994-11-24 | Massachusetts Institute Of Technology | Multiprocessor coupling system with integrated compile and run time scheduling for parallelism |
| JPH09265397A (en) * | 1996-03-29 | 1997-10-07 | Hitachi Ltd | Processor for vliw instruction |
| JP3745450B2 (en) * | 1996-05-13 | 2006-02-15 | 株式会社ルネサステクノロジ | Parallel processor |
| CN1147785C (en) | 1996-08-27 | 2004-04-28 | 松下电器产业株式会社 | Multi-program-flow synchronous processor independently processing multiple instruction stream, soft controlling processing function of every instrunetion |
| US5890009A (en) * | 1996-12-12 | 1999-03-30 | International Business Machines Corporation | VLIW architecture and method for expanding a parcel |
| US6170051B1 (en) * | 1997-08-01 | 2001-01-02 | Micron Technology, Inc. | Apparatus and method for program level parallelism in a VLIW processor |
| KR100280460B1 (en) * | 1998-04-08 | 2001-02-01 | 김영환 | Data processing device and its multiple thread processing method |
| US6317820B1 (en) * | 1998-06-05 | 2001-11-13 | Texas Instruments Incorporated | Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism |
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