CA2344791A1 - Programming flash memory analog storage using coarse-and-fine sequence - Google Patents
Programming flash memory analog storage using coarse-and-fine sequence Download PDFInfo
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- CA2344791A1 CA2344791A1 CA002344791A CA2344791A CA2344791A1 CA 2344791 A1 CA2344791 A1 CA 2344791A1 CA 002344791 A CA002344791 A CA 002344791A CA 2344791 A CA2344791 A CA 2344791A CA 2344791 A1 CA2344791 A1 CA 2344791A1
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- flash memory
- memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
Abstract
The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
Description
BACKGROUND
1. Field of the Invention This invention relates to analog storage. In particular, the invention relates to analog non-volatile flash memory..
~ 2. Description of Related Art Analog storage has been used in a number of recording and playback applications. For example, U.S. Patent No. 5,220,531 issued to Blyth and Simko describes an analog storage scheme using electrically erasable programmable read only memory (EEPROM).
Such an analog storage typically has memory cells using floating gate technology. A
memory cell of a floating gate device has a source, a drain, a gate, and a floating gate. The threshold between the gate and the source is determined or controlled by the charge on the floating gate. These memory cells are erased using Fowler-Nordheim tunneling by applying a high voltage, e.g., 21 Volts, on the gate, zero volt on the source, and zero volt on the drain. The memory cells are programmed using the same Fowler-Nordheim tunneling mechanism by applying a high voltage (e.g., 9 to 19 volts) on the drain, zero volts on the gate, and 6 volts on the source.
Existing techniques for programming analog storage cells have a number of drawbacks.
First, the programming is slow because the iterative sequence uses constant program pulses having constant programming voltage. To achieve high accuracy, the programming voltage step size has to be sufficiently small. Iterative programming the memory cells using small programming voltage step size requires a large number of steps, resulting in slow programming time. Second, the programming is used for EEPROM memory cells, and therefore is not applicable for flash memory cells which have different programming requirements.
042236.P057 1 Patent Application RWB%TVNird Therefore, there is a need to have an efficient and accurate technique to program flash memory cells.
042236.P057 2 Patent Application RWB/TVN/rd SUMMARY
The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
In one embodiment, a counter determines number of program pulses applied to the flash memory cell. The programming circuit terminates programming the flash memory cell when the number of program pulses reaches a predetermined maximum count. The first comparison result indicates if the read cell voltage is greater than the input voltage by a predetermined amount. The second comparison result indicates if the read cell voltage is greater than the input voltage. The programming circuit terminates programming the flash memory cell when the read cell voltage is less than the input voltage according to the second comparison result.
042236.P057 3 Patent Application RWBlTVN/rd BRIEF DESCRIPTI01~1 OF THE DRAWI1~1GS
The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which:
Figure 1 is a diagram illustrating a circuit according to one embodiment of the invention.
Figure 2 is a diagram illustrating a flash memory cell having program and read circuits according to one embodiment of the invention.
Figure 3 is a flowchart illustrating a process to program a flash memory cell according to one embodiment of the invention.
20 Figure 4 is a flowchart illustrating a process to program and update according to one embodiment of the invention.
Figure 5 is a diagram illustrating a coarse and fine program curve according to one embodiment of the invention.
042236.P057 4 Patent Application RWB/TVN/rd DESCRIPTION
The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
In one embodiment, a counter determines number of program pulses applied to the flash memory cell. The programming circuit terminates programming the flash memory cell when the number of program pulses reaches a predetermined maximum count. The first comparison result indicates if the read cell voltage is greater than the input voltage by a predetermined amount. The second comparison result indicates if the read cell voltage is greater than the input voltage. The programming circuit terminates programming the flash memory cell when the read cell voltage is less than the input voltage according to the second comparison result.
The first and second program pulses correspond to the coarse and fine program modes.
By selecting proper coarse and fine amplitudes, the programming is fast and accurate. The coarse mode allows the read cell voltage to quickly approach the input voltage. As the read cell voltage is close to the input voltage, the programming is switched to the fine mode with fine amplitudes. When the comparison indicates that the read cell voltage is less than the input voltage, the fine programming is terminated. Therefore, the read cell voltage differs the input voltage by at most the fine program amplitude.
042236.P057 5 Patent Application R W B/T'VN/rd The coarse-and-fine programming technique is used to program flash memory cells in an analog storage array. Such an analog storage array is used in a number of applications including multi-level analog recording and playback systems.
In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention.
However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention.
Non-volatile memory cells used in analog storage for recording and playback applications typically includes a floating gate device having a source, a drain, a gate and a floating gate. The threshold of the device as measured between the gate and the source of the device is determined, or controlled, by the charge on the floating gate. These cells are erased using Fowler-Nordheim tunneling by applying a high voltage, e.g., 15V on the gate, zero volts on the source, and zero volts on the drain. The high voltage on the gate capacitively couples to the floating gate, which creates a high electric field through the tunnel oxide between the floating gate and the drain. This electric field causes electrons to tunnel to the floating gate, which effectively raises the Vt (threshold voltage) to about 6V. In the present invention, the cell is programmed using a source side injection mechanism.
The program pulse is divided into a series of coarse pulses and a series of fine pulses to store an analog signal in the non-volatile memory cell. After each programming pulse, the content of the cell is read using a read cycle and compared with the analog signal to be stored.
The coarse pulses terminate when the desired coarse programmed level is approached and the programming is then switched to the fine stage where fine pulses are provided.
The fine pulses terminate when the desired programmed level is reached.
042236.P057 6 Patent Application RWB/TVN/rd In the read mode, the storage cell is configured as a source follower with a constant load current from the source to ground. This results in a linear relationship between the threshold voltage of the cell and the cell readout voltage. The storage cell is operated in the saturation region.
Figure 1 is a diagram illustrating a circuit 100 according to one embodiment of the invention. The circuit 100 includes a program circuit 110, a flash memory cell I 20, a read circuit 130, a comparator 140, a counter 150, and a timing and control circuit 160. The circuit I00 programs the flash memory cell 120 by writing a cell voltage as close to the input voltage as possible to the flash memory cell.
The program circuit 110 generates programming pulses to the memory cell 120 during programming. The program circuit 110 generates coarse and fine pulses having coarse and fine amplitudes, respectively, using comparison results provided by the comparator 140.
Coarse and fine amplitudes may correspond to voltage step size, current magnitude, or programming time magnitude. For example, when a memory cell is programmed, a program pulse is applied while the programming time is varied. A coarse amplitude may correspond to a large time step, and a fine amplitude may correspond to a small programming time. In one embodiment, the fine amplitude is less than the coarse amplitude. The program circuit 110 receives clocking signals and select signals to select the program pulse from the timing and control circuit 160.
The flash memory cell 120 is a memory cell in an analog memory array. The memory cell 120 is a floating-gate type having a source, a drain, a gate, and a floating gate.
The read circuit 130 reads the memory cell 120. In one embodiment, the read circuit 130 reads a cell voltage of the programmed or erased memory cell 120.
042236.P057 7 Patent Application RWB/TVN/rd The comparator 140 compares the cell voltage as read by the read circuit 130 with the input voltage and generate comparison results. There are two comparison results: a coarse result and a fine result. The coarse result corresponds to comparing the read cell voltage with the input voltage plus a pre-determined amount 0V. Typically, this predetermined amount 0V
is slightly more than the coarse amplitude. The fine result corresponds to comparing the read cell voltage with the input voltage only. In one en$bodiment, the comparator 140 may be implemented as an operational amplifier having an offset that can be switched to ground or 0V.
In one embodiment of the present invention, the program circuit 110 generates the coarse pulse to program the memory cell 120 when the comparator 140 generates the coarse result indicating that the read cell voltage is greater than the input voltage plus OV. The program circuit 110 generates the fine pulse to program the memory cell 120 when the comparator 140 generates the fine result indicating that the read cell voltage is greater than the input voltage. In a coarse-to-fine process, the program circuit 110 starts generating program pulse. The program pulse is increasing and the source-follower voltage is gradually decreasing to the low voltage as the cell voltage approaches the input voltage.
The counter 150 keeps track of the number of programming pulses provided by the program circuit 110. Each time the program circuit generate a program pulse to the memory cell 120, the counter 150 is incremented by one. When the counter 150 reaches a predetermined maximum count NMAX, the programming is terminated.
The timing and control circuit 160 generates timing signals (e.g., clocks) and control signals (e.g., program pulse select signals, voltage source select signals) to various elements in the circuit. The timing and control circuit 160 may receive the comparison results from the comparator 140 to generate appropriate control signals to the program circuit 110.
042236.P057 8 Patent Application RWB/TVN/rd Figure 2 is a diagram illustrating a circuit including a flash memory cell and program and read circuits according to one embodiment of the invention. The circuit has a flash memory cell 210, voltage switches 220 and 230, a current switch 240, voltage sources VPDP
222, VPDR 224, VS~p 232, and Vscx 234, current sources IP 242 and IR 244.
The flash memory cell 210 has a paired drain D, a gate G, and a source S
terminals, or nodes, connected to the voltage source 220, the source-to-gate voltage source 230, and the current source 240, respectively. In a typical memory array having a plurality of memory cells arranged in a two-dimensional matrix with rows and columns, the gate G
terminal corresponds to a word line which is common to all bit cells in a row of the memory array, and the source S
terminal corresponds to a bit line which is common to all bit cells in a column of the memory array. The memory cell 210 can be in a program mode or read mode depending on the voltage levels at the voltage levels at the paired drain and word line terminals. The flash memory cell is programmed by applying a high voltage pulse VPDP 222 to the paired drain node, while the wordline node is supplied with a fixed voltage VS~P 232 and the bitline node is sourced by a current IP 242. The number of electrons on the floating gate will be increased due to source side injection and the floating gate voltage will drop. The absolute value change of the floating gate voltage depends on the programming time, the programming current IP 242 and the applied voltages VPDP 222 and Vs~p 232.
In the program mode, the voltage switches 220 and 230, and the current switch switch to connect the paired drain, the word line, and the bit line to the voltage source VpDP
222, the voltage source VS~P 232, and the current source IP 242, respectively.
In the read mode, the switches 220, 230, and 240 switch to connect the paired drain, the word line, and the bit line to the voltage source VPDR 224, the voltage source VSCR 234, and the current source IR 244, respectively.
042236.P057 9 Patent Application RWBi'rVN/rd In one embodiment, the current Ip of the current source 242 is either a coarse or a fine current. During programming, the number of electrons on the floating gate is increased due to source side injection and the floating gate voltage drops. The absolute value change of the floating gate voltage depends on the programming time, the programming current Ip and the applied voltages Vsgp and Vpdp. In the read mode, the value of the floating gate voltage is indirectly measured through the source follower voltage Vsf at the bit line terminal.
Figure 3 is a flowchart illustrating a process 300 to program a flash memory cell according to one embodiment of the invention.
Upon START, the process 300 initializes the counter to zero and sets the program pulse to generate coarse amplitude (Block 310). Then the process 300 programs and updates the counter (Block 320). The details of block 320 is described in Figure 4. Next, the process 300 determines if the read cell voltage is greater than the input voltage plus a predetermined amount OV (Block 330). If so, the process 300 goes back to block 320 to continue to provide the coarse pulses. Otherwise, the coarse phase is completed and the process 300 enters the fine phase.
The process 300 sets the program pulse to generate fine amplitude (Block 340).
Then, the process 300 programs and updates the counter (Block 350). The details of block 350 is described in Figure 4. Next, the process 300 determines if the read cell voltage is greater than the input voltage (Block 360). If so, the process 300 returns to block 350 to continue the fine programming phase. Otherwise, the process 300 terminates the programming (Block 370) because the programmed cell voltage has reached close to the input voltage within the tolerance determined by the fine programming amplitude. Then, the process 300 is terminated.
Note that the above process describes a two-stage procedure, coarse and fine.
The procedure can be modified to have more than two stages. For example, a coarse, medium, and 042236.P057 10 Patent Application RWB%TVN/rd fine stage can be used with coarse amplitude, medium amplitude, and fine amplitude, respectively.
Figure 4 is a flowchart illustrating a process 320 or 350 to program and update according to one embodiment of the invention.
Upon START, the process 320/350 programs the flash memory cell (Block 410) by applying the proper voltages at the paired drain terminal of the memory cell.
This program voltage is either coarse or fine voltage. Then the process 320/350 determines if the counter has reached a predetermined maximum count NMAX (Block 420). If so, the process terminates the programming (Block 450) and is then terminated. Otherwise, the process 320/350 updates the counter by incrementing by one (Block 430). Next, the process 320/350 reads the programmed memory cell to provide a cell voltage (Block 440). Then, the process 320/350 is terminated.
Figure 5 is a diagram illustrating a coarse and fine program curve according to one embodiment of the invention. The vertical axis corresponds to the cell voltage Vsf as read by the read circuit. The horizontal axis corresponds to the program voltage or the time.
The program curve consists of two linear segments: a coarse segment AF and a fine segment FK corresponding to the coarse and fine stages. The coarse segment AF
consists of segments AB, BC, CD, and DF, each corresponding to the coarse program voltage OV~oa~e' The fine segment FK consists of segments FG, GH, HI, IJ, and JK, each corresponding to the fine program voltage ~V,;ne. The input voltage VIN intersects the fine segment FK at point P.
The predetermined voltage for comparison during the coarse programming is 0V.
This voltage OV is typically more than OV~oarse.
The programming starts from the high voltage and gradually goes down to the input voltage VIN. Initially, the programming starts at point A. The program pulse is set to result in 042236.P057 11 Patent Application RWB/TVN/rd a coarse amplitude at the coarse voltage ~V~oane- The coarse program sequence goes from A to B, then C, D, and F. Each time the programming goes toward the input voltage VIN, a comparison between the read cell voltage Vsf and the VIN+~V is made. If Vsf is greater than VIN+OV, the coarse programming continues. When it reaches F, the comparison indicates Vsf is less than VIN+OV, therefore, the programming is switched to the fine programming mode.
The program voltage is now set to result in a fine amplitude of fine voltage now OV,;ne and the Vsf goes down from F to G, then H, I, J, and K. Each time the programming goes toward the input voltage VIN, a comparison is made between the read cell voltage Vsf and VIN. If Vsf is greater than VIN, the fine programming continues. When it reaches K, the comparison indicates that Vsf is less than VIN, therefore, the programming is terminated.
Since the program voltage changes incrementally at ~V,;ne increments (or decrements), when the programming is terminated, the cell voltage Vsf differs at most the VIN by the fine voltage ~V,;ne. This fine voltage is carefully chosen so that the programmed cell voltage is very close to the input voltage VIN.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.
042236.P057 12 Patent Application RWB/TVN/rd
1. Field of the Invention This invention relates to analog storage. In particular, the invention relates to analog non-volatile flash memory..
~ 2. Description of Related Art Analog storage has been used in a number of recording and playback applications. For example, U.S. Patent No. 5,220,531 issued to Blyth and Simko describes an analog storage scheme using electrically erasable programmable read only memory (EEPROM).
Such an analog storage typically has memory cells using floating gate technology. A
memory cell of a floating gate device has a source, a drain, a gate, and a floating gate. The threshold between the gate and the source is determined or controlled by the charge on the floating gate. These memory cells are erased using Fowler-Nordheim tunneling by applying a high voltage, e.g., 21 Volts, on the gate, zero volt on the source, and zero volt on the drain. The memory cells are programmed using the same Fowler-Nordheim tunneling mechanism by applying a high voltage (e.g., 9 to 19 volts) on the drain, zero volts on the gate, and 6 volts on the source.
Existing techniques for programming analog storage cells have a number of drawbacks.
First, the programming is slow because the iterative sequence uses constant program pulses having constant programming voltage. To achieve high accuracy, the programming voltage step size has to be sufficiently small. Iterative programming the memory cells using small programming voltage step size requires a large number of steps, resulting in slow programming time. Second, the programming is used for EEPROM memory cells, and therefore is not applicable for flash memory cells which have different programming requirements.
042236.P057 1 Patent Application RWB%TVNird Therefore, there is a need to have an efficient and accurate technique to program flash memory cells.
042236.P057 2 Patent Application RWB/TVN/rd SUMMARY
The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
In one embodiment, a counter determines number of program pulses applied to the flash memory cell. The programming circuit terminates programming the flash memory cell when the number of program pulses reaches a predetermined maximum count. The first comparison result indicates if the read cell voltage is greater than the input voltage by a predetermined amount. The second comparison result indicates if the read cell voltage is greater than the input voltage. The programming circuit terminates programming the flash memory cell when the read cell voltage is less than the input voltage according to the second comparison result.
042236.P057 3 Patent Application RWBlTVN/rd BRIEF DESCRIPTI01~1 OF THE DRAWI1~1GS
The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which:
Figure 1 is a diagram illustrating a circuit according to one embodiment of the invention.
Figure 2 is a diagram illustrating a flash memory cell having program and read circuits according to one embodiment of the invention.
Figure 3 is a flowchart illustrating a process to program a flash memory cell according to one embodiment of the invention.
20 Figure 4 is a flowchart illustrating a process to program and update according to one embodiment of the invention.
Figure 5 is a diagram illustrating a coarse and fine program curve according to one embodiment of the invention.
042236.P057 4 Patent Application RWB/TVN/rd DESCRIPTION
The present invention is a method and apparatus to program a flash memory cell in an analog storage array. A read circuit reads a cell voltage of a flash memory cell. A comparator compares the read cell voltage with an input voltage representing an analog signal. The comparator generates first and second comparison results. A programming circuit generates a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result. The programming circuit generates a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
In one embodiment, a counter determines number of program pulses applied to the flash memory cell. The programming circuit terminates programming the flash memory cell when the number of program pulses reaches a predetermined maximum count. The first comparison result indicates if the read cell voltage is greater than the input voltage by a predetermined amount. The second comparison result indicates if the read cell voltage is greater than the input voltage. The programming circuit terminates programming the flash memory cell when the read cell voltage is less than the input voltage according to the second comparison result.
The first and second program pulses correspond to the coarse and fine program modes.
By selecting proper coarse and fine amplitudes, the programming is fast and accurate. The coarse mode allows the read cell voltage to quickly approach the input voltage. As the read cell voltage is close to the input voltage, the programming is switched to the fine mode with fine amplitudes. When the comparison indicates that the read cell voltage is less than the input voltage, the fine programming is terminated. Therefore, the read cell voltage differs the input voltage by at most the fine program amplitude.
042236.P057 5 Patent Application R W B/T'VN/rd The coarse-and-fine programming technique is used to program flash memory cells in an analog storage array. Such an analog storage array is used in a number of applications including multi-level analog recording and playback systems.
In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention.
However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention.
Non-volatile memory cells used in analog storage for recording and playback applications typically includes a floating gate device having a source, a drain, a gate and a floating gate. The threshold of the device as measured between the gate and the source of the device is determined, or controlled, by the charge on the floating gate. These cells are erased using Fowler-Nordheim tunneling by applying a high voltage, e.g., 15V on the gate, zero volts on the source, and zero volts on the drain. The high voltage on the gate capacitively couples to the floating gate, which creates a high electric field through the tunnel oxide between the floating gate and the drain. This electric field causes electrons to tunnel to the floating gate, which effectively raises the Vt (threshold voltage) to about 6V. In the present invention, the cell is programmed using a source side injection mechanism.
The program pulse is divided into a series of coarse pulses and a series of fine pulses to store an analog signal in the non-volatile memory cell. After each programming pulse, the content of the cell is read using a read cycle and compared with the analog signal to be stored.
The coarse pulses terminate when the desired coarse programmed level is approached and the programming is then switched to the fine stage where fine pulses are provided.
The fine pulses terminate when the desired programmed level is reached.
042236.P057 6 Patent Application RWB/TVN/rd In the read mode, the storage cell is configured as a source follower with a constant load current from the source to ground. This results in a linear relationship between the threshold voltage of the cell and the cell readout voltage. The storage cell is operated in the saturation region.
Figure 1 is a diagram illustrating a circuit 100 according to one embodiment of the invention. The circuit 100 includes a program circuit 110, a flash memory cell I 20, a read circuit 130, a comparator 140, a counter 150, and a timing and control circuit 160. The circuit I00 programs the flash memory cell 120 by writing a cell voltage as close to the input voltage as possible to the flash memory cell.
The program circuit 110 generates programming pulses to the memory cell 120 during programming. The program circuit 110 generates coarse and fine pulses having coarse and fine amplitudes, respectively, using comparison results provided by the comparator 140.
Coarse and fine amplitudes may correspond to voltage step size, current magnitude, or programming time magnitude. For example, when a memory cell is programmed, a program pulse is applied while the programming time is varied. A coarse amplitude may correspond to a large time step, and a fine amplitude may correspond to a small programming time. In one embodiment, the fine amplitude is less than the coarse amplitude. The program circuit 110 receives clocking signals and select signals to select the program pulse from the timing and control circuit 160.
The flash memory cell 120 is a memory cell in an analog memory array. The memory cell 120 is a floating-gate type having a source, a drain, a gate, and a floating gate.
The read circuit 130 reads the memory cell 120. In one embodiment, the read circuit 130 reads a cell voltage of the programmed or erased memory cell 120.
042236.P057 7 Patent Application RWB/TVN/rd The comparator 140 compares the cell voltage as read by the read circuit 130 with the input voltage and generate comparison results. There are two comparison results: a coarse result and a fine result. The coarse result corresponds to comparing the read cell voltage with the input voltage plus a pre-determined amount 0V. Typically, this predetermined amount 0V
is slightly more than the coarse amplitude. The fine result corresponds to comparing the read cell voltage with the input voltage only. In one en$bodiment, the comparator 140 may be implemented as an operational amplifier having an offset that can be switched to ground or 0V.
In one embodiment of the present invention, the program circuit 110 generates the coarse pulse to program the memory cell 120 when the comparator 140 generates the coarse result indicating that the read cell voltage is greater than the input voltage plus OV. The program circuit 110 generates the fine pulse to program the memory cell 120 when the comparator 140 generates the fine result indicating that the read cell voltage is greater than the input voltage. In a coarse-to-fine process, the program circuit 110 starts generating program pulse. The program pulse is increasing and the source-follower voltage is gradually decreasing to the low voltage as the cell voltage approaches the input voltage.
The counter 150 keeps track of the number of programming pulses provided by the program circuit 110. Each time the program circuit generate a program pulse to the memory cell 120, the counter 150 is incremented by one. When the counter 150 reaches a predetermined maximum count NMAX, the programming is terminated.
The timing and control circuit 160 generates timing signals (e.g., clocks) and control signals (e.g., program pulse select signals, voltage source select signals) to various elements in the circuit. The timing and control circuit 160 may receive the comparison results from the comparator 140 to generate appropriate control signals to the program circuit 110.
042236.P057 8 Patent Application RWB/TVN/rd Figure 2 is a diagram illustrating a circuit including a flash memory cell and program and read circuits according to one embodiment of the invention. The circuit has a flash memory cell 210, voltage switches 220 and 230, a current switch 240, voltage sources VPDP
222, VPDR 224, VS~p 232, and Vscx 234, current sources IP 242 and IR 244.
The flash memory cell 210 has a paired drain D, a gate G, and a source S
terminals, or nodes, connected to the voltage source 220, the source-to-gate voltage source 230, and the current source 240, respectively. In a typical memory array having a plurality of memory cells arranged in a two-dimensional matrix with rows and columns, the gate G
terminal corresponds to a word line which is common to all bit cells in a row of the memory array, and the source S
terminal corresponds to a bit line which is common to all bit cells in a column of the memory array. The memory cell 210 can be in a program mode or read mode depending on the voltage levels at the voltage levels at the paired drain and word line terminals. The flash memory cell is programmed by applying a high voltage pulse VPDP 222 to the paired drain node, while the wordline node is supplied with a fixed voltage VS~P 232 and the bitline node is sourced by a current IP 242. The number of electrons on the floating gate will be increased due to source side injection and the floating gate voltage will drop. The absolute value change of the floating gate voltage depends on the programming time, the programming current IP 242 and the applied voltages VPDP 222 and Vs~p 232.
In the program mode, the voltage switches 220 and 230, and the current switch switch to connect the paired drain, the word line, and the bit line to the voltage source VpDP
222, the voltage source VS~P 232, and the current source IP 242, respectively.
In the read mode, the switches 220, 230, and 240 switch to connect the paired drain, the word line, and the bit line to the voltage source VPDR 224, the voltage source VSCR 234, and the current source IR 244, respectively.
042236.P057 9 Patent Application RWBi'rVN/rd In one embodiment, the current Ip of the current source 242 is either a coarse or a fine current. During programming, the number of electrons on the floating gate is increased due to source side injection and the floating gate voltage drops. The absolute value change of the floating gate voltage depends on the programming time, the programming current Ip and the applied voltages Vsgp and Vpdp. In the read mode, the value of the floating gate voltage is indirectly measured through the source follower voltage Vsf at the bit line terminal.
Figure 3 is a flowchart illustrating a process 300 to program a flash memory cell according to one embodiment of the invention.
Upon START, the process 300 initializes the counter to zero and sets the program pulse to generate coarse amplitude (Block 310). Then the process 300 programs and updates the counter (Block 320). The details of block 320 is described in Figure 4. Next, the process 300 determines if the read cell voltage is greater than the input voltage plus a predetermined amount OV (Block 330). If so, the process 300 goes back to block 320 to continue to provide the coarse pulses. Otherwise, the coarse phase is completed and the process 300 enters the fine phase.
The process 300 sets the program pulse to generate fine amplitude (Block 340).
Then, the process 300 programs and updates the counter (Block 350). The details of block 350 is described in Figure 4. Next, the process 300 determines if the read cell voltage is greater than the input voltage (Block 360). If so, the process 300 returns to block 350 to continue the fine programming phase. Otherwise, the process 300 terminates the programming (Block 370) because the programmed cell voltage has reached close to the input voltage within the tolerance determined by the fine programming amplitude. Then, the process 300 is terminated.
Note that the above process describes a two-stage procedure, coarse and fine.
The procedure can be modified to have more than two stages. For example, a coarse, medium, and 042236.P057 10 Patent Application RWB%TVN/rd fine stage can be used with coarse amplitude, medium amplitude, and fine amplitude, respectively.
Figure 4 is a flowchart illustrating a process 320 or 350 to program and update according to one embodiment of the invention.
Upon START, the process 320/350 programs the flash memory cell (Block 410) by applying the proper voltages at the paired drain terminal of the memory cell.
This program voltage is either coarse or fine voltage. Then the process 320/350 determines if the counter has reached a predetermined maximum count NMAX (Block 420). If so, the process terminates the programming (Block 450) and is then terminated. Otherwise, the process 320/350 updates the counter by incrementing by one (Block 430). Next, the process 320/350 reads the programmed memory cell to provide a cell voltage (Block 440). Then, the process 320/350 is terminated.
Figure 5 is a diagram illustrating a coarse and fine program curve according to one embodiment of the invention. The vertical axis corresponds to the cell voltage Vsf as read by the read circuit. The horizontal axis corresponds to the program voltage or the time.
The program curve consists of two linear segments: a coarse segment AF and a fine segment FK corresponding to the coarse and fine stages. The coarse segment AF
consists of segments AB, BC, CD, and DF, each corresponding to the coarse program voltage OV~oa~e' The fine segment FK consists of segments FG, GH, HI, IJ, and JK, each corresponding to the fine program voltage ~V,;ne. The input voltage VIN intersects the fine segment FK at point P.
The predetermined voltage for comparison during the coarse programming is 0V.
This voltage OV is typically more than OV~oarse.
The programming starts from the high voltage and gradually goes down to the input voltage VIN. Initially, the programming starts at point A. The program pulse is set to result in 042236.P057 11 Patent Application RWB/TVN/rd a coarse amplitude at the coarse voltage ~V~oane- The coarse program sequence goes from A to B, then C, D, and F. Each time the programming goes toward the input voltage VIN, a comparison between the read cell voltage Vsf and the VIN+~V is made. If Vsf is greater than VIN+OV, the coarse programming continues. When it reaches F, the comparison indicates Vsf is less than VIN+OV, therefore, the programming is switched to the fine programming mode.
The program voltage is now set to result in a fine amplitude of fine voltage now OV,;ne and the Vsf goes down from F to G, then H, I, J, and K. Each time the programming goes toward the input voltage VIN, a comparison is made between the read cell voltage Vsf and VIN. If Vsf is greater than VIN, the fine programming continues. When it reaches K, the comparison indicates that Vsf is less than VIN, therefore, the programming is terminated.
Since the program voltage changes incrementally at ~V,;ne increments (or decrements), when the programming is terminated, the cell voltage Vsf differs at most the VIN by the fine voltage ~V,;ne. This fine voltage is carefully chosen so that the programmed cell voltage is very close to the input voltage VIN.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.
042236.P057 12 Patent Application RWB/TVN/rd
Claims (18)
1. An apparatus comprising:
a read circuit to read a cell voltage of a flash memory cell;
a comparator coupled to the flash memory cell to compare the read cell voltage with an input voltage representing an analog signal, the comparator generating first and second comparison results;
a programming circuit to generate a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result, the programming circuit generating a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
a read circuit to read a cell voltage of a flash memory cell;
a comparator coupled to the flash memory cell to compare the read cell voltage with an input voltage representing an analog signal, the comparator generating first and second comparison results;
a programming circuit to generate a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result, the programming circuit generating a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
2. The apparatus of claim 1 further comprising:
a counter to determine number of program pulses applied to the flash memory cell.
a counter to determine number of program pulses applied to the flash memory cell.
3. The apparatus of claim 2 wherein the programming circuit terminates programming the flash memory cell when the number of program pulses reaches a predetermined maximum count.
4. The apparatus of claim 1 wherein the first comparison result indicates if the read cell voltage is greater than the input voltage by a predetermined amount.
5. The apparatus of claim 4 wherein the second comparison result indicates if the read cell voltage is greater than the input voltage.
6. The apparatus of claim 5 wherein the programming circuit terminates programming the flash memory cell when the read cell voltage is less than the input voltage according to the second comparison result.
7. A method comprising:
reading a cell voltage of a flash memory cell;
comparing the read cell voltage with an input voltage representing an analog signal to generate first and second comparison results;
generating a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result; and generating a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
reading a cell voltage of a flash memory cell;
comparing the read cell voltage with an input voltage representing an analog signal to generate first and second comparison results;
generating a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result; and generating a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
8. The method of claim 7 further comprising:
determining number of program pulses applied to the flash memory cell.
determining number of program pulses applied to the flash memory cell.
9. The method of claim 8 further comprising terminating programming the flash memory cell when the number of program pulses reaches a predetermined maximum count.
10. The method of claim 7 wherein the first comparison result indicates if the read cell voltage is greater than the input voltage by a predetermined amount.
11. The method of claim 10 wherein the second comparison result indicates if the read cell voltage is greater than the input voltage.
12. The method of claim 11 further comprising terminating programming the flash memory cell when the read cell voltage is less than the input voltage according to the second comparison result.
13. A system comprising:
a flash memory cell to store an input voltage representing an analog signal;
a circuit coupled to the flash memory cell comprising:
a read circuit to read a cell voltage of a flash memory cell, a comparator coupled to the flash memory cell to compare the read cell voltage with an input voltage representing an analog signal, the comparator generating first and second comparison results, and a programming circuit to generate a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result, the programming circuit generating a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
a flash memory cell to store an input voltage representing an analog signal;
a circuit coupled to the flash memory cell comprising:
a read circuit to read a cell voltage of a flash memory cell, a comparator coupled to the flash memory cell to compare the read cell voltage with an input voltage representing an analog signal, the comparator generating first and second comparison results, and a programming circuit to generate a first program pulse corresponding to a first amplitude to iteratively program the flash memory cell based on the first comparison result, the programming circuit generating a second program pulse corresponding to a second amplitude less than the first amplitude to iteratively program the flash memory cell based on the first and second comparison results.
14. The system of claim 13 wherein the circuit further comprises:
a counter to determine number of program pulses applied to the flash memory cell.
a counter to determine number of program pulses applied to the flash memory cell.
15. The system of claim 14 wherein the programming circuit terminates programming the flash memory cell when the number of program pulses reaches a predetermined maximum count.
16. The system of claim 13 wherein the first comparison result indicates if the read cell voltage is greater than the input voltage by a predetermined amount.
17. The system of claim 15 wherein the second comparison result indicates if the read cell voltage is greater than the input voltage.
18. The system of claim 17 wherein the programming circuit terminates programming the flash memory cell when the read cell voltage is less than the input voltage according to the second comparison result.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/558,432 | 2000-04-25 | ||
| US09/558,432 US6301161B1 (en) | 2000-04-25 | 2000-04-25 | Programming flash memory analog storage using coarse-and-fine sequence |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2344791A1 true CA2344791A1 (en) | 2001-10-25 |
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|---|---|---|---|
| CA002344791A Abandoned CA2344791A1 (en) | 2000-04-25 | 2001-04-24 | Programming flash memory analog storage using coarse-and-fine sequence |
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| US (1) | US6301161B1 (en) |
| EP (1) | EP1154439A1 (en) |
| JP (1) | JP2001357693A (en) |
| KR (1) | KR20010098827A (en) |
| CA (1) | CA2344791A1 (en) |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6738289B2 (en) * | 2001-02-26 | 2004-05-18 | Sandisk Corporation | Non-volatile memory with improved programming and method therefor |
| US7630237B2 (en) * | 2003-02-06 | 2009-12-08 | Sandisk Corporation | System and method for programming cells in non-volatile integrated memory devices |
| US7177199B2 (en) * | 2003-10-20 | 2007-02-13 | Sandisk Corporation | Behavior based programming of non-volatile memory |
| US6888758B1 (en) * | 2004-01-21 | 2005-05-03 | Sandisk Corporation | Programming non-volatile memory |
| US7068539B2 (en) * | 2004-01-27 | 2006-06-27 | Sandisk Corporation | Charge packet metering for coarse/fine programming of non-volatile memory |
| US7139198B2 (en) * | 2004-01-27 | 2006-11-21 | Sandisk Corporation | Efficient verification for coarse/fine programming of non-volatile memory |
| US7002843B2 (en) * | 2004-01-27 | 2006-02-21 | Sandisk Corporation | Variable current sinking for coarse/fine programming of non-volatile memory |
| JP2005235287A (en) | 2004-02-19 | 2005-09-02 | Nec Electronics Corp | Programming method and device for nonvolatile semiconductor memory, and nonvolatile semiconductor memory |
| US7023733B2 (en) * | 2004-05-05 | 2006-04-04 | Sandisk Corporation | Boosting to control programming of non-volatile memory |
| ATE516584T1 (en) * | 2004-05-05 | 2011-07-15 | Sandisk Corp | BITLINE GOVERNED APPROACH TO PROGRAM CONTROLLING NON-VOLATILE MEMORY |
| US7020026B2 (en) * | 2004-05-05 | 2006-03-28 | Sandisk Corporation | Bitline governed approach for program control of non-volatile memory |
| US7092290B2 (en) * | 2004-11-16 | 2006-08-15 | Sandisk Corporation | High speed programming system with reduced over programming |
| US7173859B2 (en) * | 2004-11-16 | 2007-02-06 | Sandisk Corporation | Faster programming of higher level states in multi-level cell flash memory |
| US7339834B2 (en) * | 2005-06-03 | 2008-03-04 | Sandisk Corporation | Starting program voltage shift with cycling of non-volatile memory |
| US7656710B1 (en) | 2005-07-14 | 2010-02-02 | Sau Ching Wong | Adaptive operations for nonvolatile memories |
| US7206235B1 (en) | 2005-10-14 | 2007-04-17 | Sandisk Corporation | Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling |
| US7286406B2 (en) * | 2005-10-14 | 2007-10-23 | Sandisk Corporation | Method for controlled programming of non-volatile memory exhibiting bit line coupling |
| KR101012130B1 (en) | 2006-04-12 | 2011-02-07 | 샌디스크 코포레이션 | Reducing the impact of program disturb during read |
| US7486561B2 (en) * | 2006-06-22 | 2009-02-03 | Sandisk Corporation | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| US7489549B2 (en) * | 2006-06-22 | 2009-02-10 | Sandisk Corporation | System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| US20070297247A1 (en) * | 2006-06-26 | 2007-12-27 | Gerrit Jan Hemink | Method for programming non-volatile memory using variable amplitude programming pulses |
| DE602007007480D1 (en) * | 2006-07-20 | 2010-08-12 | Sandisk Corp | FLOATING GATE MEMORY WITH COUPLING COMPENSATION DURING PROGRAMMING |
| US7443729B2 (en) * | 2006-07-20 | 2008-10-28 | Sandisk Corporation | System that compensates for coupling based on sensing a neighbor using coupling |
| US7506113B2 (en) * | 2006-07-20 | 2009-03-17 | Sandisk Corporation | Method for configuring compensation |
| US7885119B2 (en) * | 2006-07-20 | 2011-02-08 | Sandisk Corporation | Compensating for coupling during programming |
| US7522454B2 (en) * | 2006-07-20 | 2009-04-21 | Sandisk Corporation | Compensating for coupling based on sensing a neighbor using coupling |
| US7400535B2 (en) * | 2006-07-20 | 2008-07-15 | Sandisk Corporation | System that compensates for coupling during programming |
| US7495953B2 (en) * | 2006-07-20 | 2009-02-24 | Sandisk Corporation | System for configuring compensation |
| US7450426B2 (en) * | 2006-10-10 | 2008-11-11 | Sandisk Corporation | Systems utilizing variable program voltage increment values in non-volatile memory program operations |
| US7474561B2 (en) * | 2006-10-10 | 2009-01-06 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
| US7570520B2 (en) * | 2006-12-27 | 2009-08-04 | Sandisk Corporation | Non-volatile storage system with initial programming voltage based on trial |
| US7551482B2 (en) * | 2006-12-27 | 2009-06-23 | Sandisk Corporation | Method for programming with initial programming voltage based on trial |
| US7508715B2 (en) * | 2007-07-03 | 2009-03-24 | Sandisk Corporation | Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing |
| US7599224B2 (en) * | 2007-07-03 | 2009-10-06 | Sandisk Corporation | Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing |
| CN101354919B (en) * | 2007-07-27 | 2010-10-13 | 旺宏电子股份有限公司 | Method for programming multi-order unit memory |
| JP2009301679A (en) * | 2008-06-17 | 2009-12-24 | Vantel Corp | Nonvolatile semiconductor storage device and its data writing method |
| US8059447B2 (en) | 2008-06-27 | 2011-11-15 | Sandisk 3D Llc | Capacitive discharge method for writing to non-volatile memory |
| US8130528B2 (en) | 2008-08-25 | 2012-03-06 | Sandisk 3D Llc | Memory system with sectional data lines |
| JP2010079977A (en) * | 2008-09-25 | 2010-04-08 | Toppan Printing Co Ltd | Nonvolatile semiconductor memory device with constant current type power supply circuit |
| US8027209B2 (en) * | 2008-10-06 | 2011-09-27 | Sandisk 3D, Llc | Continuous programming of non-volatile memory |
| US8279650B2 (en) * | 2009-04-20 | 2012-10-02 | Sandisk 3D Llc | Memory system with data line switching scheme |
| US8861270B2 (en) | 2013-03-11 | 2014-10-14 | Microsoft Corporation | Approximate multi-level cell memory operations |
| JP6783666B2 (en) * | 2017-01-05 | 2020-11-11 | キオクシア株式会社 | Semiconductor storage and memory system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5220531A (en) | 1991-01-02 | 1993-06-15 | Information Storage Devices, Inc. | Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog signal recording and playback |
| US5218569A (en) * | 1991-02-08 | 1993-06-08 | Banks Gerald J | Electrically alterable non-volatile memory with n-bits per memory cell |
| US5623436A (en) * | 1993-06-17 | 1997-04-22 | Information Storage Devices | Method and apparatus for adjustment and control of an iterative method of recording analog signals with on-chip trimming techniques |
| US5926409A (en) * | 1997-09-05 | 1999-07-20 | Information Storage Devices, Inc. | Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application |
| US5903487A (en) * | 1997-11-25 | 1999-05-11 | Windbond Electronics Corporation | Memory device and method of operation |
| US6040993A (en) * | 1998-02-23 | 2000-03-21 | Macronix International Co., Ltd. | Method for programming an analog/multi-level flash EEPROM |
-
2000
- 2000-04-25 US US09/558,432 patent/US6301161B1/en not_active Expired - Fee Related
-
2001
- 2001-04-23 EP EP01303687A patent/EP1154439A1/en not_active Withdrawn
- 2001-04-24 CA CA002344791A patent/CA2344791A1/en not_active Abandoned
- 2001-04-24 KR KR1020010021975A patent/KR20010098827A/en not_active Application Discontinuation
- 2001-04-25 JP JP2001128249A patent/JP2001357693A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP1154439A1 (en) | 2001-11-14 |
| JP2001357693A (en) | 2001-12-26 |
| KR20010098827A (en) | 2001-11-08 |
| US6301161B1 (en) | 2001-10-09 |
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