CA2352206A1 - Component decoder and method thereof in mobile communication system - Google Patents

Component decoder and method thereof in mobile communication system Download PDF

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Publication number
CA2352206A1
CA2352206A1 CA002352206A CA2352206A CA2352206A1 CA 2352206 A1 CA2352206 A1 CA 2352206A1 CA 002352206 A CA002352206 A CA 002352206A CA 2352206 A CA2352206 A CA 2352206A CA 2352206 A1 CA2352206 A1 CA 2352206A1
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Canada
Prior art keywords
llr
path
pes
cells
time
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CA002352206A
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French (fr)
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CA2352206C (en
Inventor
Min-Goo Kim
Beong-Jo Kim
Young-Hwan Lee
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Samsung Electronics Co Ltd
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Individual
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Publication of CA2352206A1 publication Critical patent/CA2352206A1/en
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Publication of CA2352206C publication Critical patent/CA2352206C/en
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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • H04L1/0054Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4138Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
    • H03M13/4146Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path, i.e. "SOVA" decoding
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4184Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using register-exchange
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6577Representation or format of variables, register sizes or word-lengths and quantization
    • H03M13/6583Normalization other than scaling, e.g. by subtraction
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • H04L1/0052Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957Turbo codes and decoding

Abstract

There is provided a decoder and a decoding method for decoding data modulate d with a recursive systematic convolutional code (RSC) in a mobile communicati on system. In the decoder, a branch metric calculating circuit (BMC) calculates branch metrics (BMs) associated with a plurality of input symbols. An add- compare-select circuit (ACS) receives the BMs and previous path metrics (PMs ) and generates a plurality of path selectors and LLR (Log Likelihood Ratio) data including the plurality of path selectors and reliability information a t a first time instant. A maximum likelihood (ML) state searcher has a plurali ty of cells in an array with rows and columns, connected to one another accordi ng to an encoder trellis, cells in each row having a process time, Ds, for outputting the same value of the cells in the last column as an ML state val ue representing an ML path in response to the path selectors. A delay delays th e LLR data received from the ACS by the time Ds. An LLR update circuit has a plurality of processing elements (PEs) in an array with rows and columns, connected according to the encoder trellis, PEs in each row having a process time, DL, for generating updated LLR values from the PEs at a time instant (first time instant - approximately Ds+DL) in response to the delayed LLR da ta received from the delay. A selector selects one of the updated LLR values based on the ML state value.
CA002352206A 1999-10-05 2000-10-05 Component decoder and method thereof in mobile communication system Expired - Fee Related CA2352206C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
KR19990042924 1999-10-05
KR1999/42924 1999-10-05
KR1999/43118 1999-10-06
KR19990043118 1999-10-06
PCT/KR2000/001109 WO2001026257A1 (en) 1999-10-05 2000-10-05 Component decoder and method thereof in mobile communication system

Publications (2)

Publication Number Publication Date
CA2352206A1 true CA2352206A1 (en) 2001-04-12
CA2352206C CA2352206C (en) 2005-12-06

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Family Applications (1)

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CA002352206A Expired - Fee Related CA2352206C (en) 1999-10-05 2000-10-05 Component decoder and method thereof in mobile communication system

Country Status (14)

Country Link
US (1) US6697443B1 (en)
EP (1) EP1135877B1 (en)
JP (1) JP3640924B2 (en)
KR (1) KR100350502B1 (en)
CN (1) CN1168237C (en)
AT (1) ATE385629T1 (en)
AU (1) AU762877B2 (en)
BR (1) BR0007197A (en)
CA (1) CA2352206C (en)
DE (1) DE60037963T2 (en)
DK (1) DK1135877T3 (en)
ES (1) ES2301492T3 (en)
IL (2) IL143337A0 (en)
WO (1) WO2001026257A1 (en)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020110206A1 (en) * 1998-11-12 2002-08-15 Neal Becker Combined interference cancellation with FEC decoding for high spectral efficiency satellite communications
US6865710B2 (en) 2000-09-18 2005-03-08 Lucent Technologies Inc. Butterfly processor for telecommunications
US7020214B2 (en) 2000-09-18 2006-03-28 Lucent Technologies Inc. Method and apparatus for path metric processing in telecommunications systems
US7127664B2 (en) * 2000-09-18 2006-10-24 Lucent Technologies Inc. Reconfigurable architecture for decoding telecommunications signals
EP1220455A1 (en) * 2000-12-29 2002-07-03 Motorola, Inc. Viterbi decoder, method and unit therefor
US20030067998A1 (en) * 2001-07-19 2003-04-10 Matsushita Electric Industrial Co., Ltd. Method for evaluating the quality of read signal and apparatus for reading information
KR100487183B1 (en) * 2002-07-19 2005-05-03 삼성전자주식회사 Decoding apparatus and method of turbo code
US7173985B1 (en) * 2002-08-05 2007-02-06 Altera Corporation Method and apparatus for implementing a Viterbi decoder
KR100515472B1 (en) * 2002-10-15 2005-09-16 브이케이 주식회사 Channel coding and decoding method and multiple-antenna communication systems performing the same
US7797618B2 (en) * 2004-12-30 2010-09-14 Freescale Semiconductor, Inc. Parallel decoder for ultrawide bandwidth receiver
JP4432781B2 (en) * 2005-01-17 2010-03-17 株式会社日立製作所 Error correction decoder
US7571369B2 (en) * 2005-02-17 2009-08-04 Samsung Electronics Co., Ltd. Turbo decoder architecture for use in software-defined radio systems
US7603613B2 (en) * 2005-02-17 2009-10-13 Samsung Electronics Co., Ltd. Viterbi decoder architecture for use in software-defined radio systems
KR100800853B1 (en) * 2005-06-09 2008-02-04 삼성전자주식회사 Apparatus and method for receiving signal in a communication system
US20070006058A1 (en) * 2005-06-30 2007-01-04 Seagate Technology Llc Path metric computation unit for use in a data detector
US7764741B2 (en) * 2005-07-28 2010-07-27 Broadcom Corporation Modulation-type discrimination in a wireless communication network
US7860194B2 (en) * 2005-11-11 2010-12-28 Samsung Electronics Co., Ltd. Method and apparatus for normalizing input metric to a channel decoder in a wireless communication system
US20070268988A1 (en) * 2006-05-19 2007-11-22 Navini Networks, Inc. Method and system for optimal receive diversity combining
US7925964B2 (en) * 2006-12-22 2011-04-12 Intel Corporation High-throughput memory-efficient BI-SOVA decoder architecture
US7721187B2 (en) * 2007-09-04 2010-05-18 Broadcom Corporation ACS (add compare select) implementation for radix-4 SOVA (soft-output viterbi algorithm)
US8238475B2 (en) 2007-10-30 2012-08-07 Qualcomm Incorporated Methods and systems for PDCCH blind decoding in mobile communications
US20090132894A1 (en) * 2007-11-19 2009-05-21 Seagate Technology Llc Soft Output Bit Threshold Error Correction
US8127216B2 (en) 2007-11-19 2012-02-28 Seagate Technology Llc Reduced state soft output processing
US8401115B2 (en) * 2008-03-11 2013-03-19 Xilinx, Inc. Detector using limited symbol candidate generation for MIMO communication systems
US8413031B2 (en) * 2008-12-16 2013-04-02 Lsi Corporation Methods, apparatus, and systems for updating loglikelihood ratio information in an nT implementation of a Viterbi decoder
EP2442451A1 (en) * 2009-08-18 2012-04-18 TELEFONAKTIEBOLAGET LM ERICSSON (publ) Soft output Viterbi algorithm method and decoder
TWI394378B (en) * 2010-05-17 2013-04-21 Novatek Microelectronics Corp Viterbi decoder and writing and reading method
CN103701475B (en) * 2013-12-24 2017-01-25 北京邮电大学 Decoding method for Turbo codes with word length of eight bits in mobile communication system
TWI592937B (en) * 2016-07-05 2017-07-21 大心電子(英屬維京群島)股份有限公司 Decoding method, memory storage device and memory control circuit unit
CN108491346A (en) * 2018-03-23 2018-09-04 江苏沁恒股份有限公司 A kind of BMC coding/decoding methods
KR20220051750A (en) * 2020-10-19 2022-04-26 삼성전자주식회사 Apparatus and method for training device-to-device physical interface

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583078A (en) * 1984-11-13 1986-04-15 Communications Satellite Corporation Serial Viterbi decoder
DE3910739C3 (en) * 1989-04-03 1996-11-21 Deutsche Forsch Luft Raumfahrt Method for generalizing the Viterbi algorithm and means for performing the method
US5295142A (en) * 1989-07-18 1994-03-15 Sony Corporation Viterbi decoder
KR950005860B1 (en) * 1990-12-22 1995-05-31 삼성전자주식회사 Viterbi decoding method
JPH05335972A (en) * 1992-05-27 1993-12-17 Nec Corp Viterbi decoder
US5341387A (en) * 1992-08-27 1994-08-23 Quantum Corporation Viterbi detector having adjustable detection thresholds for PRML class IV sampling data detection
JPH08307283A (en) * 1995-03-09 1996-11-22 Oki Electric Ind Co Ltd Device and method for estimating maximum likelihood series
DE69601343T2 (en) * 1995-10-25 1999-07-15 Nec Corp Maximum probability decoding with soft decisions
JP2907090B2 (en) 1996-01-12 1999-06-21 日本電気株式会社 Apparatus and method for generating reliability
GB2309867A (en) * 1996-01-30 1997-08-06 Sony Corp Reliability data in decoding apparatus
JPH09232973A (en) 1996-02-28 1997-09-05 Sony Corp Viterbi decoder
JPH09232972A (en) 1996-02-28 1997-09-05 Sony Corp Viterbi decoder
US6212664B1 (en) * 1998-04-15 2001-04-03 Texas Instruments Incorporated Method and system for estimating an input data sequence based on an output data sequence and hard disk drive incorporating same
JPH11355150A (en) * 1998-06-09 1999-12-24 Sony Corp Punctured viterbi decoding method
US6236692B1 (en) * 1998-07-09 2001-05-22 Texas Instruments Incorporated Read channel for increasing density in removable disk storage devices
JP3196835B2 (en) * 1998-07-17 2001-08-06 日本電気株式会社 Viterbi decoding method and Viterbi decoder
US6405342B1 (en) * 1999-09-10 2002-06-11 Western Digital Technologies, Inc. Disk drive employing a multiple-input sequence detector responsive to reliability metrics to improve a retry operation

Also Published As

Publication number Publication date
WO2001026257A1 (en) 2001-04-12
KR20010050871A (en) 2001-06-25
IL143337A (en) 2008-08-07
JP3640924B2 (en) 2005-04-20
JP2003511895A (en) 2003-03-25
EP1135877A4 (en) 2004-04-07
AU762877B2 (en) 2003-07-10
CN1168237C (en) 2004-09-22
AU7690900A (en) 2001-05-10
KR100350502B1 (en) 2002-08-28
BR0007197A (en) 2001-09-04
DE60037963D1 (en) 2008-03-20
ATE385629T1 (en) 2008-02-15
ES2301492T3 (en) 2008-07-01
DE60037963T2 (en) 2009-01-29
EP1135877A1 (en) 2001-09-26
EP1135877B1 (en) 2008-02-06
IL143337A0 (en) 2002-04-21
CN1327653A (en) 2001-12-19
US6697443B1 (en) 2004-02-24
DK1135877T3 (en) 2008-06-09
CA2352206C (en) 2005-12-06

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