CA2370766A1 - Design analysis workstation for analyzing integrated circuits - Google Patents

Design analysis workstation for analyzing integrated circuits Download PDF

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Publication number
CA2370766A1
CA2370766A1 CA002370766A CA2370766A CA2370766A1 CA 2370766 A1 CA2370766 A1 CA 2370766A1 CA 002370766 A CA002370766 A CA 002370766A CA 2370766 A CA2370766 A CA 2370766A CA 2370766 A1 CA2370766 A1 CA 2370766A1
Authority
CA
Canada
Prior art keywords
image
design analysis
mosaics
integrated circuits
analysis workstation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002370766A
Other languages
French (fr)
Other versions
CA2370766C (en
Inventor
David F. Skoll
Terry Ludlow
Julia Elvidge
Michael Phaneuf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TechInsights Inc
Original Assignee
Chipworks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=27104679&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CA2370766(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from US09/927,551 external-priority patent/US6684379B2/en
Application filed by Chipworks Inc filed Critical Chipworks Inc
Publication of CA2370766A1 publication Critical patent/CA2370766A1/en
Application granted granted Critical
Publication of CA2370766C publication Critical patent/CA2370766C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G06T7/001—Industrial image inspection using an image reference approach
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G06T7/0006—Industrial image inspection using a design-rule based approach
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/97—Determining parameters from multiple pictures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/24—Indexing scheme for image data processing or generation, in general involving graphical user interfaces [GUIs]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/32—Indexing scheme for image data processing or generation, in general involving image mosaicing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Abstract

A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers.
CA002370766A 2000-10-18 2001-10-18 Design analysis workstation for analyzing integrated circuits Expired - Lifetime CA2370766C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US69081300A 2000-10-18 2000-10-18
US09/690,813 2000-10-18
US09/927,551 2001-08-13
US09/927,551 US6684379B2 (en) 2000-10-18 2001-08-13 Design analysis workstation for analyzing integrated circuits
PCT/CA2001/001455 WO2002033744A2 (en) 2000-10-18 2001-10-18 Design analysis workstation for analyzing integrated circuits

Publications (2)

Publication Number Publication Date
CA2370766A1 true CA2370766A1 (en) 2002-04-18
CA2370766C CA2370766C (en) 2003-09-09

Family

ID=27104679

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002370766A Expired - Lifetime CA2370766C (en) 2000-10-18 2001-10-18 Design analysis workstation for analyzing integrated circuits

Country Status (5)

Country Link
US (2) US7020853B2 (en)
EP (1) EP1370992A2 (en)
AU (1) AU2002210300A1 (en)
CA (1) CA2370766C (en)
WO (1) WO2002033744A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012741A1 (en) * 2004-08-04 2006-02-09 Semiconductor Insights Inc. Method and apparatus for locating short circuit faults in an integrated circuit layout

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1451732A4 (en) * 2001-12-10 2007-08-08 Mentor Graphics Corp Parallel electronic design automation: shared simultaneous editing
US7590963B2 (en) * 2003-11-21 2009-09-15 Mentor Graphics Corporation Integrating multiple electronic design applications
US7305648B2 (en) * 2003-11-21 2007-12-04 Mentor Graphics Corporation Distributed autorouting of conductive paths in printed circuit boards
US20050131942A1 (en) * 2003-12-15 2005-06-16 Wei-Fan Ting Assisted generating system and method for layout data conversions
US8230358B1 (en) 2004-06-22 2012-07-24 Apple Inc. Defining motion in a computer system with a graphical user interface
JP2006072769A (en) * 2004-09-02 2006-03-16 Fujitsu Ltd Circuit diagram display device, circuit diagram display method and circuit diagram display program
US8698844B1 (en) * 2005-04-16 2014-04-15 Apple Inc. Processing cursor movements in a graphical user interface of a multimedia application
US7298370B1 (en) * 2005-04-16 2007-11-20 Apple Inc. Depth ordering of planes and displaying interconnects having an appearance indicating data characteristics
US8326926B2 (en) * 2005-09-13 2012-12-04 Mentor Graphics Corporation Distributed electronic design automation architecture
JP2010506336A (en) * 2006-10-09 2010-02-25 メンター・グラフィクス・コーポレーション Characteristics in electronic design automation.
TWI423057B (en) 2007-09-04 2014-01-11 Cadence Design Systems Inc Layout versus schematic error system and method
US7937678B2 (en) * 2008-06-11 2011-05-03 Infineon Technologies Ag System and method for integrated circuit planar netlist interpretation
US8612923B2 (en) * 2009-02-06 2013-12-17 Cadence Design Systems, Inc. Methods, systems, and computer-program products for item selection and positioning suitable for high-altitude and context sensitive editing of electrical circuits
US8533650B2 (en) * 2009-09-17 2013-09-10 Cadence Design Systems, Inc. Annotation management for hierarchical designs of integrated circuits
US8566059B2 (en) * 2009-12-08 2013-10-22 International Business Machines Corporation Insertion of faults in logic model used in simulation
JP2011254238A (en) * 2010-06-01 2011-12-15 Sony Corp Information processing device, information processing method and information processing system
US8782577B2 (en) * 2010-07-24 2014-07-15 Cadence Design Systems, Inc. Method, apparatus, and article of manufacture for providing in situ, customizable information in designing electronic circuits with electrical awareness
US8694933B2 (en) 2010-07-24 2014-04-08 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness
US8495556B2 (en) * 2010-11-09 2013-07-23 Chipworks Inc. Circuit visualization using flightlines
WO2013082181A1 (en) * 2011-11-29 2013-06-06 Kla-Tencor Corporation Systems and methods for preparation of samples for sub-surface defect review
US9411925B2 (en) * 2014-04-14 2016-08-09 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Simultaneously viewing multi paired schematic and layout windows on printed circuit board (PCB) design software and tools
CN104461477A (en) 2013-09-13 2015-03-25 腾讯科技（北京）有限公司 Method, system and corresponding device for adding network comment information
TW201518972A (en) * 2013-11-14 2015-05-16 Wistron Corp Circuit design simulation system and circuit design method for PCB
US9798708B1 (en) 2014-07-11 2017-10-24 Google Inc. Annotating relevant content in a screen capture image
US9965559B2 (en) 2014-08-21 2018-05-08 Google Llc Providing automatic actions for mobile onscreen content
US10365807B2 (en) 2015-03-02 2019-07-30 Apple Inc. Control of system zoom magnification using a rotatable input mechanism
US9703541B2 (en) 2015-04-28 2017-07-11 Google Inc. Entity action suggestion on a mobile device
US9418454B1 (en) * 2015-07-23 2016-08-16 Axure Software Solutions, Inc. Generating markup encodings for the compact rendering of curves in interactive graphical designs
US10970646B2 (en) 2015-10-01 2021-04-06 Google Llc Action suggestions for user-selected content
US10178527B2 (en) 2015-10-22 2019-01-08 Google Llc Personalized entity repository
US10055390B2 (en) 2015-11-18 2018-08-21 Google Llc Simulated hyperlinks on a mobile device based on user intent and a centered selection of text
US10360340B2 (en) 2016-10-05 2019-07-23 Oracle International Corporation Overlay display of data from different databases
US10535005B1 (en) 2016-10-26 2020-01-14 Google Llc Providing contextual actions for mobile onscreen content
US11237696B2 (en) 2016-12-19 2022-02-01 Google Llc Smart assist for repeated actions
US10515181B2 (en) 2017-05-10 2019-12-24 International Business Machines Corporation Integrated circuit identification
US10719650B1 (en) * 2017-12-18 2020-07-21 Synopsys, Inc. Hierarchical dynamic heat maps in full custom EDA applications

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4224664A (en) * 1976-05-07 1980-09-23 Honeywell Information Systems Inc. Apparatus for detecting when the activity of one process in relation to a common piece of information interferes with any other process in a multiprogramming/multiprocessing computer system
US4623255A (en) * 1983-10-13 1986-11-18 The United States Of America As Represented By The Administrator, National Aeronautics And Space Administration Method of examining microcircuit patterns
GB2247345B (en) * 1990-07-05 1995-04-05 Haroon Ahmed Integrated circuit structure analysis
US5086477A (en) * 1990-08-07 1992-02-04 Northwest Technology Corp. Automated system for extracting design and layout information from an integrated circuit
US5590271A (en) * 1993-05-21 1996-12-31 Digital Equipment Corporation Interactive visualization environment with improved visual programming interface
US5623419A (en) * 1994-04-28 1997-04-22 Cadence Design Systems, Inc. Modeling of multi-disciplinary signals
US5694481A (en) * 1995-04-12 1997-12-02 Semiconductor Insights Inc. Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit
US5561293A (en) * 1995-04-20 1996-10-01 Advanced Micro Devices, Inc. Method of failure analysis with CAD layout navigation and FIB/SEM inspection
US6289116B1 (en) * 1996-09-27 2001-09-11 Semiconductor Insights, Inc. Computer-assisted design analysis method for extracting device and interconnect information
CA2216900C (en) 1996-10-01 2001-12-04 Semiconductor Insights Inc. Method to extract circuit information
CA2260510A1 (en) * 1998-01-28 1999-07-28 Chipworks Focused ion beam imaging method
US6591278B1 (en) * 2000-03-03 2003-07-08 R-Objects, Inc. Project data management system and method
US6671424B1 (en) * 2000-07-25 2003-12-30 Chipworks Predictive image caching algorithm
US7444274B1 (en) * 2003-04-23 2008-10-28 Cadence Design Systems, Inc. Method and system for verifying circuit designs through propagation of assertions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006012741A1 (en) * 2004-08-04 2006-02-09 Semiconductor Insights Inc. Method and apparatus for locating short circuit faults in an integrated circuit layout

Also Published As

Publication number Publication date
EP1370992A2 (en) 2003-12-17
CA2370766C (en) 2003-09-09
WO2002033744A2 (en) 2002-04-25
WO2002033744A3 (en) 2003-10-02
AU2002210300A1 (en) 2002-04-29
WO2002033744B1 (en) 2003-11-20
US7020853B2 (en) 2006-03-28
WO2002033744A9 (en) 2002-10-24
US20060095884A1 (en) 2006-05-04
US20040117750A1 (en) 2004-06-17
US7509601B2 (en) 2009-03-24

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EEER Examination request
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Effective date: 20211018

MKEX Expiry

Effective date: 20211018