CA2376971A1 - Combining a clock signal and a data signal - Google Patents
Combining a clock signal and a data signal Download PDFInfo
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- CA2376971A1 CA2376971A1 CA002376971A CA2376971A CA2376971A1 CA 2376971 A1 CA2376971 A1 CA 2376971A1 CA 002376971 A CA002376971 A CA 002376971A CA 2376971 A CA2376971 A CA 2376971A CA 2376971 A1 CA2376971 A1 CA 2376971A1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4902—Pulse width modulation; Pulse position modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/02—Channels characterised by the type of signal
- H04L5/06—Channels characterised by the type of signal the signals being represented by different frequencies
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G5/006—Details of the interface to the display terminal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Abstract
A method of transmitting data is a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least ones edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.
Description
~ACK~,OU~Tb O TI3E'~L~.SN~~ON
l . ,~,'eld of the ~,ver~n_ (0002] The present invention relates to transmitting clock and data signals.
2. nesc~tion felt ,~j3ac ,grou IOD03] The digital visual interface DVI 1.0 Specification, Digital Display Working Qroup [onlineJ, April 2,1999 [retrieved March 1S, 2001], retrieved from the lrrternet;~URL~-.httn, ,-._~uww.ddwg.o~>, attempts to a~dxess the computer industry's requirements for a digital connectivity specification !'or high-performance personal computers (PCs) and digital displays.
[0004) In synchronous high-speed transtniss~on systems that process digital signals, a clack signal and one or more data signals ~~re transmitted over separate wires.
For example, the system transmits data signals over data channels; and transmits a clock signal over a clock channel. These separate channels that transmit only a data signal or only a clock signal permit high performance digital data to be transmitted using a system that has a very simple architecture.
[OOOSJ However, because only the clock signal is transmitted over the clock channel, additional signals, such as data signals for example, cannot be transmitted over the clock channel using this systerrr. Therefore, this system does not traasrnit both a data signal and the clock signal over the clock channel.
_____.
SL1 ~~lF 'i'~E I~lq"1'IUN
~n00bj A method and as apparatus to combine a clock signal and a data signal, and vo transmit the combined signal over one cable, are disclosed.
~D00?j According to one aspect of the invention, provided is a method of transmitting data in a system including at least one data charurel and a separate clock channel, the clock channel being used to decode data transmitted an the at least one data channel, comprising:
combining a clack signal to be transmitted a~a the clock channel with a data signal having'a plurality of data words to generate a combi~tad aleck and data signal, and transmitting the combined clock and data signal on the clock channel;
wherein the data signal has been generated from the data words using an encoding scheme that shifts an energy spcctruxn of the combined clock and data signal away from an effective loop bandwidth of a clock recovery black.
[0008] According to another aspect of the invention, the encoding scheme maps the data word from a p-bit data word into a q-bit data word, where q > p.
[0009 According to another aspect of the invention, the encoding scheme is direct current (DC) balanced to minimize a DC component of the combined signal.
[OOlOJ According to another aspect of the invention, the clock signal has a pltuality of pulses, each pulse of the plurality of pulses having a front edge and aback edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving the front or back edges of the plurality of pulses.
X0011] According to a further aspect of the invention, the clock sigaal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving the front edges ofthe plurality of pulses.
[0012] According to another aspect of the invention, the clock signal has a plurality of pulses, each pulse of the plurality of pulses having a first edge and a second edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving both the frant edges and the back edges of the plurality of pulses.
[0013 According to a furthea~ aspect of the invention, the combining step fiuther comprises:
performing pre-emphasis to the combined signal, so that inter-symbol interference of the combined signal transmitted over a band-limned channel is minimized or reduced, [Q014] According to another aspect of the invention, the encoding scheme fhrther comprises:
uncreasing a number of transitions in each data word. The encoding scheme may also be an encryption scheme [0015] According to another aspect of the invention, the encoding scherae includes the step of encoding an insta~neous data word of said plurality of data words as function ofbath 'the instantaneous input word and earlier data wards in the data signal.
[0016 Further, the encoding scheme may include the step of encoding one ofthe data words of said plurality of data words as a function of one of the following;
future data words; or earlier data words; or futpre and earlier data words; of said plurality of data words.
[0017] According to another aspect of the invention, pravided is a method of transmitting data in a system including at least one data channel and a separate clock channel, the clock channel being used to decode data transmitted on the at least one data channel, comprising:
providing a clock signal having a plurality o~pulses, each pulse of the plurality of pulses having a front $dge and a back edge;
modulating a data signal having a plurality of data words onto the Clock signal by moving at least one edge of the plurality of pulses, thereby to create a combined clock and dafia signal; and transmitting the combined clock and data signal an the clock channel.
j0018] The method may fwther comprise:
encoding the data words using an encoding scherrre that maps the data words from p-bit data words into a q bit data woxds, where q > p.
[0019 The encoding scheme may be direct current (DC) balanced to minimize a DC component of the combined signal:
[0030 According to another aspect of the invention, the modulating step comprises::
modulating the data signal onto the clock signal by moving both ofthe front and back edges ofthe plurality of pulses.
[D02Ij The modulating may step comprise:
modulating the data signal onto the cloak signal by moving the fxont edges of the r~lurality of pulses.
[0022] The modulating step may comprise:
modulating the data signal onto the clock sigml by moving the back edges of the plurality of pulses.
[0023] The method may further comprise:
performing pre-emphasis to the combined signal, so that inter-symbol interference of the combined signal transmitted over a band-limited channel is minimized or reduced.
10024] The method may further comprise:
encoding the data words using an encoding scheme that increasing a number oftransitions in each data word; and the encoding scheme may be an encryption scheme [0025] Alternatively, the encoding scherae may comprise:
encoding art instantaneous data word of said plurality of data words as function of both the instantaneous input word and earlier data vyords in the data signal.
[0026] Alternatively, the eneodirtg scheme may comprise:
e~ncodiag one of the data words of said plurality of data words as a function of one of the following:
future data words; or earlier data v~rords; or future and earlier data words;
of said plurality of data words.
[002T] According to yet another aspect of tile invention, provided is a system for transmitting data, comprising a transmitter including at least one data channel and a separate clock channel, the clock channel being used by a receiver to diode data transmitted ca the at least one data channel, the transmitter being operative to:
combine a clock signal to be transmitted an the clock channel with a data signal hawing a plurality of data words, to generate a combined clock, and data signal, and transmit the combined clock and data signal on the cock channel;
wherein the 'data signal has been generated from the data words using an encoding scheme that shifts as energy spectrwn of the combined clock and data signal away from an effective loop bandwidth of a clock recovery blocj~. .
j0028] In the system, the encoding scheme may map the data word firom a p-bit data word into a q-bit data word, where q > p.
[0029) According to another aspect of the invention, the cloak signal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the transmitter combines the clod signal with the data signal by:
modulating the data signal onto the clock signal by moving at least. one edge of the plwality of pulses.
j0030] According to another aspect of the invention, the modulation may be done by moving he front edges ofthe plurality ofpul es.
j0031J According to another aspect of the invention, the modulation may be done by moving both the front edges and the back edges of the plurality of pulses.
j0032J According to yet another aspect of the invention, provided is a system for transmitting data, comprising a transmitter including at least one data channel and a separate clock charmel, the clock channel being used by a receiver to decode data transmitted an the at least one data channel, the transmitter being operative to;
provide a clock signal having a plurality of pulses, eachpulse of the plurality of pulses having a front edge and a back edge;
modulate a data signal having a plurality of data words onto the clock signal by moving at least one edge ofthe plurality of pulses, thereby to create $
coirrbined clock and data signal; and transmit the combined clock and data signal an the clock channel.
j003~~ The transmitter may further be operative tu:
encode the data words using an encoding scheme that maps the data words froia p-bit data words into a q-bit data words, where q > p.
j0034] , The transmitter may further be operative to:
modulate the data signal onto the clock signal by moving both of the front and back edges of the plurality of pulses.
j0035~ Alternatively, the transmitter may fu~.her be operative to:
modulate the data signal onto the clack signal by moving the front edges of the plurality of pulses.
[0036 Alternatively, the transmitter may further be operative to:
modulating the data signal onto the clock signal by moving the back ~dges of the plurality of pulse.
jOQ37j According to a further aspect of the invention, the transmitter uses as encoding scheme for generating the data signal from the data words that shifts an energy spectrum of the combined clock and data signal away from an effective loop bandwidth of a clock recovery block.
[OQ3BJ Other features and embodiments of the present invention will be illustrated by way of example and not by way of limitation in the accorapanying abstract, drawings, and detailed description: The abstract, summary of tlse invention, drawings, and detailed description are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims.
~F ~~T~~T~p ~NGS
j0039j The invention is illustrated by way ofexample and not by way of limitation in the figures of the accompanying drawings.
[0040j Figure 1 is a block diagram of a traa~silion-minimized differential signaling (TMbS) system that transmits a clock signal and one or more data signals over the clock channel.
[0041] Figut~e 2 is a liming disgraxn for data signals and clock signals that are transmitted over the clock channel.
[0042) Figure 3 illustrates a scheme for mixing a data signal into the clock signal in order to transmit the data and clock signals over the clock channel.
[0043j Figure 4 is a block diagram of a portion ofa receiver showing a phase locked loop (PLL) used to recover the clock signal firon~ the combined clock and data signal. .
[0044j Figure 5 shows individual clock and data components of a combined clack and data signal.
[0045] Figure 6 illustrates the effects of noise on the recovered clock and data signal at the receiving end.
[0046) Figure 7 shows a non-return-to-zero (1'~1.2Z) power spectrum of a data signal that is modulated with the clock signal and transmitted over the clock ehamtel.
j0047) Figure 8 shoves P>=L fitter transfer characteristics for a 2"a order PLL used to recover the clock signal from the combined clock and data si final j0048] Figure 9 shows the frequency spectra of the combined clock and data signal after being transformed by the PT.L fitter traus.~er characteristics.
'!o r0049j ~'~ignre 10 shows the ~xe~guency spcetrwa jitternoise components in a combined encoded data and clock signal.
r0050j Figure I1 shows an example of an encoding method.
[OOSIj Figure 12 shows a block diagram of an cpparatus that generates a combined encoded data and clock signal.
1t DE AILFiri D~FSCRYI~"~'~)~",N, j0052] A method and system to combine a data signal with a clock signal and to transmit the combined signal are disclosed. The eom~ined clock and data signal are transmitted over a clock channel. This increases the amount ofbandwidth that is available in the clock channel. In one embodiment, tie data signal is encoded, and the encoded data signal is combined with the clack signal. The encoding of the data signal causes some of the energy components of the encoded data signal to move to higher frequencies, so that a low pass filter can attenuate them. The low pass filter can then recover the clock signal from the combined signal, and output the recovered signal to other devices.
j0053] An example of a system that combines the clock signal and the data signal is a transition-minimized differential signaling (T1VI~S) system, which is described in published PCT application no. PCTIU899120488, publication no. WO 00/16525;
entitled "A System And Method For Sending And Receiving l7ata Signals Uver A Clock Signal .
Line," which is fully incaiporated into this application by reference.
(0054] Figure I shows a block diagram of the TMDS systerrr that can generate and transmit the combined clock and data signal. The combined signal is generated at the transmitting end 150, and the data signal', and the clock signal arc recovered at the receiving end 160. The combined clock and data signal 175 is transmitted over clack channel 170. Additional data signals are transmitted over data channels 110,120, and I30, j0055] Figure Z shows an example of a dada signal 210 that is typically transmitted separately from a clock signal 220 over one of the data channels 110, 120, t2 130. The clock signal 220 is used by the TN.IDS receirrer 160 to extract the data from the data signal 210. In addition to the data signals) 210 transmitted over one or more data channels 110,120,130, a further data sigmal may be combined with the olock signal 220 to generate a combined clock and data signal. The tr~rrsrnitling end 130 as shown in FiEure 1 may gea~erate the combined clock arid data signal by multiplexing the further digital data signal and the clock signal. The transmitting end then transmits the multiplexed signal over the clock channel.
j0056] Multiplexing a data signal with the clock signal may be performed using a modulation method to modulate one signal onto another signal. For example, as shown in Figures 3 and S, the location of the falling {or trailing) edge 310 of a pulse 315 of the clock signal 301 is modulated, or moved,; with respect to the position of the rising edge 320 so that the falling edge 310 of combined clock and data signal 175 is a function of data signal 520, and the rising edge 320 of combined signal 175 is a function of clock signal 301. This combined clock and data signal 17;~ can then be used to ~rans~mit the data signal simultaneously with the clock signal. Alternatively, the position of the rising edge 320 is modulated, or moved, with resp~t to the falling edge 310 so that the position ofthe rising edge 320 ofthc combined clo4k and data signal i75 is a function of the data signal. Alternatively, both the rising and failing edges of the clock signal 301 are modulated; or moved, relative to thoir normal positjons; so that the positions of both the rising and falling edges of the combined clock and data signal 175 is a function of the data signal. Note that the illustrated data ignal 520 is the final component that xnodula~es the clock signal 301. 'rhe original data signal, or the data words themselves, may typically be more simply represented. That is, the data signal 520 that is shown represents the data signal 520 aRer any encoding has been done to shift the energy spectrum of the data signal away fronn the energy spectntar of the clock signal 301.
[0057] The receiving end 160, as shown in Figrtre 1, may recover the cloak signal 301 from the combined signal 175 using a low pass filter, such as phase-locked loop (PLL) that can act as a low pass filter for example. The clack signal component of signal 1?5 may have a frequency that is well below the bandwidth of the clock transmission channel 170. Also, the datasignal component of the combined signal rnay have a frequency that is significantly higher than the frequency of the clock signal component, and higher than the Iow pass 'filter loop bandwidth. At the receiving end 160, the combined signal passes througtr thE:low pass filter. The high frequency energy of the data signal is attenuated from the combined signal by the low pass filter.
Therefore, the lvw pass filter can remove the data signal from the combined signal, and output a recovered clock signal.
j0058] An embodiment of a block diagram of a PLL low pass alter 400 used by the TMAS ystem 100 to recover the clock signal and send the recovered clock signal to data recovery components is shown in Figure 4. niv N block 410 is a divide by N circuit that receives combined clock and data signal 175, divides signal 175 by N, and outputs a divided by N combined clock and data ignal. PFD block 420 is a phase frequency detector that detects the frequency of divided by N combined signal. Cp block 4~0 is a charge pump that increases the voltage level of the sisal.
[0059] lyoop filter (L,l~ black 440 fohows !?lock 430, and filters the signal in order to zecover the data signal 480 and to recover the clock signal 490 from the combined signal 175. ThB mufti-phase Voltage Cqnfirolled Oscillator (V'CO) 450 feeds 1~
zhe recovered data signal 480 having a correctly generated frequency to the data extraction circuit 455. Data extraction circuit 455 is a dual-function circuit in the illustrated eW bodiment, and selves to extract the data both from recovered data signal 480 and from data signals 485 transmiried separately from the combined clock and data signal 175 over data channels 110, 120 and 130, as described above with reference to Figure 1. Note that data extraction circuit 455 has been shown schematically as a dual function circuit for purposes of illustrating the invention only, and separate functionality is typically provided in two diiferern modules, one for extracting data from the separate data channels and another for extracting data from the combined clock and' data channel.
This separate functionality usually results from the fact that the data extracting methods may be very different for the separate data channels as compared to the combined clock and data channel.
(0060] V'CO 450 also feeds the recovered clock signal to the divide by M (div M~
block 470, where the recovered clock signal is divie~eci by M. Div M block 470 then outputs the recovered clock signal 490 that is at the proper frequency, which is then provided to any device that needs it. For example, the proper frequency of signal 490 may be the frequency that is needed by Bata extraction unit 455 to extract data from the data signals 485 that are received by unit 455.
(0061] Thus, using modulation to combine the clock signal with the data signal allows the system 100 to transmit the combined signal 175 over cloak chaasnel 170. The modulation also allows the system 100 to recover the clock signal from the combined signal by using the low pass filter to attenuate the ttotse from the data signal component ofthe combined signal.
~0062j An example of the noise generated by combining the clock signal and the data signal is shown in Fignre 3, Modulating the clock signal 301 to include data signal X20 adds intentional fitter to the falling edge 310 of combined signal 175 in order to allow the transmission of both data and clbck information over the same channel, or line.
'The combined signal 175, including the fitter in falling edges 3I0, is pmces'sed at the receiving end I 60. At low frequencies; tlye fitter rnay only affect the unused, e.g., falling, edge of the combined signal.
(0063] The combined signal gives a minimal penalty in the performance of the system at low frequencies, because the PLL uses the rising edges of the incoming ~ ' combined signal to compare clock phases: Therefore, ~ benefit of using modulation to combine signals is maintaining the orthogonal pmpetrty of both the data signal and the clock signal. Also; because the clock si~aal is tran~itted at a significantly lower frequency than the data signals, as shown in ~'gure 2, the clock signal is not significantly attenuated in the bandwidth-limited clock channel 170.
[0064) However, as the frequency of the combined signal approaches the bandwidth 'limit ofthe clock channel, or the length of the clock channel cable increases, the combined signal is attenuated. This attenuation causes errors to the combined signal that is use to recover the clack signal,: Therefore, the recovered clock signal that is output from the low pass filter also has: errors caused by the attenuation.
[0U65] Furthermore, at a higher clock frequert~y, the frequency of the clock signal approaches the freqttancy of the data sigrjal. As a result, same of the energy components of the data signal are in a frequency region that is below the low pass filter's bandwidth, and are not attenuated by the low pass f:iter. The date signal's law frequency energy 1~
components that are able to pass through the low pass alter cause fitter noise to the combined signal. Therefore, the clack sisal recovered by the low pass fiber has fitter noise, which causes errors in the recovered clock signal that is output by the PLL. The fitter noise may be caused by inter-symbol interference end signal dispersion, for example.
[0066] Inter-symbol interference occurs wheq the frequency of the signal approaches the &eguency of the clock channel bandwidth. fit this high frequency, a bit, or symbol; transraitted on the signal is affected by an acjjacent bit or symbol. This prevents the symbol from reaching the threshold needed for detection by the receiver.
j006~J Signal dispersion also occurs ~rrhen the frequency ofthe signal is increased. For example, the digital data bits are reprcaented on the signal as square waves. Each square wave has multiple frequency components. Sorrae frequency components of a square wave travel faster than othets, which cause the frequency components to become dispersed at high frequencies. The slower frequency components may affect subsequently transmitted bits, and the faster frequency components may aff~t previously transmitted bits. For exaraple; the modulated falling edge ofthe clack signal may affect the rising edge of the clock signal because pf this signal dispersion.
[0068] Therefore, the noise from inter-symbol ~interferenoe and signal dispersion inereasos the amount of tow frequency fitter noise that passes through the low pass filter, such as a PLL for example, along with the clock si~n:rtl, and results in a noisy recovered clock signal. For example the effects of the noise caused by inter-symbol interference and signal dispersion at higher frequencies is shown with reference to~Figures 5 and 6.
1"i The combined clock and data signal 175 may be represented as the superposition of clock signal 301 and data signal 520, as shown in ~'ignrc S.
j0069] When the combined signal is transmitted Aver the clock line at a frequency that approaches the limit of the clock chynel's bandwidth, noise such as inter-symbol interference and signal dispersion cause the recovered clock and data signals to have errors. For example, Figure 5 shows the recovered clock signal 610 and the recovered data signal 620 that both have errors produced by the nqise that can pass through the low pass filter. Therefore, the r~overed clock signal that is output from tha PLL
has an increased bit error rate (BER).
r00TO] For example, the rising edge of the recovered clock signal is contaminated by Y~",~, . Ths resulting error impact from the jitteT noise can be expressed as:
Y
tr"~, = dy~
dt Because positive and negative pulses have opposite ef.~ects on the fitter, they effectively add fitter noise to the signal input to the PFIa (Phase Frequency Detector) as shown in Figure ~1. ' (QD711 The amount of fitter noise is the low frequency region can be graphically' shown by power and frequency spectrums. For example, a random data signal produces a power spectrum as illustrated in Figure 7. This power sp~um is produced using the following equation:
pow~T - k ~ 2 , where fo is the bit rate and f is the frequency.
A
t [0072] With respect to the frequency spectrum; if a random data stream is input M
a PLL having the transfer curve of Figure: 8, the noise energy components that are in frequency regions that are below the PLL loop bandwidth are able to pass through the low pass filter of the PLL, as shown in Figure 9. There~'ore, the PLL reshapes the incoming clock signal based on he unaltered fitter noise power spectrum, and outputs a recovered clack sigial having fitter noise components that era related to the PLL transfer characteristics.
]0093] Because the recovered clock sigpal that is output by the PLL includes the low frequency energy noise of the combined data and c~aek signal, as show~a by the shaded regions of Figure 9, this low fr~uency noise c~.uses the recovered clock signal to have errors; which consequently causes errors in the data sigials output by devices that use the clock signal for data recovery.
[0074] The amount of fitter anise that passes though the PLL, and is included in the recovered clock signal, can be significantly reduced or eliminated by encoding the data signal. The encoding can be used to reduce the amount of low frequency energy introduced onto the recovered clock signal from the fitter noise by moving a major portion of the data signal's data frequency spectrum into a higher frequency region that is above the PLL bandwidth. The PLL low pass filter at#cnuatea the high freguency fitter noise from the combined clock and encoded data signal, and recovers the lower frequency clock signal with a reduced amount ofnoise.
[U095] This movement of some jitier noise energy from lower frequency regions into higher frequency regions by encoding the data signal is apparent by comparing Flgeres 9 and 10. For example; the spectral: energy distnbution of a combined clock and 1g unencoded data word is shown in Figure 9. 'Wlsen a date signal is encoded, the encoding may include mapping an $-bit data word onto a' I O-bit data word for exatxiplE. The mapping causes the combined clock aid encoded data signal to have the spectral energy distribution as shown in Figure 10. .' [007bJ A comparison of the differences betweerk Figures 9 an<110 show that encoding a data word into a code space shi$s the spectral ~tergy distribution of the data word to higher frequencies, in order to move the energy' of some low freguency fitter components of blgurc 9 into the higher frequencies of Figure l0: For example, the amount of noise energy from the unencoded data signal that passes unfiltered through the PLL is shown by the energy distribution between the dated lines oFFigure 9.
This amount of noise energy is greater than the amount of noise energy from the encoded data signal that passes unfiltered through the T'LL, which is'~hown in Figure 10.
[0077j By shifting the energy spectrum of the combined clock and data signal away from the effective loop bandwidth of the PLL, 'the dependence on an unchanging front edge ofthe clock signal is substantially reduced pr eliminated, permitting the front edge or both edges of the clock signal to be used for ~odulatirnt.
[00981 The encoding causes the combined eloek and encoded data signal to harre characteristics that include minimizing or reducing jit~er noise, such as intez-symbol interference and signal dispersion for example, in the jcombined signal that is transmitted over a band-limitod channel. Because thie PLL can filter the high frequency fitter component from the combined clock and encoded dad signal, the encoding allows the PLL to attenuate the high fregueney fitter noise ener~r from the combined signal as shown in Figure 10.
[0099) As a result of encoding the data signal, therefore, the clock signal that is recovered by the PlrL from the combined clock and enepded data signal hes a reduced amount of noise energy, as shown by p'r'gnres 9 and 10..The recovered clock signal is sent to data recovery devices that use the cluck signal tai extract data either from a data signal or from the combined clock and encoded data sig;lal. This extracted data has fewer errors because the recovered clock si,gnal'used by the data recovery devices bas fewer errors, as compared tv a clock signal recovered from a combined signal that includes an unencoded data signal.
,.
[0080j One benefit of encoding the data is pern~itting a high frequency clock ~i signal to be combined with encoded data o form a combined signal that is transmitted over a single channel, and~permitting theclock signal ~;ttd the encoded data signal ofthe transmitted combined signal to be recovered, because borne low frequency eocnponents of the data signal are pushed to a higher frequency region by the data encoding.
'The high frequency may be a frequency that approaclhes the banjdwidth of the clock channel, for example.
a [0081] One method of data encoding uses minimal redundancy to increase the .
frequency spectnun ofthe energy irria~oduced to the carabined signal from modulating the ._ data signal onto the clock signal, in order to reduce th~ amount ofnoise in the recowereal clock signal. The minimal redundancy encoding method raay include mapping the data signal by increasing the number of bits of data in the data signal before the data signal is mixed with the clock signal. rrrcreasing he number of bits in the data signal allows moat of the energy in the data signal to be placed in a ~eqr~enoy region that is high enough to be filtered by the PLL.
?.l ~0082~ The encoding increases, ormaximi2es, the data transitions, thus moving some or all cfthe noise energy into a higher frequency spectrum region. For example, an cnrbadiment of encoding data is shown in~Figure 1l: The encoding 111(1 includes a data encoder in which an input data ward hawing p-bits is moped into a data word having g-bits, where q > p. Therefore, the encoding method increases the number ofdata transitions in order to move some energy from the fitter atoise alto higher frequency regions.
j0083j The method may combine he encoded cta wrord with a clock signal by modulating one or more edges of a clock si,~nal pulse bpsed on the encoded data word, 1124. For exxmmple, modulating the data word onto a cock signal pulse may use a transition maximized encoding scheme o move a rising edge, a falling edge, or both edges of one or mare pulses of the clock signal based ~~ the encoded data v~iard.
Alternatively, an encoding scheme with less than full ~t~~ansition maxitniza#ion may be ..
used rn one embodiment, the clock modulation based'on the encoded data signal includes pre-emphasis of the combined signal, so that the inter-symbol interference of the combined signal that is transmitted over a band-limited channel is minimized or reduced. ' . .
.~
~0084j Also, the data may be encoded so that ,fin output data word is a function of both the instantaneous input word and earlier input dada words. For example, as output encoded data word may be a function of-a finite number of future input data words or a finite number of earlier output data words orboth, F~rthcnnore, the encoding method ., may also include scrambling the encoded data signal ~n order to encrypt the data while maintaining the data signal's energy shift to higher frequencies. The encrypted data may be decrypted at the receiving end. The encoding method may ((se a coding that is direct 22, current (DC) balanced to miniraize DC coiuponent of encoded signal. The type of encoding that is uscd may vary depending on the frequency used and the amount of fitter reduction effect required by the devices that use the reaawered clock signal, such as data recovery devices for example.
[0085] The combined clock and encoded data word is then transmitted over a single channel,1130. In one embodiment; the data may;~be transmitted in both directions on the clock line: rn another embodiment; the data maybe transmitted in the opposite direction from the clock only.
[008G] An example of a device 1200 to encode ~ data signal and to combine the clock signal and the encoded data signal is shown in Figure 12. Many different implementations of this device, which may be a transitj~On-maximized (or transition increasing) encoder 1210, can be used. hor example, otie erabodiment of the encodor ,f 1210 maps as 8-bit input coding space into a 10-bit output coding space. This coding can F
be extended to map a p-hit into a q-bit by using higher redundancy. For example, instead of using an 8-bit to 10-bit encoding, the encoder may use an 8-bit to 12-bit encoding in ., order to further remove lower frequency components i~ the input stream.
.~
[0089) 1f the encoded data signal needs to be serialized, serializer 1220 may be ::
used to serialize the encoded data signal. After the dada signal is encoded and seriali2ed, ..
,, the encoded data signal is combincsd with; the clock signal. The combining may be i performed by modulator 1230, which modulates the c~~ock signal based on the encoded ~i data signal to generate a combined clock and encoded' data signal.
.~
[0088] For example, in one embodiment the Modulator may use one or more edges of a first edge, such as a rising or a falling edgq for example, of one or more pulses :;
:1 ., ,, ':
t7 k l ,t of the clock signal to send precise reference clock infonx~tion: In this embodiment, the ~~
modulator may use one or more edges of a second edge, uch as a falling or a rising edge for example, of one or more pulses of the clock signal t4isend digital data information.
a ~i C,nher embodiments of modulation may also be 'used. Fc~r example, both the rising edges ..
:r and falling edges of the clock signal pulses may be rnod~~lated as a function of the ..
encoded data signal, because the impact caused by jitter~is greatly reduced by the .
.1 frequency spectrum characteristics of the combined c1 "k and encoded data signal. The °~
combined sibmal may be transmitted in one signal cabled .
,.
[0089] A system and a method to combine a do ~~,a signal with a clock signal have .~
been discussed. Encoding a data signal before cambini~g the data signal with a high l frequency clock signal permits some of the noise components that ate moved to higher frequencies by the encoding to be attenuated by the PIS~.. Because the high frequency ,t noise components are attenuated, the amount of noise ''~ the recovered clock signal is ., ,.
reduced. Therefore, removing some of the noise enemy from the combined signal increases the precision in the recovered clock signal tit~t is output by the PLL. This :;
recovered clock signal with a reduced amount of erg allows data recovery devices that use the clock signal to extract data, either from a data .signal, or from the combined clock and encoded data signal. This extracted data has few errors than data extracted by a data recovery device that uses a noisy clock signal r~~overai from a combined cloak and ., unencoded data signal. a a [0090 Thus, combining a clock signal. and a data signal increases the bandwidth of the clock channel so that this channel can transmit~~oth clock and data simultaneously.
In one embodiment, the data signal may 1!re encoded. jEneoding the data signal moves 2~ir some of the energy components of the data signal to mode into higher frequency regions :.
~~
that can be filtered by the PLL, and reduces the amount Qf noise in the received combined encoded dale and clock signal. Therefore the combinec~j encoded data and clock signal I
can be transmitted at a frequency that approaches the ba~Odwidth of the clock channel without being significantly affected by noise, such as ink symbol interference or signal dispersion, for exaraple. Furthermore, the encoding permits the PLL to filter the high frequency energy from the combined signal, and to recct'~ver an accurate clock signal that .
:, ,~
can be used by other devices. '~
j0091] These and other embodiments of the prc~ent invention may be reali2ed in accordance with the teachings described Herein and it s ~ ould be evident that various modifications and changes may be made in these teac ~ g$ without departing from the .
broader spirit and scope of the invention. fihe specification and drawings are, z accordingly, to be regarded in an illustrative rather Thai restrictive sense and the .r invention measured only is terms of the claims.
;.
t.
l . ,~,'eld of the ~,ver~n_ (0002] The present invention relates to transmitting clock and data signals.
2. nesc~tion felt ,~j3ac ,grou IOD03] The digital visual interface DVI 1.0 Specification, Digital Display Working Qroup [onlineJ, April 2,1999 [retrieved March 1S, 2001], retrieved from the lrrternet;~URL~-.httn, ,-._~uww.ddwg.o~>, attempts to a~dxess the computer industry's requirements for a digital connectivity specification !'or high-performance personal computers (PCs) and digital displays.
[0004) In synchronous high-speed transtniss~on systems that process digital signals, a clack signal and one or more data signals ~~re transmitted over separate wires.
For example, the system transmits data signals over data channels; and transmits a clock signal over a clock channel. These separate channels that transmit only a data signal or only a clock signal permit high performance digital data to be transmitted using a system that has a very simple architecture.
[OOOSJ However, because only the clock signal is transmitted over the clock channel, additional signals, such as data signals for example, cannot be transmitted over the clock channel using this systerrr. Therefore, this system does not traasrnit both a data signal and the clock signal over the clock channel.
_____.
SL1 ~~lF 'i'~E I~lq"1'IUN
~n00bj A method and as apparatus to combine a clock signal and a data signal, and vo transmit the combined signal over one cable, are disclosed.
~D00?j According to one aspect of the invention, provided is a method of transmitting data in a system including at least one data charurel and a separate clock channel, the clock channel being used to decode data transmitted an the at least one data channel, comprising:
combining a clack signal to be transmitted a~a the clock channel with a data signal having'a plurality of data words to generate a combi~tad aleck and data signal, and transmitting the combined clock and data signal on the clock channel;
wherein the data signal has been generated from the data words using an encoding scheme that shifts an energy spcctruxn of the combined clock and data signal away from an effective loop bandwidth of a clock recovery black.
[0008] According to another aspect of the invention, the encoding scheme maps the data word from a p-bit data word into a q-bit data word, where q > p.
[0009 According to another aspect of the invention, the encoding scheme is direct current (DC) balanced to minimize a DC component of the combined signal.
[OOlOJ According to another aspect of the invention, the clock signal has a pltuality of pulses, each pulse of the plurality of pulses having a front edge and aback edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving the front or back edges of the plurality of pulses.
X0011] According to a further aspect of the invention, the clock sigaal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving the front edges ofthe plurality of pulses.
[0012] According to another aspect of the invention, the clock signal has a plurality of pulses, each pulse of the plurality of pulses having a first edge and a second edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving both the frant edges and the back edges of the plurality of pulses.
[0013 According to a furthea~ aspect of the invention, the combining step fiuther comprises:
performing pre-emphasis to the combined signal, so that inter-symbol interference of the combined signal transmitted over a band-limned channel is minimized or reduced, [Q014] According to another aspect of the invention, the encoding scheme fhrther comprises:
uncreasing a number of transitions in each data word. The encoding scheme may also be an encryption scheme [0015] According to another aspect of the invention, the encoding scherae includes the step of encoding an insta~neous data word of said plurality of data words as function ofbath 'the instantaneous input word and earlier data wards in the data signal.
[0016 Further, the encoding scheme may include the step of encoding one ofthe data words of said plurality of data words as a function of one of the following;
future data words; or earlier data words; or futpre and earlier data words; of said plurality of data words.
[0017] According to another aspect of the invention, pravided is a method of transmitting data in a system including at least one data channel and a separate clock channel, the clock channel being used to decode data transmitted on the at least one data channel, comprising:
providing a clock signal having a plurality o~pulses, each pulse of the plurality of pulses having a front $dge and a back edge;
modulating a data signal having a plurality of data words onto the Clock signal by moving at least one edge of the plurality of pulses, thereby to create a combined clock and dafia signal; and transmitting the combined clock and data signal an the clock channel.
j0018] The method may fwther comprise:
encoding the data words using an encoding scherrre that maps the data words from p-bit data words into a q bit data woxds, where q > p.
[0019 The encoding scheme may be direct current (DC) balanced to minimize a DC component of the combined signal:
[0030 According to another aspect of the invention, the modulating step comprises::
modulating the data signal onto the clock signal by moving both ofthe front and back edges ofthe plurality of pulses.
[D02Ij The modulating may step comprise:
modulating the data signal onto the cloak signal by moving the fxont edges of the r~lurality of pulses.
[0022] The modulating step may comprise:
modulating the data signal onto the clock sigml by moving the back edges of the plurality of pulses.
[0023] The method may further comprise:
performing pre-emphasis to the combined signal, so that inter-symbol interference of the combined signal transmitted over a band-limited channel is minimized or reduced.
10024] The method may further comprise:
encoding the data words using an encoding scheme that increasing a number oftransitions in each data word; and the encoding scheme may be an encryption scheme [0025] Alternatively, the encoding scherae may comprise:
encoding art instantaneous data word of said plurality of data words as function of both the instantaneous input word and earlier data vyords in the data signal.
[0026] Alternatively, the eneodirtg scheme may comprise:
e~ncodiag one of the data words of said plurality of data words as a function of one of the following:
future data words; or earlier data v~rords; or future and earlier data words;
of said plurality of data words.
[002T] According to yet another aspect of tile invention, provided is a system for transmitting data, comprising a transmitter including at least one data channel and a separate clock channel, the clock channel being used by a receiver to diode data transmitted ca the at least one data channel, the transmitter being operative to:
combine a clock signal to be transmitted an the clock channel with a data signal hawing a plurality of data words, to generate a combined clock, and data signal, and transmit the combined clock and data signal on the cock channel;
wherein the 'data signal has been generated from the data words using an encoding scheme that shifts as energy spectrwn of the combined clock and data signal away from an effective loop bandwidth of a clock recovery blocj~. .
j0028] In the system, the encoding scheme may map the data word firom a p-bit data word into a q-bit data word, where q > p.
[0029) According to another aspect of the invention, the cloak signal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the transmitter combines the clod signal with the data signal by:
modulating the data signal onto the clock signal by moving at least. one edge of the plwality of pulses.
j0030] According to another aspect of the invention, the modulation may be done by moving he front edges ofthe plurality ofpul es.
j0031J According to another aspect of the invention, the modulation may be done by moving both the front edges and the back edges of the plurality of pulses.
j0032J According to yet another aspect of the invention, provided is a system for transmitting data, comprising a transmitter including at least one data channel and a separate clock charmel, the clock channel being used by a receiver to decode data transmitted an the at least one data channel, the transmitter being operative to;
provide a clock signal having a plurality of pulses, eachpulse of the plurality of pulses having a front edge and a back edge;
modulate a data signal having a plurality of data words onto the clock signal by moving at least one edge ofthe plurality of pulses, thereby to create $
coirrbined clock and data signal; and transmit the combined clock and data signal an the clock channel.
j003~~ The transmitter may further be operative tu:
encode the data words using an encoding scheme that maps the data words froia p-bit data words into a q-bit data words, where q > p.
j0034] , The transmitter may further be operative to:
modulate the data signal onto the clock signal by moving both of the front and back edges of the plurality of pulses.
j0035~ Alternatively, the transmitter may fu~.her be operative to:
modulate the data signal onto the clack signal by moving the front edges of the plurality of pulses.
[0036 Alternatively, the transmitter may further be operative to:
modulating the data signal onto the clock signal by moving the back ~dges of the plurality of pulse.
jOQ37j According to a further aspect of the invention, the transmitter uses as encoding scheme for generating the data signal from the data words that shifts an energy spectrum of the combined clock and data signal away from an effective loop bandwidth of a clock recovery block.
[OQ3BJ Other features and embodiments of the present invention will be illustrated by way of example and not by way of limitation in the accorapanying abstract, drawings, and detailed description: The abstract, summary of tlse invention, drawings, and detailed description are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims.
~F ~~T~~T~p ~NGS
j0039j The invention is illustrated by way ofexample and not by way of limitation in the figures of the accompanying drawings.
[0040j Figure 1 is a block diagram of a traa~silion-minimized differential signaling (TMbS) system that transmits a clock signal and one or more data signals over the clock channel.
[0041] Figut~e 2 is a liming disgraxn for data signals and clock signals that are transmitted over the clock channel.
[0042) Figure 3 illustrates a scheme for mixing a data signal into the clock signal in order to transmit the data and clock signals over the clock channel.
[0043j Figure 4 is a block diagram of a portion ofa receiver showing a phase locked loop (PLL) used to recover the clock signal firon~ the combined clock and data signal. .
[0044j Figure 5 shows individual clock and data components of a combined clack and data signal.
[0045] Figure 6 illustrates the effects of noise on the recovered clock and data signal at the receiving end.
[0046) Figure 7 shows a non-return-to-zero (1'~1.2Z) power spectrum of a data signal that is modulated with the clock signal and transmitted over the clock ehamtel.
j0047) Figure 8 shoves P>=L fitter transfer characteristics for a 2"a order PLL used to recover the clock signal from the combined clock and data si final j0048] Figure 9 shows the frequency spectra of the combined clock and data signal after being transformed by the PT.L fitter traus.~er characteristics.
'!o r0049j ~'~ignre 10 shows the ~xe~guency spcetrwa jitternoise components in a combined encoded data and clock signal.
r0050j Figure I1 shows an example of an encoding method.
[OOSIj Figure 12 shows a block diagram of an cpparatus that generates a combined encoded data and clock signal.
1t DE AILFiri D~FSCRYI~"~'~)~",N, j0052] A method and system to combine a data signal with a clock signal and to transmit the combined signal are disclosed. The eom~ined clock and data signal are transmitted over a clock channel. This increases the amount ofbandwidth that is available in the clock channel. In one embodiment, tie data signal is encoded, and the encoded data signal is combined with the clack signal. The encoding of the data signal causes some of the energy components of the encoded data signal to move to higher frequencies, so that a low pass filter can attenuate them. The low pass filter can then recover the clock signal from the combined signal, and output the recovered signal to other devices.
j0053] An example of a system that combines the clock signal and the data signal is a transition-minimized differential signaling (T1VI~S) system, which is described in published PCT application no. PCTIU899120488, publication no. WO 00/16525;
entitled "A System And Method For Sending And Receiving l7ata Signals Uver A Clock Signal .
Line," which is fully incaiporated into this application by reference.
(0054] Figure I shows a block diagram of the TMDS systerrr that can generate and transmit the combined clock and data signal. The combined signal is generated at the transmitting end 150, and the data signal', and the clock signal arc recovered at the receiving end 160. The combined clock and data signal 175 is transmitted over clack channel 170. Additional data signals are transmitted over data channels 110,120, and I30, j0055] Figure Z shows an example of a dada signal 210 that is typically transmitted separately from a clock signal 220 over one of the data channels 110, 120, t2 130. The clock signal 220 is used by the TN.IDS receirrer 160 to extract the data from the data signal 210. In addition to the data signals) 210 transmitted over one or more data channels 110,120,130, a further data sigmal may be combined with the olock signal 220 to generate a combined clock and data signal. The tr~rrsrnitling end 130 as shown in FiEure 1 may gea~erate the combined clock arid data signal by multiplexing the further digital data signal and the clock signal. The transmitting end then transmits the multiplexed signal over the clock channel.
j0056] Multiplexing a data signal with the clock signal may be performed using a modulation method to modulate one signal onto another signal. For example, as shown in Figures 3 and S, the location of the falling {or trailing) edge 310 of a pulse 315 of the clock signal 301 is modulated, or moved,; with respect to the position of the rising edge 320 so that the falling edge 310 of combined clock and data signal 175 is a function of data signal 520, and the rising edge 320 of combined signal 175 is a function of clock signal 301. This combined clock and data signal 17;~ can then be used to ~rans~mit the data signal simultaneously with the clock signal. Alternatively, the position of the rising edge 320 is modulated, or moved, with resp~t to the falling edge 310 so that the position ofthe rising edge 320 ofthc combined clo4k and data signal i75 is a function of the data signal. Alternatively, both the rising and failing edges of the clock signal 301 are modulated; or moved, relative to thoir normal positjons; so that the positions of both the rising and falling edges of the combined clock and data signal 175 is a function of the data signal. Note that the illustrated data ignal 520 is the final component that xnodula~es the clock signal 301. 'rhe original data signal, or the data words themselves, may typically be more simply represented. That is, the data signal 520 that is shown represents the data signal 520 aRer any encoding has been done to shift the energy spectrum of the data signal away fronn the energy spectntar of the clock signal 301.
[0057] The receiving end 160, as shown in Figrtre 1, may recover the cloak signal 301 from the combined signal 175 using a low pass filter, such as phase-locked loop (PLL) that can act as a low pass filter for example. The clack signal component of signal 1?5 may have a frequency that is well below the bandwidth of the clock transmission channel 170. Also, the datasignal component of the combined signal rnay have a frequency that is significantly higher than the frequency of the clock signal component, and higher than the Iow pass 'filter loop bandwidth. At the receiving end 160, the combined signal passes througtr thE:low pass filter. The high frequency energy of the data signal is attenuated from the combined signal by the low pass filter.
Therefore, the lvw pass filter can remove the data signal from the combined signal, and output a recovered clock signal.
j0058] An embodiment of a block diagram of a PLL low pass alter 400 used by the TMAS ystem 100 to recover the clock signal and send the recovered clock signal to data recovery components is shown in Figure 4. niv N block 410 is a divide by N circuit that receives combined clock and data signal 175, divides signal 175 by N, and outputs a divided by N combined clock and data ignal. PFD block 420 is a phase frequency detector that detects the frequency of divided by N combined signal. Cp block 4~0 is a charge pump that increases the voltage level of the sisal.
[0059] lyoop filter (L,l~ black 440 fohows !?lock 430, and filters the signal in order to zecover the data signal 480 and to recover the clock signal 490 from the combined signal 175. ThB mufti-phase Voltage Cqnfirolled Oscillator (V'CO) 450 feeds 1~
zhe recovered data signal 480 having a correctly generated frequency to the data extraction circuit 455. Data extraction circuit 455 is a dual-function circuit in the illustrated eW bodiment, and selves to extract the data both from recovered data signal 480 and from data signals 485 transmiried separately from the combined clock and data signal 175 over data channels 110, 120 and 130, as described above with reference to Figure 1. Note that data extraction circuit 455 has been shown schematically as a dual function circuit for purposes of illustrating the invention only, and separate functionality is typically provided in two diiferern modules, one for extracting data from the separate data channels and another for extracting data from the combined clock and' data channel.
This separate functionality usually results from the fact that the data extracting methods may be very different for the separate data channels as compared to the combined clock and data channel.
(0060] V'CO 450 also feeds the recovered clock signal to the divide by M (div M~
block 470, where the recovered clock signal is divie~eci by M. Div M block 470 then outputs the recovered clock signal 490 that is at the proper frequency, which is then provided to any device that needs it. For example, the proper frequency of signal 490 may be the frequency that is needed by Bata extraction unit 455 to extract data from the data signals 485 that are received by unit 455.
(0061] Thus, using modulation to combine the clock signal with the data signal allows the system 100 to transmit the combined signal 175 over cloak chaasnel 170. The modulation also allows the system 100 to recover the clock signal from the combined signal by using the low pass filter to attenuate the ttotse from the data signal component ofthe combined signal.
~0062j An example of the noise generated by combining the clock signal and the data signal is shown in Fignre 3, Modulating the clock signal 301 to include data signal X20 adds intentional fitter to the falling edge 310 of combined signal 175 in order to allow the transmission of both data and clbck information over the same channel, or line.
'The combined signal 175, including the fitter in falling edges 3I0, is pmces'sed at the receiving end I 60. At low frequencies; tlye fitter rnay only affect the unused, e.g., falling, edge of the combined signal.
(0063] The combined signal gives a minimal penalty in the performance of the system at low frequencies, because the PLL uses the rising edges of the incoming ~ ' combined signal to compare clock phases: Therefore, ~ benefit of using modulation to combine signals is maintaining the orthogonal pmpetrty of both the data signal and the clock signal. Also; because the clock si~aal is tran~itted at a significantly lower frequency than the data signals, as shown in ~'gure 2, the clock signal is not significantly attenuated in the bandwidth-limited clock channel 170.
[0064) However, as the frequency of the combined signal approaches the bandwidth 'limit ofthe clock channel, or the length of the clock channel cable increases, the combined signal is attenuated. This attenuation causes errors to the combined signal that is use to recover the clack signal,: Therefore, the recovered clock signal that is output from the low pass filter also has: errors caused by the attenuation.
[0U65] Furthermore, at a higher clock frequert~y, the frequency of the clock signal approaches the freqttancy of the data sigrjal. As a result, same of the energy components of the data signal are in a frequency region that is below the low pass filter's bandwidth, and are not attenuated by the low pass f:iter. The date signal's law frequency energy 1~
components that are able to pass through the low pass alter cause fitter noise to the combined signal. Therefore, the clack sisal recovered by the low pass fiber has fitter noise, which causes errors in the recovered clock signal that is output by the PLL. The fitter noise may be caused by inter-symbol interference end signal dispersion, for example.
[0066] Inter-symbol interference occurs wheq the frequency of the signal approaches the &eguency of the clock channel bandwidth. fit this high frequency, a bit, or symbol; transraitted on the signal is affected by an acjjacent bit or symbol. This prevents the symbol from reaching the threshold needed for detection by the receiver.
j006~J Signal dispersion also occurs ~rrhen the frequency ofthe signal is increased. For example, the digital data bits are reprcaented on the signal as square waves. Each square wave has multiple frequency components. Sorrae frequency components of a square wave travel faster than othets, which cause the frequency components to become dispersed at high frequencies. The slower frequency components may affect subsequently transmitted bits, and the faster frequency components may aff~t previously transmitted bits. For exaraple; the modulated falling edge ofthe clack signal may affect the rising edge of the clock signal because pf this signal dispersion.
[0068] Therefore, the noise from inter-symbol ~interferenoe and signal dispersion inereasos the amount of tow frequency fitter noise that passes through the low pass filter, such as a PLL for example, along with the clock si~n:rtl, and results in a noisy recovered clock signal. For example the effects of the noise caused by inter-symbol interference and signal dispersion at higher frequencies is shown with reference to~Figures 5 and 6.
1"i The combined clock and data signal 175 may be represented as the superposition of clock signal 301 and data signal 520, as shown in ~'ignrc S.
j0069] When the combined signal is transmitted Aver the clock line at a frequency that approaches the limit of the clock chynel's bandwidth, noise such as inter-symbol interference and signal dispersion cause the recovered clock and data signals to have errors. For example, Figure 5 shows the recovered clock signal 610 and the recovered data signal 620 that both have errors produced by the nqise that can pass through the low pass filter. Therefore, the r~overed clock signal that is output from tha PLL
has an increased bit error rate (BER).
r00TO] For example, the rising edge of the recovered clock signal is contaminated by Y~",~, . Ths resulting error impact from the jitteT noise can be expressed as:
Y
tr"~, = dy~
dt Because positive and negative pulses have opposite ef.~ects on the fitter, they effectively add fitter noise to the signal input to the PFIa (Phase Frequency Detector) as shown in Figure ~1. ' (QD711 The amount of fitter noise is the low frequency region can be graphically' shown by power and frequency spectrums. For example, a random data signal produces a power spectrum as illustrated in Figure 7. This power sp~um is produced using the following equation:
pow~T - k ~ 2 , where fo is the bit rate and f is the frequency.
A
t [0072] With respect to the frequency spectrum; if a random data stream is input M
a PLL having the transfer curve of Figure: 8, the noise energy components that are in frequency regions that are below the PLL loop bandwidth are able to pass through the low pass filter of the PLL, as shown in Figure 9. There~'ore, the PLL reshapes the incoming clock signal based on he unaltered fitter noise power spectrum, and outputs a recovered clack sigial having fitter noise components that era related to the PLL transfer characteristics.
]0093] Because the recovered clock sigpal that is output by the PLL includes the low frequency energy noise of the combined data and c~aek signal, as show~a by the shaded regions of Figure 9, this low fr~uency noise c~.uses the recovered clock signal to have errors; which consequently causes errors in the data sigials output by devices that use the clock signal for data recovery.
[0074] The amount of fitter anise that passes though the PLL, and is included in the recovered clock signal, can be significantly reduced or eliminated by encoding the data signal. The encoding can be used to reduce the amount of low frequency energy introduced onto the recovered clock signal from the fitter noise by moving a major portion of the data signal's data frequency spectrum into a higher frequency region that is above the PLL bandwidth. The PLL low pass filter at#cnuatea the high freguency fitter noise from the combined clock and encoded data signal, and recovers the lower frequency clock signal with a reduced amount ofnoise.
[U095] This movement of some jitier noise energy from lower frequency regions into higher frequency regions by encoding the data signal is apparent by comparing Flgeres 9 and 10. For example; the spectral: energy distnbution of a combined clock and 1g unencoded data word is shown in Figure 9. 'Wlsen a date signal is encoded, the encoding may include mapping an $-bit data word onto a' I O-bit data word for exatxiplE. The mapping causes the combined clock aid encoded data signal to have the spectral energy distribution as shown in Figure 10. .' [007bJ A comparison of the differences betweerk Figures 9 an<110 show that encoding a data word into a code space shi$s the spectral ~tergy distribution of the data word to higher frequencies, in order to move the energy' of some low freguency fitter components of blgurc 9 into the higher frequencies of Figure l0: For example, the amount of noise energy from the unencoded data signal that passes unfiltered through the PLL is shown by the energy distribution between the dated lines oFFigure 9.
This amount of noise energy is greater than the amount of noise energy from the encoded data signal that passes unfiltered through the T'LL, which is'~hown in Figure 10.
[0077j By shifting the energy spectrum of the combined clock and data signal away from the effective loop bandwidth of the PLL, 'the dependence on an unchanging front edge ofthe clock signal is substantially reduced pr eliminated, permitting the front edge or both edges of the clock signal to be used for ~odulatirnt.
[00981 The encoding causes the combined eloek and encoded data signal to harre characteristics that include minimizing or reducing jit~er noise, such as intez-symbol interference and signal dispersion for example, in the jcombined signal that is transmitted over a band-limitod channel. Because thie PLL can filter the high frequency fitter component from the combined clock and encoded dad signal, the encoding allows the PLL to attenuate the high fregueney fitter noise ener~r from the combined signal as shown in Figure 10.
[0099) As a result of encoding the data signal, therefore, the clock signal that is recovered by the PlrL from the combined clock and enepded data signal hes a reduced amount of noise energy, as shown by p'r'gnres 9 and 10..The recovered clock signal is sent to data recovery devices that use the cluck signal tai extract data either from a data signal or from the combined clock and encoded data sig;lal. This extracted data has fewer errors because the recovered clock si,gnal'used by the data recovery devices bas fewer errors, as compared tv a clock signal recovered from a combined signal that includes an unencoded data signal.
,.
[0080j One benefit of encoding the data is pern~itting a high frequency clock ~i signal to be combined with encoded data o form a combined signal that is transmitted over a single channel, and~permitting theclock signal ~;ttd the encoded data signal ofthe transmitted combined signal to be recovered, because borne low frequency eocnponents of the data signal are pushed to a higher frequency region by the data encoding.
'The high frequency may be a frequency that approaclhes the banjdwidth of the clock channel, for example.
a [0081] One method of data encoding uses minimal redundancy to increase the .
frequency spectnun ofthe energy irria~oduced to the carabined signal from modulating the ._ data signal onto the clock signal, in order to reduce th~ amount ofnoise in the recowereal clock signal. The minimal redundancy encoding method raay include mapping the data signal by increasing the number of bits of data in the data signal before the data signal is mixed with the clock signal. rrrcreasing he number of bits in the data signal allows moat of the energy in the data signal to be placed in a ~eqr~enoy region that is high enough to be filtered by the PLL.
?.l ~0082~ The encoding increases, ormaximi2es, the data transitions, thus moving some or all cfthe noise energy into a higher frequency spectrum region. For example, an cnrbadiment of encoding data is shown in~Figure 1l: The encoding 111(1 includes a data encoder in which an input data ward hawing p-bits is moped into a data word having g-bits, where q > p. Therefore, the encoding method increases the number ofdata transitions in order to move some energy from the fitter atoise alto higher frequency regions.
j0083j The method may combine he encoded cta wrord with a clock signal by modulating one or more edges of a clock si,~nal pulse bpsed on the encoded data word, 1124. For exxmmple, modulating the data word onto a cock signal pulse may use a transition maximized encoding scheme o move a rising edge, a falling edge, or both edges of one or mare pulses of the clock signal based ~~ the encoded data v~iard.
Alternatively, an encoding scheme with less than full ~t~~ansition maxitniza#ion may be ..
used rn one embodiment, the clock modulation based'on the encoded data signal includes pre-emphasis of the combined signal, so that the inter-symbol interference of the combined signal that is transmitted over a band-limited channel is minimized or reduced. ' . .
.~
~0084j Also, the data may be encoded so that ,fin output data word is a function of both the instantaneous input word and earlier input dada words. For example, as output encoded data word may be a function of-a finite number of future input data words or a finite number of earlier output data words orboth, F~rthcnnore, the encoding method ., may also include scrambling the encoded data signal ~n order to encrypt the data while maintaining the data signal's energy shift to higher frequencies. The encrypted data may be decrypted at the receiving end. The encoding method may ((se a coding that is direct 22, current (DC) balanced to miniraize DC coiuponent of encoded signal. The type of encoding that is uscd may vary depending on the frequency used and the amount of fitter reduction effect required by the devices that use the reaawered clock signal, such as data recovery devices for example.
[0085] The combined clock and encoded data word is then transmitted over a single channel,1130. In one embodiment; the data may;~be transmitted in both directions on the clock line: rn another embodiment; the data maybe transmitted in the opposite direction from the clock only.
[008G] An example of a device 1200 to encode ~ data signal and to combine the clock signal and the encoded data signal is shown in Figure 12. Many different implementations of this device, which may be a transitj~On-maximized (or transition increasing) encoder 1210, can be used. hor example, otie erabodiment of the encodor ,f 1210 maps as 8-bit input coding space into a 10-bit output coding space. This coding can F
be extended to map a p-hit into a q-bit by using higher redundancy. For example, instead of using an 8-bit to 10-bit encoding, the encoder may use an 8-bit to 12-bit encoding in ., order to further remove lower frequency components i~ the input stream.
.~
[0089) 1f the encoded data signal needs to be serialized, serializer 1220 may be ::
used to serialize the encoded data signal. After the dada signal is encoded and seriali2ed, ..
,, the encoded data signal is combincsd with; the clock signal. The combining may be i performed by modulator 1230, which modulates the c~~ock signal based on the encoded ~i data signal to generate a combined clock and encoded' data signal.
.~
[0088] For example, in one embodiment the Modulator may use one or more edges of a first edge, such as a rising or a falling edgq for example, of one or more pulses :;
:1 ., ,, ':
t7 k l ,t of the clock signal to send precise reference clock infonx~tion: In this embodiment, the ~~
modulator may use one or more edges of a second edge, uch as a falling or a rising edge for example, of one or more pulses of the clock signal t4isend digital data information.
a ~i C,nher embodiments of modulation may also be 'used. Fc~r example, both the rising edges ..
:r and falling edges of the clock signal pulses may be rnod~~lated as a function of the ..
encoded data signal, because the impact caused by jitter~is greatly reduced by the .
.1 frequency spectrum characteristics of the combined c1 "k and encoded data signal. The °~
combined sibmal may be transmitted in one signal cabled .
,.
[0089] A system and a method to combine a do ~~,a signal with a clock signal have .~
been discussed. Encoding a data signal before cambini~g the data signal with a high l frequency clock signal permits some of the noise components that ate moved to higher frequencies by the encoding to be attenuated by the PIS~.. Because the high frequency ,t noise components are attenuated, the amount of noise ''~ the recovered clock signal is ., ,.
reduced. Therefore, removing some of the noise enemy from the combined signal increases the precision in the recovered clock signal tit~t is output by the PLL. This :;
recovered clock signal with a reduced amount of erg allows data recovery devices that use the clock signal to extract data, either from a data .signal, or from the combined clock and encoded data signal. This extracted data has few errors than data extracted by a data recovery device that uses a noisy clock signal r~~overai from a combined cloak and ., unencoded data signal. a a [0090 Thus, combining a clock signal. and a data signal increases the bandwidth of the clock channel so that this channel can transmit~~oth clock and data simultaneously.
In one embodiment, the data signal may 1!re encoded. jEneoding the data signal moves 2~ir some of the energy components of the data signal to mode into higher frequency regions :.
~~
that can be filtered by the PLL, and reduces the amount Qf noise in the received combined encoded dale and clock signal. Therefore the combinec~j encoded data and clock signal I
can be transmitted at a frequency that approaches the ba~Odwidth of the clock channel without being significantly affected by noise, such as ink symbol interference or signal dispersion, for exaraple. Furthermore, the encoding permits the PLL to filter the high frequency energy from the combined signal, and to recct'~ver an accurate clock signal that .
:, ,~
can be used by other devices. '~
j0091] These and other embodiments of the prc~ent invention may be reali2ed in accordance with the teachings described Herein and it s ~ ould be evident that various modifications and changes may be made in these teac ~ g$ without departing from the .
broader spirit and scope of the invention. fihe specification and drawings are, z accordingly, to be regarded in an illustrative rather Thai restrictive sense and the .r invention measured only is terms of the claims.
;.
t.
Claims (33)
1. A method of transmitting data in a system including at least one data channel and a separate clock channel, the clock channel being used to decode data transmitted on the at least one data channel, comprising:
combining a clock signal to be transmitted on the clock channel with a data signal, having a plurality of data words, to generate a combined clock and data signal, and transmitting the combined clock and data signal on the clock channel;
wherein the data signal has been generated from the data words using an encoding scheme that shifts an energy spectrum of the combined clock and data signal away from an effective loop bandwidth of a clock recovery block.
combining a clock signal to be transmitted on the clock channel with a data signal, having a plurality of data words, to generate a combined clock and data signal, and transmitting the combined clock and data signal on the clock channel;
wherein the data signal has been generated from the data words using an encoding scheme that shifts an energy spectrum of the combined clock and data signal away from an effective loop bandwidth of a clock recovery block.
2. The method of Claim 1 wherein the encoding scheme maps the data word from a p-bit data word into a g-bit data word, where q > p.
3. The method of Claim 2 wherein said encoding scheme is direct current (DC) balanced to minimize a DC component of the combined signal.
4. The method of Claim 1 wherein the clock signal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving the front or back edges of the plurality of pulses.
modulating the data signal onto the clock signal by moving the front or back edges of the plurality of pulses.
5. The method of Claim 1 wherein the clank signal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving the front edges of the plurality of pulses.
modulating the data signal onto the clock signal by moving the front edges of the plurality of pulses.
6. The method of Claim 1 wherein the clock signal has a plurality of pulses, each pulse of the plurality of pulses having a first edge and a second edge, and wherein the combining step comprises:
modulating the data signal onto the clock signal by moving both the front edges and the back edges of the plurality of pulse:
modulating the data signal onto the clock signal by moving both the front edges and the back edges of the plurality of pulse:
7. The method of Claims 1 wherein said combining further comprises:
performing pre-emphasis to the combined signer, so that inter-symbol interference of the combined signal transmitted over a band limited channel is minimized or reduced.
performing pre-emphasis to the combined signer, so that inter-symbol interference of the combined signal transmitted over a band limited channel is minimized or reduced.
8. The method of Claim 2 wherein said encoding scheme further comprises:
increasing a number of transitions in each data word.
increasing a number of transitions in each data word.
9. The method of Claim 1 wherein the encoding scheme is a an encryption scheme
10. The method of Claim 1 wherein the encoding scheme includes the step of:
encoding an instantaneous data word of said plurality of data words as function of both the instantaneous input word and earlier data words in the data signal.
encoding an instantaneous data word of said plurality of data words as function of both the instantaneous input word and earlier data words in the data signal.
11. The method of Claim 1 wherein the encoding scheme includes the step of;
encoding one of the data wards of said plurality of data words as a function of one of the following:
future data words; or earlier data words; or future and earlier data words; of said plurality of data words.
encoding one of the data wards of said plurality of data words as a function of one of the following:
future data words; or earlier data words; or future and earlier data words; of said plurality of data words.
12. A method of transmitting data in a system including at least one data channel and a separate clock channel, the clock channel being used to decode data transmitted on the at least one data channel, comprising:
providing a clock signal having a plurality at pulses, each pulse of the plurality of pulses having a front edge and a back edge;
modulating a data signal having a plurality of data words onto the clack signal by moving the front edges or the front and back edges of the pulses, thereby to create a combined clock and data signal; and transmitting the combined clock and data signal on the clock channel.
providing a clock signal having a plurality at pulses, each pulse of the plurality of pulses having a front edge and a back edge;
modulating a data signal having a plurality of data words onto the clack signal by moving the front edges or the front and back edges of the pulses, thereby to create a combined clock and data signal; and transmitting the combined clock and data signal on the clock channel.
13. The method of Claim 12 further comprising:
encoding the data words using an encoding scheme that maps the data words from p-bit data words into a q-bit data words, where q > p.
encoding the data words using an encoding scheme that maps the data words from p-bit data words into a q-bit data words, where q > p.
14. The method of Claim 13 wherein the encoding scheme is direct current (DC) balanced to minimize a DC component of the combined signal.
15. The method of Claim 12 wherein the modulating step comprises:
modulating the data signal onto the clock signal by moving both of the front and back edges of the plurality of pulses.
modulating the data signal onto the clock signal by moving both of the front and back edges of the plurality of pulses.
16. The method of Claim 12 wherein the modulating step comprises:
modulating the data signal onto the clock signal by moving the front edges of the plurality of pulses.
modulating the data signal onto the clock signal by moving the front edges of the plurality of pulses.
17. The method of Claim 12 wherein the modulating step comprises:
modulating the data signal onto the clock signal by moving the back edges of the plurality of pulses.
modulating the data signal onto the clock signal by moving the back edges of the plurality of pulses.
18. The method of Claim 12 further comprising:
performing pre-emphasis to the combined signal, so that inter-symbol interference of the combined signal transmitted over a band-limited channel is minimized or reduced.
performing pre-emphasis to the combined signal, so that inter-symbol interference of the combined signal transmitted over a band-limited channel is minimized or reduced.
19. The method of Claim 12 further comprising:
encoding the data words using an encoding scheme that increasing a number of transitions in each data word.
encoding the data words using an encoding scheme that increasing a number of transitions in each data word.
20. The method of Claim 19 wherein the encoding scheme is a an encryption scheme
21. The method of Claim 12 further comprising:
encoding an instantaneous data word of said plurality of data words as function of both the instantaneous input word and earlier data words in the data signal.
encoding an instantaneous data word of said plurality of data words as function of both the instantaneous input word and earlier data words in the data signal.
22. The method of Claim 12 further comprising:
encoding one of the data words of said plurality of data words as a function of one of the following:
future data words; or earlier data words; or future and earlier data words; of said plurality of data words.
encoding one of the data words of said plurality of data words as a function of one of the following:
future data words; or earlier data words; or future and earlier data words; of said plurality of data words.
23. A system for transmitting data, comprising a transmitter including at least one data channel and a separate clock channel, the clock channel being used by a receiver to decode data transmitted an the at least one data channel, the transmitter being operative to:
combine a clock signal to be transmitted on the clock channel with a data signal having a plurality of data words, to generate a combined clock and data signal, and transmit the combined clock and data signal on the clock channel;
wherein the data signal has been generated from the data words using an encoding scheme that shifts an energy spectrum of the combined clock and data signal away from an effective loop bandwidth of a clock recovery block.
combine a clock signal to be transmitted on the clock channel with a data signal having a plurality of data words, to generate a combined clock and data signal, and transmit the combined clock and data signal on the clock channel;
wherein the data signal has been generated from the data words using an encoding scheme that shifts an energy spectrum of the combined clock and data signal away from an effective loop bandwidth of a clock recovery block.
24. The system of Claim 23 wherein the encoding scheme maps the data word from a p-bit data word into a q-bit data ward, where q > p.
25. The system of Claim 23 wherein the clock signal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the transmitter combines the clock signal with the data signal by:
modulating the data signal onto the clock signal by moving at least one edge of the plurality of pulses.
modulating the data signal onto the clock signal by moving at least one edge of the plurality of pulses.
26. The system of Claim 23 wherein the clock signal has a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge, and wherein the transmitter combines the clock signal with the data signal by:
modulating the data signal onto the clock signally moving by the front edges of the plurality of pulses.
modulating the data signal onto the clock signally moving by the front edges of the plurality of pulses.
27. The system of Claim 23 wherein the clock signal has a plurality of pulses, each pulse of the plurality of pulses having a first edge and a second edge, and wherein the transmitter combines the clock signal with the data signal by:
modulating the data signal onto the clock signal by moving both the front edges and the back edges of the plurality of pulses.
modulating the data signal onto the clock signal by moving both the front edges and the back edges of the plurality of pulses.
28. A system for transmitting data, comprising a transmitter including at least one data channel and a separate clock channel, the clock channel being used by a receiver to decode data transmitted on the at least one data channel, the transmitter being operative to:
provide a clock signal having a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge;
modulate a data signal having a plurality of data words onto the clock signal by moving the front edges or the front and back edges of the plurality of pulses, thereby to create a combined clock and data signal; and transmit the combined clock and data signal on the clock channel.
provide a clock signal having a plurality of pulses, each pulse of the plurality of pulses having a front edge and a back edge;
modulate a data signal having a plurality of data words onto the clock signal by moving the front edges or the front and back edges of the plurality of pulses, thereby to create a combined clock and data signal; and transmit the combined clock and data signal on the clock channel.
29. The system of Claim 28 wherein the transmitter is further operative to:
encode the data words using an encoding scheme that maps the data words from p-bit data words into a q-bit data weds, where q > p.
encode the data words using an encoding scheme that maps the data words from p-bit data words into a q-bit data weds, where q > p.
30. The system of Claim 28 wherein the transmitter is further operative to:
modulate the data signal onto the clock signal by moving both of the front and back edges of the plurality of pulses.
modulate the data signal onto the clock signal by moving both of the front and back edges of the plurality of pulses.
31. The system of Claim 28 wherein the transmitter is further operative to:
modulate the data signal onto the clock signal by moving the front edges of the plurality of pulses.
modulate the data signal onto the clock signal by moving the front edges of the plurality of pulses.
32. The system of Claim 28 wherein the transmitted is further operative to:
modulating the data signal onto the clock signal by moving the back edges of the plurality of pulses.
modulating the data signal onto the clock signal by moving the back edges of the plurality of pulses.
33. The system of Claim 28 wherein the transmitter uses an encoding scheme for generating the data signal from the data words that shifts an energy spectrum of the combined clock and data signal away from an effective loop bandwidth of a clock recovery block.
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| US6351489B1 (en) * | 1996-09-30 | 2002-02-26 | Rosemount Inc. | Data bus communication technique for field instrument |
| JPH10164041A (en) * | 1996-11-26 | 1998-06-19 | Matsushita Electric Ind Co Ltd | Communication equipment |
| KR19980060015A (en) * | 1996-12-31 | 1998-10-07 | 김광호 | Interface circuit of liquid crystal module using reduced DC signal |
| KR100423135B1 (en) * | 1997-04-10 | 2004-06-16 | 삼성전자주식회사 | Lcd module using low-voltage differential signaling and system thereof |
| JPH1124035A (en) * | 1997-07-07 | 1999-01-29 | Hitachi Ltd | Liquid crystal display device |
| JP3092702B2 (en) * | 1997-10-29 | 2000-09-25 | 日本ビクター株式会社 | Clock generator |
| US6167077A (en) * | 1997-12-23 | 2000-12-26 | Lsi Logic Corporation | Using multiple high speed serial lines to transmit high data rates while compensating for overall skew |
| KR100521262B1 (en) * | 1997-12-31 | 2005-12-21 | 삼성전자주식회사 | Driving Method of Liquid Crystal Display Using Graphic Card |
| US6463092B1 (en) | 1998-09-10 | 2002-10-08 | Silicon Image, Inc. | System and method for sending and receiving data signals over a clock signal line |
-
2002
- 2002-03-15 US US10/099,533 patent/US7158593B2/en not_active Expired - Lifetime
- 2002-03-15 EP EP02251851.8A patent/EP1241844B1/en not_active Expired - Lifetime
- 2002-03-15 CA CA002376971A patent/CA2376971A1/en not_active Abandoned
- 2002-03-16 KR KR1020020014336A patent/KR100875348B1/en active IP Right Grant
- 2002-03-18 JP JP2002075003A patent/JP2002359613A/en active Pending
-
2009
- 2009-06-29 JP JP2009153903A patent/JP4940268B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP4940268B2 (en) | 2012-05-30 |
| US7158593B2 (en) | 2007-01-02 |
| KR20020074084A (en) | 2002-09-28 |
| EP1241844A3 (en) | 2006-05-10 |
| EP1241844A2 (en) | 2002-09-18 |
| EP1241844B1 (en) | 2019-11-06 |
| US20020181608A1 (en) | 2002-12-05 |
| KR100875348B1 (en) | 2008-12-22 |
| JP2009219159A (en) | 2009-09-24 |
| JP2002359613A (en) | 2002-12-13 |
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| Date | Code | Title | Description |
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| FZDE | Discontinued |