CA2393668A1 - Semiconductor component - Google Patents
Semiconductor component Download PDFInfo
- Publication number
- CA2393668A1 CA2393668A1 CA002393668A CA2393668A CA2393668A1 CA 2393668 A1 CA2393668 A1 CA 2393668A1 CA 002393668 A CA002393668 A CA 002393668A CA 2393668 A CA2393668 A CA 2393668A CA 2393668 A1 CA2393668 A1 CA 2393668A1
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- Prior art keywords
- strip
- resistance
- current
- limit value
- semiconductor component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 238000011017 operating method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 17
- 230000001681 protective effect Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 claims description 3
- 238000011161 development Methods 0.000 description 13
- 230000018109 developmental process Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 8
- 230000004044 response Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009532 heart rate measurement Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000010327 methods by industry Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The present invention creates an operating method for a semiconductor component having a substrate (1; 5);
having a conductive polysilicon strip (10; l0a-d) which is applied to the substrate (1; 5); having a first and a second electrical contact (11, 12; 11a-d, 12a-d) which are connected to the conductive polysilicon strip (10; 10a-d) such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (R diff1) up to a current limit value (I t) corresponding to an upper voltage limit value (V t) and, at current values greater than this, has a second differential resistance (R diff2), which is less than the first differential resistance (R diff1).
having a conductive polysilicon strip (10; l0a-d) which is applied to the substrate (1; 5); having a first and a second electrical contact (11, 12; 11a-d, 12a-d) which are connected to the conductive polysilicon strip (10; 10a-d) such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (R diff1) up to a current limit value (I t) corresponding to an upper voltage limit value (V t) and, at current values greater than this, has a second differential resistance (R diff2), which is less than the first differential resistance (R diff1).
Description
r ~A
Operating method for a semiconductor component Description S The present invention relates to an operating method for a semiconductor component having a substrate, having a conductive strip composed of a semiconductor material which is applied to the substrate, having a first and a second electrical contact which are connected to the conductive strip such that this forms an electrical resistance in between them.
Although, in principle, any semiconductor components with switch characteristics can be used, the present invention and the problems on which it is based will be explained with reference to trigger diodes based on silicon technology.
Trigger diodes are semiconductor components which switch from a blocking state to a switched-on state when the voltage which is applied between the two connections exceeds a specific value and, in the process, greatly reduce their differential resistance.
One known type of a trigger diode is the so-called four-layer diode (Binistor), which is sometimes also referred to as a breakover diode and is equally a thyristor which has no control electrode but makes use of breakdown triggering.
Trigger diodes and other known current and voltage switchable semiconductor components, such as controlled transistors (JFETs, NMOS, etc.), thyristors, TRIACs and DIACs as well as bipolar transistors for high-current pulse shaping have the following disadvantages:
a. complex multilayer structure;
b. restricted adaptability of the key parameters within the specified manufacturing technology;
~ , c. a high level of development effort, resulting from the complex method of operation;
d. complex and time-consuming process engineering (a large number of mask levels, etc.);
e. no compatibility for integration in conventional VLSI processes:
f. lack of stability with respect to technology fluctuations and transfer to different production sites: and g. large area and space requirements in VLSI
circuits.
One object of the present invention is thus to provide an operating method for a semiconductor component, which can easily be integrated in a VLSI process, in order to achieve a current-switched or voltage-switched switch characteristic.
According to the invention, this object is achieved by the operating method specified in Claim 1.
The idea on which the present invention is based is to allow the initially mentioned semiconductor component to be operated reversibly in a current/voltage range in which it has a first differential resistance up to a first current limit value corresponding to an upper voltage limit value and, at current values greater than this, has a second differential resistance, which is less than the first differential resistance.
The operation, according to the invention, of the component which is known per se in the form of a strip composed of a semiconductor material is distinguished by the simplicity of production, design and integribility in modern CMOS, BiCMOS and bipolar technologies for the component, and by its excellent linearity in the two operating modes, with a high and a low differential resistance. One excellent feature of the novel operation is undoubtedly the full adjustment capability of the key parameters within one manufacturing technology, just by means of layout measures, and hence the capability to use a number of such components, with a different characteristic, in a large scale integrated product.
According to the invention, the known resistance strip is used reversibly, with a different differentia l resistance, in two operating states. Reversibly relates, by way of example, 'to non-destructive operation in the DC mode or at least in the pulsed mode, with a typical duty ratio of 1 ms [sic].
When the current level is low, the resistance assumes a specific nominal value and, when a specific threshold current or a specific threshold voltage is exceeded, the component switches to a more highly conductive state, with a lower differential resistance.
The characterizing parameters of this switchable resistor are the two differential resistances Rdiffi and Rdiff2~ the limit voltage Vt, the limit current It and the upper limit of the reversible operating range, characterized by the critical current Ik. If required, the component may also have a blocking range up to a threshold value of Vth < Vt.
The use of the polysilicon resistor according to the invention has the following further advantages over the prior art:
a. simple structure, capability for implementation easily using all technologies;
Operating method for a semiconductor component Description S The present invention relates to an operating method for a semiconductor component having a substrate, having a conductive strip composed of a semiconductor material which is applied to the substrate, having a first and a second electrical contact which are connected to the conductive strip such that this forms an electrical resistance in between them.
Although, in principle, any semiconductor components with switch characteristics can be used, the present invention and the problems on which it is based will be explained with reference to trigger diodes based on silicon technology.
Trigger diodes are semiconductor components which switch from a blocking state to a switched-on state when the voltage which is applied between the two connections exceeds a specific value and, in the process, greatly reduce their differential resistance.
One known type of a trigger diode is the so-called four-layer diode (Binistor), which is sometimes also referred to as a breakover diode and is equally a thyristor which has no control electrode but makes use of breakdown triggering.
Trigger diodes and other known current and voltage switchable semiconductor components, such as controlled transistors (JFETs, NMOS, etc.), thyristors, TRIACs and DIACs as well as bipolar transistors for high-current pulse shaping have the following disadvantages:
a. complex multilayer structure;
b. restricted adaptability of the key parameters within the specified manufacturing technology;
~ , c. a high level of development effort, resulting from the complex method of operation;
d. complex and time-consuming process engineering (a large number of mask levels, etc.);
e. no compatibility for integration in conventional VLSI processes:
f. lack of stability with respect to technology fluctuations and transfer to different production sites: and g. large area and space requirements in VLSI
circuits.
One object of the present invention is thus to provide an operating method for a semiconductor component, which can easily be integrated in a VLSI process, in order to achieve a current-switched or voltage-switched switch characteristic.
According to the invention, this object is achieved by the operating method specified in Claim 1.
The idea on which the present invention is based is to allow the initially mentioned semiconductor component to be operated reversibly in a current/voltage range in which it has a first differential resistance up to a first current limit value corresponding to an upper voltage limit value and, at current values greater than this, has a second differential resistance, which is less than the first differential resistance.
The operation, according to the invention, of the component which is known per se in the form of a strip composed of a semiconductor material is distinguished by the simplicity of production, design and integribility in modern CMOS, BiCMOS and bipolar technologies for the component, and by its excellent linearity in the two operating modes, with a high and a low differential resistance. One excellent feature of the novel operation is undoubtedly the full adjustment capability of the key parameters within one manufacturing technology, just by means of layout measures, and hence the capability to use a number of such components, with a different characteristic, in a large scale integrated product.
According to the invention, the known resistance strip is used reversibly, with a different differentia l resistance, in two operating states. Reversibly relates, by way of example, 'to non-destructive operation in the DC mode or at least in the pulsed mode, with a typical duty ratio of 1 ms [sic].
When the current level is low, the resistance assumes a specific nominal value and, when a specific threshold current or a specific threshold voltage is exceeded, the component switches to a more highly conductive state, with a lower differential resistance.
The characterizing parameters of this switchable resistor are the two differential resistances Rdiffi and Rdiff2~ the limit voltage Vt, the limit current It and the upper limit of the reversible operating range, characterized by the critical current Ik. If required, the component may also have a blocking range up to a threshold value of Vth < Vt.
The use of the polysilicon resistor according to the invention has the following further advantages over the prior art:
a. simple structure, capability for implementation easily using all technologies;
b. full adaptability of the key parameters possible just by means of layout measures ("custom design");
c. simple internal structure linked to a low level of development effort;
d. short process time;
e. seamless integribility in conventional VLSI
processes;
f. high stability with respect to technology fluctuations and transfer to different production sites, by virtue of a robust internal structure; and g. small area requirements in VLSI circuits owing to good integribility and the comparatively high current carrying capacity per unit area (the area advantage is a factor of 2 to 10).
The dependent claims contain advantageous developments and improvements of the respective subject matter of the invention.
According to a further preferred development, the strip has a sheet resistance which is in the range between 100 and 1000 ohms per square.
According to a further preferred development, the strip has a cuboid shape with a length 1, a width b and a height h.
According to a further preferred development, the strip is formed from a number of strip elements with different dopings and/or lengths so as to produce a predetermined voltage limit value.
According to a further preferred development, the strip elements are alternately p-doped and n-doped.
According to a further preferred development, the alternate doping creates additional diode forward-bias thresholds in the current path.
According to a further preferred development, the alternate doping creates additional diode breakdown thresholds in the current path.
According to a further preferred development, the voltage limit value Vt is set in accordance with the relationship Vt = R b (k/RSq) 1i2, where R is the resistance, b is the width, k is a constant and RSQ is the sheet resistance of the strip.
According to a further preferred development, the semiconductor component is used as an ESD protective element.
According to a further preferred development, the semiconductor component is used with two functions, as an ESD protective element and as a bias resistor, in a radio-frequency circuit arrangement.
According to a further preferred development, the strip is formed from doped polysilicon as the semiconductor material.
Exemplary embodiments of the invention will be explained in more detail in the following description and are illustrated in the drawings, in which:
Figure 1 shows a schematic illustration of a polysilicon resistor on a substrate, in order to explain a first embodiment of the present invention;
Figure 2 shows the response of the differential resistance and the current/voltage characteristic of the polysilicon strip for the first embodiment of the operating method according to the invention;
Figure 3 shows a current/voltage characteristic with two selected resistors with the same nominal resistance;
Figure 4 shows the arrangement of a polysilicon strip in order to explain a second embodiment of the operating method according to the invention; and Figure 5 shows a radio-frequency circuit arrangement in order to explain one field of application of the operating method according to the invention.
Identical reference symbols in the figures denote identical or functionally identical components.
Figure 1 shows a schematic illustration of a polysilicon resistor on a substrate, in order to explain a first embodiment of the present invention.
In Figure 1, the reference symbol 1 denotes a silicon wafer substrate, on which an insulation layer 5, for example composed of silicon dioxide, is applied. A
cuboid polysilicon strip with a length 1, a width b and a height h is provided on the insulation strip 5, and is denoted by the reference symbol 10. The technological production of such a polysilicon strip 10 is well known from the prior art. Chemical vapor deposition with subsequent structuring of doped polysilicon may be mentioned as one example. With a known technology, by way of example, the height h of the polysilicon resistance strip is about O.1S E.tm, the width b is in the region of a few micrometers, and the length I is in the region of a few tens of micrometers.
- 7 _ The sheet resistance of the deposited polysilicon, and hence the resistance of the polysilicon strip 10, may be varied within a very wide value range by the doping level, for example using boron, arsenic, phosphorus and the like. Comprehensive investigations have been carried out in the value range from 100 to 1000 S2/sq in conjunction with the described embodiment. Contacts 11, 12 are fitted in the normal way to the ends of the polysilicon strip 10 and are connected to lines 13, 14, which are in turn connected to the connections of a controllable current source 15.
The response of the differential resistance and of the current/voltage characteristic of the polysilicon strip 10 for the first embodiment of the operating method according to the invention are illustrated in Figure 2.
During operation, the controllable current source 15 makes it possible to provide the polysilicon strip with a reversible response, with the polysilicon strip having a first differential resistance Rdiffi up to a current limit value It corresponding to an upper voltage limit value Vt, and having a second differential resistance Raiff2. which is less than the first differential resistance Rdiffl. at current levels above this.
As can clearly be seen from Figure 2, this response is the same as the response of a known DIAC. In particular, all that need be remembered is that the current may be limited to a critical upper current value Ik, above which irreversible changes occur in the polysilicon, for example fused channels.
Typical test conditions for the controllable current source I5 illustrated in Figure 1 are pulse measurements in the 100 nanosecond range, with the polysilicon strip 10 being observed to have recovery r . ' ~
times for reaching the higher resistance, starting from the lower one, in the millisecond range.
The switching of the resistor in the form of the polysilicon strip 10 can be explained by the current limit value It being exceeded such that this leads to the resistor being flooded with charge carriers by means of thermal generation. Analytically, this switching can be described by a specific electrical power Vt x It being supplied in a specific resistor volume bxlxh, where b, h, 1 are the abovementioned dimensions of the polysilicon strip 10.
The definition V, x I, - k = constant Ixb and the definition of the sheet resistance Rsq by l R = Rsq -w results in the relationship Vt = R b k (1) In this case, the voltage limit value Vt can be varied by the width of the polysilicon resistor, the resistance R and by the specific resistance or resistivity. R is normally governed by the application, and the minimum width b of the resistor is governed by the electromigration requirements and/or the maximum current carrying capacity.
Virtually any desired resistance from a few ohms up to the Megaohm range can be achieved, with an acceptable surface area, by the combination of different resistor dopings in polysilicon or by using diffusion resistors (for example n+/n-/intrinsic) so that the limit voltage ' S t Vt can be varied over a very wide range.
Figure 3 shows a current/voltage characteristic with two selected resistors, with the same nominal resistance. The curve (1) shows the response for a ratio b/1 = 5/1, and the curve (2) shows the response for a ratio b/1 = 25/5. It can clearly be seen that the limit voltage Vt2 becomes greater as the width 1 increases, that is to say Vt2 = 13.8 V is greater than Vtl = 4 V .
Figure 4 shows the arrangement of a polysilicon strip in order to explain a second embodiment of the operating method according to the invention.
According to this second embodiment, the polysilicon strip 10 is formed from a number of strip elements l0a-lOd, which have different doping and/or a different length 11-14, so that a predetermined voltage limit value Vt can be achieved over a wide value range by appropriate series connection. Such connection can be achieved by means of the fuse principle, by laser trimming, or by other conventional techniques.
Figure 5 shows a radio-frequency circuit arrangement in order to explain one field of application of the operating method according to the invention.
In Figure 5, 100, 200 respectively denote a first and a second supply voltage line. E1 to E6 are ESD protective elements, for example trigger diodes, which are provided between the two supply lines. Al, A2 are, respectively, a first and a second radio-frequency path for injection of a radio-frequency signal, and they are respectively connected to the circuit nodes Kl and K4, which in turn form center nodes for the ESD protective elements E1, E2 and E3, E4, respectively.
A differential stage, which is denoted by DS and has two input transistors T1, T2 and one output transistor T3, is provided in the center of the circuit. Further details of this differential stage are known and will not be explained in any more detail here. 50 S2 resistors R1 and R2 are provided as bias resistors for the differential stage DS and are connected via the respective circuit nodes K2 and K3 to the transistors T1, T2. Furthermore, the nodes K2, K3 are at the same potential as the respective nodes K1 and K4.
The particular difficulty of ESD protection in a radio-frequency circuit arrangement such as this is the very small tolerable capacitance plates which can be used for ESD protection. Until now, effective ESD protection has been impossible to achieve in many cases. The use of the polysilicon strip 10 according to the invention as a switchable resistor allows these previous problems to be overcome.
For this purpose, the resistors R1, R2 are simply each replaced by a polysilicon strip according to the invention and of appropriate size, in which case the ESD protective elements E1 and E3 may be omitted at the same time. Since the parameters of the width d and the resistance R of these resistors can be varied independently of one another, it is possible, as shown in Figure 4, to design a 50 S2 resistor with a specific b/1 ratio, which has a suitable limit voltage Vtz, for example of several hundred volts, which is suitable for this application.
A suitable layout thus allows the polysilicon strip 10 to be used as the resistor R1 or R2, and at the same time as the ESD protective element E1 or E3, respectively. This leads to a significant saving in surface area, and at the same time to improved performance, since there is no need for any additional capacitance plates in the form of additional ESD
protective elements E1, E2.
A resistance layer of p+ polysilicon with 310 S2/sq will be used as a specific example for the design of a polysilicon resistor strip in a radio-frequency circuit arrangement 50 as shown in Figure 5. For electromigration reasons, b must be greater than micrometers. With the relationship (1) quoted above, b is 20 micrometers, so that the electromigration condition is satisfied, and an ESD resistance of 10 approximately 1 kV is achieved. Should greater widths b be required owing to electromigration or ESD
protection, the sheet resistance may be increased by changing the doping.
15 Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted to these, but may be modified in a large number of ways.
In particular, the present invention is not restricted to polysilicon or to a specific type of polysilicon doping. In addition, the quoted applications are only by way of example and may be extended as required to any fields of application where switchable resistors are required.
The strip may also have any other desired geometries.
Typical further fields of application for the method according to the invention are:
a. nonlinear pulse shaping of high-speed current pulses, for example in laser diode drivers;
b. fields of application of a DIAC, for example triggering of TRIACs and thyristors for high-current/high-voltage and smart power applications c. non-destructive dissipation of high-current S
pulses, for example of electrostatic discharges (ESD
protective elements), lightning protection circuits;
d. latch-up protection circuits;
e. applications in the high-current field, in which the power loss is intended to be limited for high current densities.
List of reference symbols 1 Wafer substrate Insulation layer 10; l0a-d Polysilicon strip 11, 12 Contacts 13, 14 Lines Controllable current source l,ll-14,b,h Length, width, height It; Vt, Vri, Current limit value; voltage limit value Vt2 Ik Critical current value 100, 200 Supply potential lines VDDP, VSSB Supply potentials E1, E6 ESD protective elements Al, A2 Radio-frequency pads R1, R2 50 ohm bias resistors DS Differential stage K1-K4 Circuit nodes
c. simple internal structure linked to a low level of development effort;
d. short process time;
e. seamless integribility in conventional VLSI
processes;
f. high stability with respect to technology fluctuations and transfer to different production sites, by virtue of a robust internal structure; and g. small area requirements in VLSI circuits owing to good integribility and the comparatively high current carrying capacity per unit area (the area advantage is a factor of 2 to 10).
The dependent claims contain advantageous developments and improvements of the respective subject matter of the invention.
According to a further preferred development, the strip has a sheet resistance which is in the range between 100 and 1000 ohms per square.
According to a further preferred development, the strip has a cuboid shape with a length 1, a width b and a height h.
According to a further preferred development, the strip is formed from a number of strip elements with different dopings and/or lengths so as to produce a predetermined voltage limit value.
According to a further preferred development, the strip elements are alternately p-doped and n-doped.
According to a further preferred development, the alternate doping creates additional diode forward-bias thresholds in the current path.
According to a further preferred development, the alternate doping creates additional diode breakdown thresholds in the current path.
According to a further preferred development, the voltage limit value Vt is set in accordance with the relationship Vt = R b (k/RSq) 1i2, where R is the resistance, b is the width, k is a constant and RSQ is the sheet resistance of the strip.
According to a further preferred development, the semiconductor component is used as an ESD protective element.
According to a further preferred development, the semiconductor component is used with two functions, as an ESD protective element and as a bias resistor, in a radio-frequency circuit arrangement.
According to a further preferred development, the strip is formed from doped polysilicon as the semiconductor material.
Exemplary embodiments of the invention will be explained in more detail in the following description and are illustrated in the drawings, in which:
Figure 1 shows a schematic illustration of a polysilicon resistor on a substrate, in order to explain a first embodiment of the present invention;
Figure 2 shows the response of the differential resistance and the current/voltage characteristic of the polysilicon strip for the first embodiment of the operating method according to the invention;
Figure 3 shows a current/voltage characteristic with two selected resistors with the same nominal resistance;
Figure 4 shows the arrangement of a polysilicon strip in order to explain a second embodiment of the operating method according to the invention; and Figure 5 shows a radio-frequency circuit arrangement in order to explain one field of application of the operating method according to the invention.
Identical reference symbols in the figures denote identical or functionally identical components.
Figure 1 shows a schematic illustration of a polysilicon resistor on a substrate, in order to explain a first embodiment of the present invention.
In Figure 1, the reference symbol 1 denotes a silicon wafer substrate, on which an insulation layer 5, for example composed of silicon dioxide, is applied. A
cuboid polysilicon strip with a length 1, a width b and a height h is provided on the insulation strip 5, and is denoted by the reference symbol 10. The technological production of such a polysilicon strip 10 is well known from the prior art. Chemical vapor deposition with subsequent structuring of doped polysilicon may be mentioned as one example. With a known technology, by way of example, the height h of the polysilicon resistance strip is about O.1S E.tm, the width b is in the region of a few micrometers, and the length I is in the region of a few tens of micrometers.
- 7 _ The sheet resistance of the deposited polysilicon, and hence the resistance of the polysilicon strip 10, may be varied within a very wide value range by the doping level, for example using boron, arsenic, phosphorus and the like. Comprehensive investigations have been carried out in the value range from 100 to 1000 S2/sq in conjunction with the described embodiment. Contacts 11, 12 are fitted in the normal way to the ends of the polysilicon strip 10 and are connected to lines 13, 14, which are in turn connected to the connections of a controllable current source 15.
The response of the differential resistance and of the current/voltage characteristic of the polysilicon strip 10 for the first embodiment of the operating method according to the invention are illustrated in Figure 2.
During operation, the controllable current source 15 makes it possible to provide the polysilicon strip with a reversible response, with the polysilicon strip having a first differential resistance Rdiffi up to a current limit value It corresponding to an upper voltage limit value Vt, and having a second differential resistance Raiff2. which is less than the first differential resistance Rdiffl. at current levels above this.
As can clearly be seen from Figure 2, this response is the same as the response of a known DIAC. In particular, all that need be remembered is that the current may be limited to a critical upper current value Ik, above which irreversible changes occur in the polysilicon, for example fused channels.
Typical test conditions for the controllable current source I5 illustrated in Figure 1 are pulse measurements in the 100 nanosecond range, with the polysilicon strip 10 being observed to have recovery r . ' ~
times for reaching the higher resistance, starting from the lower one, in the millisecond range.
The switching of the resistor in the form of the polysilicon strip 10 can be explained by the current limit value It being exceeded such that this leads to the resistor being flooded with charge carriers by means of thermal generation. Analytically, this switching can be described by a specific electrical power Vt x It being supplied in a specific resistor volume bxlxh, where b, h, 1 are the abovementioned dimensions of the polysilicon strip 10.
The definition V, x I, - k = constant Ixb and the definition of the sheet resistance Rsq by l R = Rsq -w results in the relationship Vt = R b k (1) In this case, the voltage limit value Vt can be varied by the width of the polysilicon resistor, the resistance R and by the specific resistance or resistivity. R is normally governed by the application, and the minimum width b of the resistor is governed by the electromigration requirements and/or the maximum current carrying capacity.
Virtually any desired resistance from a few ohms up to the Megaohm range can be achieved, with an acceptable surface area, by the combination of different resistor dopings in polysilicon or by using diffusion resistors (for example n+/n-/intrinsic) so that the limit voltage ' S t Vt can be varied over a very wide range.
Figure 3 shows a current/voltage characteristic with two selected resistors, with the same nominal resistance. The curve (1) shows the response for a ratio b/1 = 5/1, and the curve (2) shows the response for a ratio b/1 = 25/5. It can clearly be seen that the limit voltage Vt2 becomes greater as the width 1 increases, that is to say Vt2 = 13.8 V is greater than Vtl = 4 V .
Figure 4 shows the arrangement of a polysilicon strip in order to explain a second embodiment of the operating method according to the invention.
According to this second embodiment, the polysilicon strip 10 is formed from a number of strip elements l0a-lOd, which have different doping and/or a different length 11-14, so that a predetermined voltage limit value Vt can be achieved over a wide value range by appropriate series connection. Such connection can be achieved by means of the fuse principle, by laser trimming, or by other conventional techniques.
Figure 5 shows a radio-frequency circuit arrangement in order to explain one field of application of the operating method according to the invention.
In Figure 5, 100, 200 respectively denote a first and a second supply voltage line. E1 to E6 are ESD protective elements, for example trigger diodes, which are provided between the two supply lines. Al, A2 are, respectively, a first and a second radio-frequency path for injection of a radio-frequency signal, and they are respectively connected to the circuit nodes Kl and K4, which in turn form center nodes for the ESD protective elements E1, E2 and E3, E4, respectively.
A differential stage, which is denoted by DS and has two input transistors T1, T2 and one output transistor T3, is provided in the center of the circuit. Further details of this differential stage are known and will not be explained in any more detail here. 50 S2 resistors R1 and R2 are provided as bias resistors for the differential stage DS and are connected via the respective circuit nodes K2 and K3 to the transistors T1, T2. Furthermore, the nodes K2, K3 are at the same potential as the respective nodes K1 and K4.
The particular difficulty of ESD protection in a radio-frequency circuit arrangement such as this is the very small tolerable capacitance plates which can be used for ESD protection. Until now, effective ESD protection has been impossible to achieve in many cases. The use of the polysilicon strip 10 according to the invention as a switchable resistor allows these previous problems to be overcome.
For this purpose, the resistors R1, R2 are simply each replaced by a polysilicon strip according to the invention and of appropriate size, in which case the ESD protective elements E1 and E3 may be omitted at the same time. Since the parameters of the width d and the resistance R of these resistors can be varied independently of one another, it is possible, as shown in Figure 4, to design a 50 S2 resistor with a specific b/1 ratio, which has a suitable limit voltage Vtz, for example of several hundred volts, which is suitable for this application.
A suitable layout thus allows the polysilicon strip 10 to be used as the resistor R1 or R2, and at the same time as the ESD protective element E1 or E3, respectively. This leads to a significant saving in surface area, and at the same time to improved performance, since there is no need for any additional capacitance plates in the form of additional ESD
protective elements E1, E2.
A resistance layer of p+ polysilicon with 310 S2/sq will be used as a specific example for the design of a polysilicon resistor strip in a radio-frequency circuit arrangement 50 as shown in Figure 5. For electromigration reasons, b must be greater than micrometers. With the relationship (1) quoted above, b is 20 micrometers, so that the electromigration condition is satisfied, and an ESD resistance of 10 approximately 1 kV is achieved. Should greater widths b be required owing to electromigration or ESD
protection, the sheet resistance may be increased by changing the doping.
15 Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted to these, but may be modified in a large number of ways.
In particular, the present invention is not restricted to polysilicon or to a specific type of polysilicon doping. In addition, the quoted applications are only by way of example and may be extended as required to any fields of application where switchable resistors are required.
The strip may also have any other desired geometries.
Typical further fields of application for the method according to the invention are:
a. nonlinear pulse shaping of high-speed current pulses, for example in laser diode drivers;
b. fields of application of a DIAC, for example triggering of TRIACs and thyristors for high-current/high-voltage and smart power applications c. non-destructive dissipation of high-current S
pulses, for example of electrostatic discharges (ESD
protective elements), lightning protection circuits;
d. latch-up protection circuits;
e. applications in the high-current field, in which the power loss is intended to be limited for high current densities.
List of reference symbols 1 Wafer substrate Insulation layer 10; l0a-d Polysilicon strip 11, 12 Contacts 13, 14 Lines Controllable current source l,ll-14,b,h Length, width, height It; Vt, Vri, Current limit value; voltage limit value Vt2 Ik Critical current value 100, 200 Supply potential lines VDDP, VSSB Supply potentials E1, E6 ESD protective elements Al, A2 Radio-frequency pads R1, R2 50 ohm bias resistors DS Differential stage K1-K4 Circuit nodes
Claims (11)
1. Operating method for a semiconductor component having:
a substrate (1; 5);
a conductive strip (10; 10a-d) which is applied to the substrate (1: 5);
a first and a second electrical contact (11, 12; 11a-d, 12a-d), which are connected to the conductive polysilicon strip (10; 10a-d) such that this forms an electrical resistance in between;
with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (R diff1) up to a current limit value (I t) corresponding to an upper voltage limit value (V t) and, at current values greater than this, has a second differential resistance (R diff2), which is less than the differential resistance (R diff1).
a substrate (1; 5);
a conductive strip (10; 10a-d) which is applied to the substrate (1: 5);
a first and a second electrical contact (11, 12; 11a-d, 12a-d), which are connected to the conductive polysilicon strip (10; 10a-d) such that this forms an electrical resistance in between;
with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (R diff1) up to a current limit value (I t) corresponding to an upper voltage limit value (V t) and, at current values greater than this, has a second differential resistance (R diff2), which is less than the differential resistance (R diff1).
2. Method according to Claim 1, characterized in that the strip (10; 10a-d) has a sheet resistance which is in the range between 100 and 1000 ohms per square.
3. Method according to Claim 1 or 2, characterized in that the strip (10; 10a-d) has a cuboid shape with a length 1, a width b and a height h.
4. Method according to one of the preceding claims, characterized in that the strip (10; 10a-d) is formed from a number of strip elements (10a-d) with different dopings and/or lengths (11-14), with the strip elements (10a-d) being combined in series so as to produce a predetermined voltage limit value (V t).
5. Method according to Claim 4, characterized in that the strip elements (100a-d) are alternately p-doped and n-doped.
6. Method according to Claim 5, characterized in that the alternate doping creates additional diode forward-bias thresholds in the current path.
7. Method according to Claim 5, characterized in that the alternate doping creates additional diode breakdown thresholds in the current path.
8. Method according to one of Claims 3 or 4, with the voltage limit value V t being set in accordance with the relationship V t = R b (k/R sq) 1/2, where R is the resistance, b is the width, k is a constant and R sq is the sheet resistance of the strip (10; 10a-d).
9. Method according to one of the preceding claims, with the semiconductor component being used as an ESD
protective element.
protective element.
10. Method according to Claim 9, with the semiconductor component being used with two functions, as an ESD protective element and as a bias resistor, in a radio-frequency circuit arrangement (50).
11. Method according to one of the preceding claims, with the strip (10; 10a-d) being formed from doped polysilicon as the semiconductor material.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10134665.4 | 2001-07-20 | ||
| DE10134665A DE10134665C1 (en) | 2001-07-20 | 2001-07-20 | Operating method for semiconductor element has differential resistance switched to lesser value above given current limit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2393668A1 true CA2393668A1 (en) | 2003-01-20 |
Family
ID=7692038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002393668A Abandoned CA2393668A1 (en) | 2001-07-20 | 2002-07-16 | Semiconductor component |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6905892B2 (en) |
| JP (1) | JP2003133428A (en) |
| KR (1) | KR100525012B1 (en) |
| CN (1) | CN1167130C (en) |
| CA (1) | CA2393668A1 (en) |
| DE (1) | DE10134665C1 (en) |
| FR (1) | FR2827706B1 (en) |
| GB (1) | GB2382462B (en) |
Families Citing this family (51)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6919592B2 (en) * | 2001-07-25 | 2005-07-19 | Nantero, Inc. | Electromechanical memory array using nanotube ribbons and method for making same |
| US6706402B2 (en) | 2001-07-25 | 2004-03-16 | Nantero, Inc. | Nanotube films and articles |
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| US7583526B2 (en) * | 2003-08-13 | 2009-09-01 | Nantero, Inc. | Random access memory including nanotube switching elements |
| US7330709B2 (en) * | 2004-06-18 | 2008-02-12 | Nantero, Inc. | Receiver circuit using nanotube-based switches and logic |
| US7161403B2 (en) * | 2004-06-18 | 2007-01-09 | Nantero, Inc. | Storage elements using nanotube switching elements |
| WO2006121461A2 (en) | 2004-09-16 | 2006-11-16 | Nantero, Inc. | Light emitters using nanotubes and methods of making same |
| TWI348169B (en) * | 2004-09-21 | 2011-09-01 | Nantero Inc | Resistive elements using carbon nanotubes |
| WO2006065937A2 (en) * | 2004-12-16 | 2006-06-22 | Nantero, Inc. | Aqueous carbon nanotube applicator liquids and methods for producing applicator liquids thereof |
| US8000127B2 (en) * | 2009-08-12 | 2011-08-16 | Nantero, Inc. | Method for resetting a resistive change memory element |
| US9390790B2 (en) | 2005-04-05 | 2016-07-12 | Nantero Inc. | Carbon based nonvolatile cross point memory incorporating carbon based diode select devices and MOSFET select devices for memory and logic applications |
| US9287356B2 (en) | 2005-05-09 | 2016-03-15 | Nantero Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
| US8513768B2 (en) * | 2005-05-09 | 2013-08-20 | Nantero Inc. | Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same |
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| TWI324773B (en) | 2005-05-09 | 2010-05-11 | Nantero Inc | Non-volatile shadow latch using a nanotube switch |
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| US7915637B2 (en) | 2008-11-19 | 2011-03-29 | Nantero, Inc. | Switching materials comprising mixed nanoscopic particles and carbon nanotubes and method of making and using the same |
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| US8551806B2 (en) * | 2009-10-23 | 2013-10-08 | Nantero Inc. | Methods for passivating a carbonic nanolayer |
| US8895950B2 (en) | 2009-10-23 | 2014-11-25 | Nantero Inc. | Methods for passivating a carbonic nanolayer |
| WO2011100661A1 (en) | 2010-02-12 | 2011-08-18 | Nantero, Inc. | Methods for controlling density, porosity, and/or gap size within nanotube fabric layers and films |
| US20110203632A1 (en) * | 2010-02-22 | 2011-08-25 | Rahul Sen | Photovoltaic devices using semiconducting nanotube layers |
| US10661304B2 (en) | 2010-03-30 | 2020-05-26 | Nantero, Inc. | Microfluidic control surfaces using ordered nanotube fabrics |
| DE202013001327U1 (en) | 2013-02-13 | 2014-05-14 | Harald Rudolph | Anti-theft device for a media receiving container |
| US9650732B2 (en) | 2013-05-01 | 2017-05-16 | Nantero Inc. | Low defect nanotube application solutions and fabrics and methods for making same |
| US10654718B2 (en) | 2013-09-20 | 2020-05-19 | Nantero, Inc. | Scalable nanotube fabrics and methods for making same |
| US9299430B1 (en) | 2015-01-22 | 2016-03-29 | Nantero Inc. | Methods for reading and programming 1-R resistive change element arrays |
| US9947400B2 (en) | 2016-04-22 | 2018-04-17 | Nantero, Inc. | Methods for enhanced state retention within a resistive change cell |
| US9941001B2 (en) | 2016-06-07 | 2018-04-10 | Nantero, Inc. | Circuits for determining the resistive states of resistive change elements |
| US9934848B2 (en) | 2016-06-07 | 2018-04-03 | Nantero, Inc. | Methods for determining the resistive states of resistive change elements |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3667228D1 (en) | 1985-03-29 | 1990-01-04 | Raychem Ltd | PROTECTIVE DEVICE FOR ELECTRICAL CIRCUITS. |
| DE3937329B4 (en) * | 1989-11-09 | 2004-10-14 | Atmel Germany Gmbh | Semiconductor device and its use |
| US5189387A (en) * | 1991-07-11 | 1993-02-23 | Electromer Corporation | Surface mount device with foldback switching overvoltage protection feature |
| JPH05267659A (en) * | 1992-03-19 | 1993-10-15 | Nec Corp | Semiconductor device |
| KR970011140B1 (en) * | 1993-12-08 | 1997-07-07 | 한국전자통신연구원 | Structure of resonant tunneling opto-electronic device |
| US5535156A (en) * | 1994-05-05 | 1996-07-09 | California Institute Of Technology | Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same |
| DE4434894C2 (en) * | 1994-09-29 | 1998-07-02 | Siemens Ag | Power semiconductor component with a monolithically integrated sensor arrangement and its production and use |
| JP3444045B2 (en) * | 1995-09-20 | 2003-09-08 | 株式会社日立製作所 | Semiconductor circuit, driving method thereof, and semiconductor element |
| US5708291A (en) * | 1995-09-29 | 1998-01-13 | Intel Corporation | Silicide agglomeration fuse device |
| JPH1092946A (en) * | 1996-09-12 | 1998-04-10 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
| JPH10270640A (en) * | 1997-03-26 | 1998-10-09 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JP3082714B2 (en) * | 1997-07-18 | 2000-08-28 | 日本電気株式会社 | Semiconductor device |
| TW511103B (en) | 1998-01-16 | 2002-11-21 | Littelfuse Inc | Polymer composite materials for electrostatic discharge protection |
-
2001
- 2001-07-20 DE DE10134665A patent/DE10134665C1/en not_active Expired - Fee Related
-
2002
- 2002-07-16 CA CA002393668A patent/CA2393668A1/en not_active Abandoned
- 2002-07-18 JP JP2002209383A patent/JP2003133428A/en active Pending
- 2002-07-19 KR KR10-2002-0042601A patent/KR100525012B1/en not_active IP Right Cessation
- 2002-07-19 GB GB0216883A patent/GB2382462B/en not_active Expired - Fee Related
- 2002-07-19 US US10/200,067 patent/US6905892B2/en not_active Expired - Lifetime
- 2002-07-19 FR FR0209195A patent/FR2827706B1/en not_active Expired - Fee Related
- 2002-07-22 CN CNB021268347A patent/CN1167130C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| GB2382462A (en) | 2003-05-28 |
| JP2003133428A (en) | 2003-05-09 |
| FR2827706B1 (en) | 2004-04-09 |
| US20030017676A1 (en) | 2003-01-23 |
| US6905892B2 (en) | 2005-06-14 |
| FR2827706A1 (en) | 2003-01-24 |
| DE10134665C1 (en) | 2002-09-05 |
| GB2382462B (en) | 2004-01-28 |
| CN1167130C (en) | 2004-09-15 |
| CN1399337A (en) | 2003-02-26 |
| KR100525012B1 (en) | 2005-10-31 |
| KR20030009223A (en) | 2003-01-29 |
| GB0216883D0 (en) | 2002-08-28 |
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