CA2408252C - Method and apparatus for pre-emptively arbitrating on an acyclic directed graph - Google Patents

Abstract

A bus arbitration scheme is implemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangement of nodes has one node designated a root while all other nodes have established parent-child relationships with the nodes to which they are linked.
Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer.
Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.

Description

_ 1 ._ METHOD AN~~ APPARATUS FOR PRE-EMPTIVELY ARBITRATING
ON AN ACYCLIC DIRECTED GRAPH
This is a divisional application of Canadian patent application Serial Number 2,151,369 which is the national phase application of PCT International application PCT/US93/12311 filed December 16, 1993.
BACKGROUND OF THE INVENTION
Field of the Invention The present invent:zan relates to computer. systems.
More particularly, the present invention relates to a method and apparatus f~.~r establishing and uti~izing a ~ .r WO 941153 PCTNS93I1?311 communications scheme between a plurality of arbitrarily assembled elements of a computer system.
Components within a given ctanputer system need the ability to convey signals amongst thelves. In very simple systems, it is possible to have each element of the system directly wired to all of the other parts of the system. However, in reality, in order to make computers expandable and to accommodate an unknown number of system parts, computer architects long ago developed the concept of a communications bus.
A bus is a communications path, such as a wire or wires, running throughout the computer system. Each component of the system need only plug into the bus to be theoretically connected to each of the other components in the system. Of course, each component cannot simultaneously comanunicate with other components because there may be only a single communications channel between the components. It is necessary when utilizing a communications bus to establish some form a sharing arrangement so that each component may use the bus to .
communicate with other components in an efficient manner r o., WO 94115302 PCTNS9311?311 that does not leave critical pieces of information from one component hanging, waiting.for bus access. The method by which components on the bus share the bus is generally referred to as a bus arbitration scheme.
In addition to the critical need to optimize the bus arbitration scheme so as to maximize tha flow of important information, the physical (and logical/electrical) configuration of the bus itself can and should be optimized to minimize system delays while remaining as flexible as possible.
In order to communicate with other components attached to a bus, each component must be equipped with hardware such as transmitting and receiving circuitry compatible with the comnrunications protocol implemented for the bus.
One such communications standard is described in IEEE
Standards Document P1399 entitled "High Perfas~nance Ser3a1 Hus", said document attached as Appendix A to this document. The standard described in P1394 is intended to provide a low cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals.
Prior art buses or networks required knowing what was being plugged in where. For example, the back of many w WO 94115302 PCTf1JS93112311 _q_ computers have specified ports for specific peripherals.
Some computers implement several buses, such as the Macintosh which uses a bus referred to as ADB for components like a mouse and keyboard and SCSI bus for other , peripherals. These.types of buses provide for daisy chaining elements together but connections are of limited topology. Other known buses/networks require that the nodes of the network be arranged in a ring, a loop which must be closed in order to operate. Finally, afar, or hub-and-spoke arrangements required that each node be directly linked to a central master. Each of the prior art systems lacks a desirable measure of flexibility.
It would be desirable, and is therefore sad object of the present invention, to be able to arbitrarily assemble elements of a computer .system onto a bus where the arbitrary topology can be resolved by the system into a functioning system without requiring a predetermined arrangement of components.

t .~

It is an object of the present invention to provide a . fair bus access arbitration scheme for a computer system bus or network in which the connections of nodes have been resolved into an acyclic directed graph.
It is also an object of the present invention to provide a priority bus access arbitration scheme for a computer system bus or network in which the connections of nodes have been resolved into an acyclic directed graph.
It is another object of the present invention to provide a method of token passing bus arbitration for a computer system bus or network in which the connections of nodes have been resolved into an acyclic directed graph.
It is yet another object of the present invention to provide a mechanism whereby a preemptive bus initialization may be triggered by any node in a network of nodes which are resolved into an acyclic directed graph when errors are detected or nodes are added or subtracted during operation.
These and other objects of the present invention are i~lemented in a system where an arbitrary assembly of nodes on a system bus have been resolved into an acyclic directed graph. The hierarchical arrangesaent of nodes has y n ~I

one node designated a root while all other nodes have established parent/child relationships with the nodes to which they are linked. Each node may have a plurality of connected child ports with a predetermined acknowledgment priority scheme established. Fair bus access arbitration provides for bus granting in a sequence corresponding to the predetermined port priorities allowing all nodes a turn on the bus. The root node may always assert its priority access status to gain bus access which is useful for accommodating a root node which requires isochronous data transfer. Alternatively, a token passing arbitration scheme may be implemented where the token for bus access is passed around the nodes according to the above-described predetermined port priority scheme. Preemptive bus initialization may be triggered by any node upon detection of a necessitating error or addition or removal of a connection to an existing node.
Accordingly, in one aspect, the present invention provides in a computer system comprising a plurality of components, the plurality of components each having at least one communications node wherein the communications nodes of the plurality of components are interconnected by communications links, the communications nodes and communications links comprising a bus of a directed v r ~ .r -6a-acyclic graph wherein one node is designated a root node, all nodes coupled to only one adjacent node being designated leaf nodes, all other nodes in the directed acyclic graph being designated branch nodes, the directed acyclic graph having established hierarchical parent-child relationships between all adjacent nodes proceeding from the root node down to any leaf nodes wherein a leaf node has only one parent node and all nodes adjacent to the root node are child nodes with respect to the root node but parent nodes with respect to other adjacent nodes, the root node being defined as having no parent node, a method of preemptive bus initialization comprising: propagating a "Bus Initialization" (BI) signal from any node determining that bus initialization is necessary; sustaining the BI
signal for a predetermined period of time; and propagating that signal throughout the directed acyclic graph to all nodes in the directed acyclic graph.
In a further aspect, the present invention provides in a computer system comprising a plurality of components, the plurality of components each having at least one communications node wherein the communications nodes of the plurality of components are interconnected by communications links, the communications nodes and communications links comprising a bus of a directed t, -6b-acyclic graph wherein one node is designated a root node, all nodes coupled to only one adjacent node being designated leaf nodes, all other nodes in the directed acyclic graph being designated branch nodes, the directed acyclic graph having established hierarchical parent-child relations ships between all adjacent nodes proceeding from the root node down to any leaf nodes wherein a leaf node has only one parent node and all nodes adjacent to the root node are child nodes with respect to the root node but parent nodes with respect to other adjacent nodes, the root node being defined as having no parent node, a method of preemptive bus initialization comprising: propagating a "Bus Initialization" (BI) signal from any node determining that bus initialization is necessary; sustaining the BI
signal for a predetermined period of time; and propagating that signal throughout the directed acyclic graph to all nodes in the directed acyclic graph.
In a still further aspect, the present invention provides a method fox a first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the method comprising:
determining an error condition in communication through -CC-the at least one links; sustaining a "Bus Initialization"
(BI) signal for a period of time to propagate the BI
signal from t:he f~.rst node to the <~t least one adjacent node in response to the: error condition; and performing bus initialization in :.ommunication with the at least one adjacent node.
In a still further. aspect, the present invention provides in a method for a first node to communicate with a plurality of adjacent TlUdeS through a plurality of point-to-point links connected from the first node to the plurality of ~~djacent nodes respectively, the method comprising: receiving <~ "Bus Initialization" (BI) signal.
from a second. node of ~~;,he plurality of adjacent nodes;
sustaining the BI signal for a period of time to propagate the BI signal. from the :~irst node to the plurality of adjacent nodes except the second node in response to said receiving the BI signal; and performing bus initialization in communicat_Lon with the plurality of adjacent nodes.

~ r ~~11 The objects, features and advantages of the present - invention will be apparent from the following detailed description in which:
ligutse 3 illustrates a block diagram of the hardware layer implementation utilized in accordance with the present invention.
liQ~s 2(sy-2(b) illustrate arbitrarily assembled collection of nodes, one being acyclic and the other including taultiple cycles.
ligt~s~ 3(s) is the arbitrarily assembled collection of nodes of Figure 2ia) undergoing the graph transfos~aation process in accordance with the present invention.
139ur~s 3(b)-3(d) illustrate alternative communications exchanges between nodes in implementing the present invention.
lignr~ 3(~) graphically illustrates the directed graph resulting from the arbitrarily assembled network of nodes of Figure 2fa).
ligurw 4 illustrates a symt~etrical graph arrangement which requires resolving a root contention.

~ r Figure 5 illustrates a directed acyclic graph with a possible unique address assignment order indicated.
Figures 6(a)-6(t) illustrate the process flow for carrying out the graph transformation procedure in accordance with the preferred embodiment of the present invention.

y , f y WO 9~II1Si0t PGTI~9311Z311 A method and apparatus for utilizing a bus having an . arbitrary topology are described. In the following description, many specific details are set forth such as various computer components in order to prowide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that the present invention may be practiced without such specific details. Tn other instances, well-known control structures and coding techniques have not been described in detail in order not to obscure unnecessarily the present invention.
Throughout this detailed description, numerous descriptive terms are introduced to provide metaphorical clarity to the description. For example, frequent references will be made to parent-child relationships between nodes in a given topology. The puspose of this is to provide the concept of "direction" to the finally resolved graph. As will be described, once an arbitrary topology has been reduced to an acyclic directed graph, there will be one node identified as the "root" node. The root node will not have a parent node, all nodes logically immediately adjacent to the root node are the child nodes of the root.. The "tree" metaphor is completed by the inclusion of nodes referred to as "branches" and "leaves".
The bus architecture described herein, though described with reference to components for a single computer, i.n general has a broader scope. The present invention for defining the bus topology may be applied to any arbitrarily assembled collection of nodes linked together a~; in a network of devices. One point that must be noted i~; that it is necessary to distinguish a node from a physical. computer r_omponent. Each component to reside on the bus wi7.1 have associated with it at least one node physical layer contzol.ler. In certain circumstance, a given component may advantageously be associated with multiple nodes but in the usual case there will be a one-to-one corz:espondence between devices or components on the bus and nodes.
Refer:cing now to $igars 1 a block diagram of a node is illustrated. 'The physical implementation of a node is somewhat: arbitrary. In the preferred embodiment implementation of the present invention, the nodes are designed to comply with the IEEE P1394 j~,gh PeTforr a Serial Bus communications protocol. The node 10 includes arbitration state machine logic 11. This arbitration state machine logic r. ~, WO 94IIS302 PCTlU593l1?31I

incorporates all the logic circuitry for carrying out the methodologies and algorithms to be described herein. The circuitry may comprise a programmable logic array tPLA) or be uniquely designed to carry out the functions described herein. Those skilled in the art, once described the functions to be carried cut by the node logic will be able to implement the present invention without undue experimentation. The node, by meats of its logic, shall implement the minimum arbitration protocol including the bus initiaiizativn, tree identification, self identification, and the bus arbitration functions, all to be described in detail further herein.
The node 10 shown in 1'igns~ 1 also includes transmission multiplexers 12 sad 13 and data transmitter, receiver and resynchronizer 14. The node illustrated in ligur~ 1 is coupled to local host 15. Local host 15 may be any device one wishes to attach to the bus such as a disk drive, CPU, keyboard or any other component which needs to comutunicate with other components in the system.
The node 10 communicates with other nodes through communications links. A link is a connection between two ports and in incnediate practical terms is a cable segment but in general it may be implemented as any physical communication channel. A link shall be able, at minimum, .
WO 91l1536i2 FCTIIJSl3l12311 to provide a halt duplex communication channel between the two ports which it connects. A port is the interface between a node and a link. Zn accordance with the present invention, a port must have the ability to transmit and receive data and arbitration signaling. A port needs to be able to determine whether or not it is connected to another port through a link. One method of facilitating this is by having connected ports apply a biasing voltage through the link which is detectable by the port at the other end of the link. Thus, if a port has a Link attached which is not connected to a port at the other end, a naked link, the port will determine that it is not a connected port. In piQare 1, the illustrated node 10 has thr~se external ports 21, 22 and 23 with connecting links 17, 18 and I9, respectively.
Some of the rules of implementation for nodes in order to i~leaieat the present invention are that a node may have one or more ports. A node shall be able to transmit and receive data on any one of its pons. A node shall be able to receive data on one and only one of its enabled ports at a time and be able to retransmit this data on all remaining enabled ports. A node shall be able to receive and transmit signaling messages through all of its ports simultaneously and independently. Separate signaling Y v ! A
WO 94115302 PCTIUS9311?311 transceivers, encoders and decoders are required for each port of a node. A minimum implementation node does not require a local host device. For example, such a node may function as a cable extension. From hereon devices and local hosts will be ignored and all references to bus topology will refer to nodes and node connections through various ports.
lignras 2ta) std ~(b) illustrate arbitrarily assembled collections of nodes. From hereon, nodes will be illustrated merely as circles, but are deemed to each incorporate elements equivalent to those described with respect to liqurs 1. Note, however, that each node may have more or less than the three external ports shown in that figure. The lines 111ustrated connecting each of the nodes are the method by which links are shown. Ports are not illustrated, but are impliedly the interface where a link and a node connect.
The bus arbitration methodology to be described herein requires that the arbitrary topology be resolved into an acyclic directed graph. In an arbitrary topology graph a collection of nodes and links may form a cycle. A cycle W~ ~1~ ~~~~~11 exists if starting from a specific node in the graph it is possible to return to the same node by traversing links and nodes without any link being traversed twice. ligare 2(:) illustrates an acyciic graph because none of the nodes illustrated are connected within a loop. lig~x~
2(b), however, is not an acyclic graph because the region in bounding box 25 contains a collection of nodes, 90-97 which Eons multiple cycles. The bus arbitration methodology to be described requires that there be no cycles, so a method of user intervention to resolve cycles will also be described further herein.
In addition to the require~aent that a graph be acyclic, it must also be directed. A directed graph is one in which a hierarchical arrangement has been established between adjacent nodes. Initially, there are no established parent-child relationships between nodes. That is, for example, node 31 may be the "parent node" for node 34, or be the "child nude" for node 34. Thus, it is necessary to take a given arbitrary topology graph and transform it into an acyclic and directed graph. The methods described herein will Work to perform this transformation for any give arbitrary topology, regardless of the number of nodes or how they are physically linked . , . .
WO lAll~Z PCTN551311?3I1 and regardless of the signaling propagation time along the links.
Initially, the process of transforming an acyclic arbitrary topology graph into a directed graph will be described. The case where cycle resolution is required will follow, lign~se 3 (a) shows the arbitrary graph of lig~tre 2 (a) wherein the nodes and links have status labels and com~aunicated signals are indicated for the graph transformation process for directing a graph. It is instructive at thin point to describe signal communications between nodes. ligut~ 3(b) illustrates twc nodes 50 and 51 (hereinafter node A and node 8, respectively) coupled by link 52. A~ described, the link is the conaaunications channel coupling transceiver ports of the respective nodes as described above with reference to ligur~ 1. During the graph transformation process, it becomes necessary for nodes to establish parent-child relationships with adjacent nodes. Two nodes are said to be adjacent nodes if there is at least one link connected between a port of the first node and a port of the second node. In ligns~s 3(b)-3(d1 it will be assumed that the relationship to be WO 94!15302 PCTIUS93/1?311 -ls-resolved is that node B is the parent of node A and that it is appropriate for the nodes to establish that relationship.
Prior to a direction being established, when it become appropriate for node A to establish node B as its parent, node A will transmit from its port to which link 52 is coupled the signal "You Are My Parent" (YAMP). This message content may take any form, so long as node A knows that it is signaling YAMP and node B is capable of understanding that the received message is YAMP. When YAMP
signal 53 is received by node B, node 8 will respond to node A by sending "You Are My Child" (YAMC) through link 52 to node A. The arbitration state machine logic 11 of node A will keep track of the time delay between sending YAMP
signal 53 and receiving YAMC signal 54. The time measured signifies twice the propagation delay between nodes A and B. Upon receiving the YAMC signal, node A will reapoad with a "You Are My Child Acknowledged" (YAMCA) signal 55.
This provides node B with the ability to also determine the propagation time delay between the nodes equal to the time delay between sending YAMC and receiving YAMCA. For half duplex communication links, the YAMCA message also has the effect of properly orienting the comtaunication channel.

. Y , For full duplex communicationa channels the three logical messages, YAMg, Y1~MC and YAMCA can alternatively be relayed by only two signal transmissions. In ligar~ 3(c) this situation is illustrated where node A asserts the YAt~
signal 56 continuously until it receives the return YAMC
signal 57. The YAMCA Signal is logically transmitted to node B when the YAMf signal is detected as no longer arriving.
The use of this described triple asynchronous message exchange provides a mechanism by Which both nodes involved in the message exchange can determine the propagation time delay through the link. This delay value is used in resolving contention events to be described further herein as well as during normal bus arbitration to optimize bus performance. The dynamic extraction of this parameter is not mandatory. As an alternative a maxiiaum propagation time delay can be apriory defined at the expense of optimum bus performance .
Once nodes A and 8 have exchanged messages signifying that node H is the parent of node A, the link can be said to be directed. Node A within its logic labels its port to Which link 52 is coupled as a parent port (it talks to a garent node) and node B labels its port to which link 52 is coupled a child port tit talks to a child node). It is important to maintain the labels that ports achieve because the methods to be described below will be in terms of the labels assigned to nodes and ports at a given time. A
short hand graphical notation is illustrated in Figure 3(d) where the direction arrow 58 indicates that node B is established as the parent of node A and the link is directed.
Directioa Dstsrmiaet~.on Referring back now to Figurs 3(a) and to process Figurem 6(a)-6(f), the process of directing the overall arbitrary topology will now be described. It is necessary to introduce a few more colorful definitions to aid in explaining the topology transformation process. First, a "leaf" node is defined as a node with only one connected port. A node recognizes its status as a leaf node as soon as it is initialized after power-up or other bus initialization. A "branch" node is a node which has at least two connected ports. Though all but one of the connected ports a branch node will have received the VAMP
signal and have acknowledged it. Through its remaining port, a branch node has sent the VAMP signal thus establishing that it has a parent node. A nade does not ,. ~, P~~~11 achieve branch status until it has established that it has one parent (a node can have only one parent node) and all its other ports are connected to child nodes. Prior to achieving branch status, a node is considered a "cycle"
node because until it is determined to be a branch the possibility exists that the node is part of a cycle which makes establishing direction impossible.
The graph transfozmatian procedure begins at step 60 upon bus initialization (power-up or instigated) at which time the leaf nodes in the arbitrary topology recognize at step 61 and label themselves at step 68 as leaf nodes by determining that they have only one connected port at decision box 66. In the graph depicted in ls~re 3(~), nodes 33, 35, 36 and 37 are leaf nodes which, once initialized, at step 69 each transmits the YAK signal through its only connected port to its adjacent node. The nodes receiving these signals will then propagate the YAMC
signals back to the leaf nodes at step 70, thus establishing a direction for the given link between respective parent-child pairs when the YAMCA communication is completed. At step 71 each leaf node labels its one connected port as a parent port and each receiving port on the parent node is labeled a child port.

WO q4115302 PCTN593/IZ3I1 The nodes on the graph which are not Initially leaf nodes are initially considered "cycle nodes" for the reason described above and proceed according to the Cycle Node Procedure 63. Any cycle node which has labeled all but one .
of its connected ports as child ports then propagates the YAMP signal from its remaining unlabeled port at step 85.
~ihen that direction is established for the link, the cycle node then becomes labeled a branch node. Thus, after leaf node 37 establishes that node 34 is its parent, node 34 has only one unlabeled port (having labeled the link connection to node 37 as being through a child port) so node 34 broadcasts the VAMP signal to node 31, resulting in node 39 becoming a branch node. Likewise, once node 31 has identified that nodes 33 and 34 are its children, node 31 broadcasts the YAMP signal to node 30. When one node has received through all of its ports the YAMB signal at decision box 75, that node becomes the root node. In lignre 3(a) aftez node 30 has received the YAMP signals from nodes 31 and 32, its label changes from being a cycle node to being the root node. In the graph of 1'iyure 3(s~, it is not necessarily the case that node 30 would become the root. If some of the links in the tree provided long propagation delays, node 30 might have received a YAMP
signal on one part and then transmitted a VAMP signal through its other port. Any of the nodes maY become the ~~~~l~l ~

root, even a leaf, the root property taking precedence.
ligar~ 3(~) shows the resulting directed graph in response to the communicated signals shown in liQnss 3(a) - with each node labsled and the directions indicated by dark arrows.
Tn certain circumstances a root contention situation may arise. This may happer~ for example in the case where the arbitrary topology has a symmetrical arrangement to it such as that shown in !ice i. In tha arbitrary graph illustrated in lis~nsa ~, nodes 160 and 161 have each established that it is a parent to the two leaf nodes to which it is coupled. Then, each has propagated the YAMP
signal to the other at nearly the same time. The root contention situation is recognized by both nodes involved at decision box 86. Each node is receiving a signal which designates it as a parent while it has sent the same signal out through the same port. Each of the contending nodes responds to the other with the YAMC signal at step 91 which allows each to determine the "decision time period" which is equal to twice the propagation time between the nodes.

.. r.
wo rcr~ns~m The root contention situation is resolved by utilizing a random decision mechanism incorporated on each arbitration state machine logic unit 11 0~ each node. For every "decision time period" that elapses, each node will randomly decide at step 92 (with a 503 probability) whether to again transmit the Y~ signal to the other. Almost certainly within a finite number of the cycles, one node will decide to designate the other its parent without that one reciprocating. The one that is designated the parent becomes the root at step 95. Alternatively, predetermined selection criteria values may be assigned to nodes, the larger or smaller determining which dominates in a contention event. The dynamic determination of the "decision tisae period", while it offers optimus< performance is not essential in implementing the present invention. As an alternative an apriory defined ~decision time period"
may be used as long as it is greater than the worst case link propagation that can be encountered in any bus using this algorithm. The sane method used to resolve root contentions will also be used to resolve other contention events to be described further herein.

v, wo ~u~z pcrrt~nnz3u As described above, the result of the graph . transformation process is the assignment of the root attribute to one and only one node in the graph. The root node will have the ultimate decision in the bus arbitration scheme to be described and therefore can accsss the bus with maximum priority without the use of special priority time gaps. It is often desirable to be able to assign the root property to a predetermined node either when it is manufactured or dynamically~tduring run tisae) to optimize a given system. A given bus may include a node which requires isoehronous data transfer. Isoehronous data is data that must be transmitted at a given time to be of any value. For example, music from a compact disk needs to be transferred and output in the order in which it is to be heard and with no significant delays, unlike data files which may be transferred piecemeal and not necessarily in order.
Nodes can be classified into three categories with respect to root designations. These designations iaay be applied during manufacturing by hard-wiring the designation into the device, programming the arbitration state machine logic or by higher level software making the decision then ~~;1 initiating a reboot while preserving that decision. The three designations that a node may be assigned with respect ' to being designated a root are: nodes that do not want to be root, nodes that may (should) be root and nodes that shall be root. These designations are tested for at steps 81 and 83. A node designated in the first category will begin the graph transformation procedure as soon as it is directed to do so. This will usually be iaaaadiately following the completion of the bus initialization procedure. A node from the~second category will delay the beginning of the graph transfoxmation procedure for a predetermined amount of time after it is directed to begin the procedure at step 84. 8y this delay, the node increases its chance of becoming the root. (The YAl4p signals are more likely to propagate to it due to the delay.) Despite the added delay, it is still possible that a "may be root" node will not wind up being designated the root. This will depend on the given topology and message propagation delays. The amount of delay can be defined during design to be greater than a reasonable worst case propagation delay through a fairly complex graph.
A node from the third category of root designation possibilities may only recognize the fact that it must be the root after the graph has already been transformed and _ ,, WO 9411: PCTIUS3311I31i all nodes have identified themselves. The arbitration state machine logic may make this determination or software running on the host system. When this occurs, the node that has to be root agrees with all other nodes on the bus that it is going to be the one and only root and restarts the graph transformation process by signaling a preemptive bus initialization signal which is described further herein. The node then waits at step 82 to become the root and does not participate in the graph transformation until it has received. the YAI~ signal on all of its ports, thus forcing it to be designated the root.
Once the root has bean determined, the graph can be said to be directed. There is a defined relationship existing between all adjacent nodes an the graph.
The procedures descri3aed above far directing a graph will only wozk for an acyclic graph. If there are cycles in the arbitrary topology, they must be broken by the procedure beginning at step 80. The existence of a cycle is detected at step 79 when, after a predetermined time-out period has elapsed, a node is still labeled a cycle node rather than a leaf, branch or root. The "cycle detect"

~~11 timing starts immediately after the end of the bus initialization function. The time-out period need be no longer than the worst curse duration of the graph ' transformation process tadding in delay time for a "may be root" node snd a possible root contention event).
The "cycle detect" time-out event does not have to occur synchronous for all nodes of a graph as all message exchanges are asynchronous events. As such, it is possible for a node which has not yet reached its "cycle detect"
time-out event to receive a message indicating that cycle resolution is ongoing. Such a node will teratinate its cycle detect time-out interval and begin the appropriate cycle resolution process.
The nuethod of cycle resolution in accordance with the present invention requires the user of the assembled collection of nodes to intervene. When a node encounters the "cycle detect" time out the system user may be notified at step 100 of ligur~ 6(a) through an output device that a cycle exists and which nodes are tben involved. The user will then be instructed to disconnect links to eliminate whatever cycles are present. The user will then return control to the graph transformation procedure.

W~ ~l~ ~~~~1~

Once each of the loops is broken, and no cycles remain, the procedure for transforming the graph as described in the earlier sections may proceed until the entire graph is both acyclic and directed.
Once a directed acyelic graph has bean established from the original arbitrary topology, it is then possible to assign unique physical addresses to each node on the graph. This process begins with all leaf nodes requesting the bus by transmitting through their single connected ports the Bus Request (BR) signal. The parent node receiving the signal will wait until it has received the BR
signal from all of its child ports and then will propagate the BR signal to its garent. The BR signals will propagate through the gzaph until the root has received the BR signal from all of its children. Once the root has received a bus request through all of its child ports, it will make a decision for granting the bus through one port and propagating a Bus Denial BBD) signal through its remaining child ports. The method for selecting which bus request to grant may be an apriory decision such as that described above where, for example, ports art selected from left to WO 9411Si0Z pCT~l133I1 right or based on port numbering, etc. The Bus Grant (BG) signal will be trans~aitted from the root to its requesting child. If that requesting child is itself a parent node which has propagated the bus request from one of its .
children, it will send the bus denial signal through all but one of Sts child ports in the same predetermined fashion as described above. Eventually ons la~a~f node will receive the bus grant signal to which it will reply with a Hus Grant Acknowledged (BGA) signal which will be propagated back to the root node. The propagation of the BD and HGA signals serve to~orient the comeaunication links which may be necessary for the case of half duplex communications channels. All of the denied nodes will then wait for activity by the node which finally receives the BG
signal.
The node which is finally granted access to the bus will transmit an address assignment packet. The node will transmit this packet on the bus and it will be received by all other nodes, each of which will count the number of address packets they receive. The transmitted address packet may have any arbitrary information. A node's unique physical address will be based on the numfaer of address packets a node has counted before it transmits an address packet. Thus, no two nodes will acquire the same physical wo gum ~rvssa~tt3u address despite not having address information assigned in advance. The actual composition of the address packet is arbitrary and may be any bit stream efficiently utilizable . by the system. After transmitting the physical address assignment packet, a node will transmit a "Child ID
Completed" signal iCIC) signal. The parent node receiving this on its child port will then transmit the "Child Identification Completed Acknowledgment" tCICA~ signal and label the port as an identified child port. In response to the next HR signal propagation, the parent of the node which has dust identified itself will then Select its next child to transmit the physical address packet. Once all the child nodes of a parent node have identified themselves, the parent node will request the bus and, when granted the bus, will propagate its physical address assignment packet. This procedure will continue following the predetermined selection criteria until all nodes determine a unique physical address assignment by counting.
Tignre 5 illustrates the graph of figure 3(e~ in which a left-to-right predefined selection criteria is implemented.
The nodes are uniquely assigned addresses where node 33 receives the first and as described, the root node 30 receives the eighth and last address.

wo mss rc~rn~nz~m When this procedure is completed, each node in the graph will have a unique physical address, ~rhich need not have been determined in advance and which may be utilised for system management or other purposes.
The process of node self identification essentially follows the Same routine as the physical address assignment procedure described above. ,As each node transmits its physie:al address assignment packet, that packet may include further information such as identification of the physical device comprising the identification of the local host related to the node, how much power it requires, and, for example. whether it supports a "soft power-oa" attribute, etc. In fact, the node self-identification information may serve as the physical address assignment packet because the practice of sending any information at all provides the basis for counting to yield unique physical addresses.
With respect to the node self-identification packet, the particular information concerning the node need only be "listened" to by those nodes affected by the nature of the announcing node. This procedure, as with the alcove, WO f1/15~ pGTNSl31Lt311 proceeds until all nodes have transmitted their node self identification information.
The method of topology mapping follows along the same lines as physical address assignment and node self-identification. This procedure thus has each node, when it is going through the address assignment or node self-identification process, further transiait i.aforsaation concerning all of its ports such as the number of child ports it has and whether or not it has aay disabled ports.
With respect to disabled ports, it may be desirable to implement a comtaunication protocol between ports that are disabling so that they can Identify from whom they are disabled. Thus, when a port identifies a disabled port it will give an identifier indicating its own ID as well as the port iD from which it has become disabled.
Hy assembling all the topology information about all the ports received during the topology mapping procedure, the bus server, host or any software level application may logically reconstruct the resolved bus topology. This is useful for many purposes including implementing redundancy where if a link unexpectedly goes down, previously disabled WO 94/1902 PCTNSl3/12311 links may serve to prevent the loss of communication channels to any nodes.
Once the topology snapping, node self identification or physical address assignment routines have eo~leted, the bus can be considered up and running. One arbitration scheme implemented in accordance with the present invention is that of fair bus access., When a node desires access to the bus, it sends through its parent port (unless it is the root) a bus request (BR) signal. The parent, upon receiving the 8R signal from one child sends a bus denied signal (BD) through all its other child ports. The parent then propagates the BR signal upward through its parent until the signal reaches the root. The rant issues a bus grant signal (BG) responsive to the first BR signal it receives and sends the HD signal through all of its other child ports which propagate downward thereby orienting the links. The BG signal propagates downward through the graph until it reaches the requesting node which then sends Bus Acknowledge (BA) signal followed by the packet of information that the node needed to send on the bus. When n Y
WO PCTJ~Sl3I1Z3i1 the packet is completed, all nodes return or enter into an idle state.
In the case where the root receives nearly simultaneous requests for the bus, the predetermined selection criteria for the root node will be used for granting to one of the nodes bus access. This may be the same predetersained priority selecting criteria as described above.
A further aspect of fair bus access arbitration is that a parent node has priority aver its children. Thus, when a parent node wants the bus, it sends the HD signal through all of its child ports, then propagates the HR
signal up toward the root. One potential problem with this mechanism is that if the parent has a large quantity of information to traasmit an the bus a child node may have trouble getting adequate bus access. There is therefore introduced a gap system which is widely used and well-known in the art. After a made has utilized the bus, the node must wait for one gap period before it can again request 'the bus. This gives equal chance of being granted the bus to every node on the bus independent of its topological placement on the bus. In order to guarantee a fair arbitration protocol the length of the gap has to be greater than the worst case signal propagation delay ~ ~ r WO ~~ PCT~31123~1 through the bus. The gap value can be predetera4ined and hard-wired into the node logic but such an approach will result in all but the most extreme case in a sub optimal utilization of the bus. The topology mapping capability together with the measurement of the propagation delay between adjacent nodes performed during the graph transformation phase enables the calculation of an optimal fair gap that will maximize the bus performance for any specific implementation.
In the bus arbitration scheme impl~em~ented in accordance with the above fair bus access arbitratioa, it may be desirable that the root always have bus priority.
When this is impletaented, the root node may grant the bus to itself at any time. This is done by first sending the BD signal dawn through all of the nodes in the graph.
Priority bus access for the root is very useful for the case where the root node is required to perform isochroaous data transfer.

WO 94115302 PCTf~iS43I1Z311 As an alternative to the fair and priority bus access arbitrations schemes described above, the present inventiow may be utilized in implementing a token passing bus arbitration scheme. Metaphorically speaking, token passing bus access refers to the nation that a node may communicate on a bus when it is in possession of a token that is passed between nodes. The token is passed from node to node in a cyclic fashion so that each node receives the bus in a predetermined point in the cycle. Token passing is implemented in the present invention in following the same manner as the physical address assignment routine described above. The predetermined selection nsschanisms implemented are used to select the order in which the token will be passed from node to node. This order resembles the order as shown in 1'iQnre 5 which dictates the order of unique address assignment. Each node, when it is assigned the token will propagate its information packet on the bus while the remaining nodes listen. The node will then pass the token to the next logical node based on the predetermined sequencing ~thod as described above.

WO 9411902 ~CZ'NSl3ILt311 An important feature that may be implemenlted in accordance with the present invention is the notion of preemptive bus initialization. The state machine logic incorporated on each node is capable of triggering a bus initialization t8I) signal to be propagated from the node through all of its parts upon certain canditians. When a node has determined it is necessary to signal a bus initialization condition, it Trill propagate the BI signal out through all of its ports for a length of time sufficient to guarantee that all adjacent nodes have received it and then released. A node will then go into the initiating procedures which then lead to the graph transformation process in the above described procedures.
There are a number of situations which may make it necessary or desirable to trigger a preemptive bus initialization. First, this may be a node response to an unforeseen error. Additionally, at the host level, it may be determined that a different node should acquire the root attribute, for example, an isochronous data transfer node.
This assignment will be preserved throughout the bus initialization routine thereby causing the desired nods to wait during the transform procedure until it receives the Wa 9411902 fCTN593J11311 root designation. Another condition leading to a preemptive bus initialization may be the breakage of a link, in which case it may be necessary to calculate a new acyclic directed graph for the attached nodes. Finally, an important situation in which a pree~tive bus initialization should occur is when a device is added to the network, referred to as "hot addition" of peripherals.
The port to which a new device is connected will detect the presence of a new node and trigger a bus initialization which will be transparent to the user of the system but which allows the addition and subtraction of peripherals, for example, without having to shut down and repower. A
new acyclic directed graph is calculated which includes the presence of the added node. It is possible that upon removing certain nodes. it will not be necessary to trigger a bus initialization, for example, when a leaf node is removed, there is no harm to the network. Flowever, if a branch node is disengaged from an operating bus, it is likely to be necessary to reconfigure the graph.
Although the present invention has been described in terms of preferred embodiments, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit W4 9A/1530Z PC'Z'N993112311 and scope of the invention. The invention should, therefore, be n~asured in terms of the claims which follow.

Claims (17)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. In a computer system comprising a plurality of components, the plurality of components each having at least one communications node wherein the communications nodes of the plurality of components are interconnected by communications links, the communications nodes and communications links comprising a bus of a directed acyclic graph wherein one node is designated a root node, all nodes coupled to only one adjacent node being designated leaf nodes, all other nodes in the directed acyclic graph being designated branch nodes, the directed acyclic graph having established hierarchical parent-child relationships between all adjacent nodes proceeding from the root node down to any leaf nodes wherein a leaf node has only one parent node and all nodes adjacent to the root node are child nodes with respect to the root node but parent nodes with respect to other adjacent nodes, the root node being defined as having no parent node, a method of preemptive bus initialization comprising:
propagating a "Bus Initialization" (BI) signal from any node determining that bus initialization is necessary;

sustaining the BI signal for a predetermined period of time; and propagating that signal throughout the directed acyclic graph to all nodes in the directed acyclic graph.

2. A method for a first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the method comprising:
determining a first determination that a parent-child relationship between the first node and one of the at least one adjacent node is to be changed;
sustaining a "Bus Initialization" (HI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the first determination; and communicating with the at least one adjacent node to perform bus initialization.

3. A method as in claim 2 wherein said communicating comprises:
delaying for a period before propagating a "You Are My Parent" (YAMP) signal from the first node to any of the at least one adjacent node to increase a chance of the first node to become a parent of the at least one adjacent node.

4. A method as in claim 3 wherein the period is sufficiently long such that the first node receives a "You Are My Parent" (YAMP) signal from each of the at least one adjacent node to become a parent of the at least one adjacent node.

5. A method as in claim 2 wherein said communicating comprises:
determining an unique address of the first node for communication with the at least one adjacent node.

6. A method for a first node to communicate with at least one adjacent node through at least one paint-to-point link connected from the first node to the at least one adjacent modes respectively, the method comprising:
determining a change in status of a second node in communication with the first node through a point-to-point link;
sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the change; and performing bus initialization in communication with the at least one adjacent node.

7. A method as in claim 6 wherein the change in status comprises one of:
a) addition of the second node in communication with the first node; and b) removal of the second node in communication with the first node.

8. A method as in claim 6 wherein said performing bus initialization comprises:
determining a parent-child relationship between the first node and each of the at least one adjacent node.

9. A method as in claim 8 wherein said performing bus initialization comprises:
determining an unique address of the first node for communication with the at least one adjacent node.

10. A method for a first node to communicate with at least one adjacent node through at least one point-to-point link connected from the first node to the at least one adjacent nodes respectively, the method comprising:
determining an error condition in communication through the at least one links:
sustaining a "Bus Initialization" (BI) signal for a period of time to propagate the BI signal from the first node to the at least one adjacent node in response to the error condition; and performing bus initialization in communication with the at least one adjacent node.

11. A method as in claim 10 wherein said performing bus initialization comprises determining a parent-child relationship between the first node and each of the at least one adjacent node.

12. A method as in claim 11 wherein said performing bus initialization comprises determining an unique address of the first node for communication with the at least one adjacent node.

13. A method for a first node to communicate with a plurality of adjacent nodes through a plurality of point-to-point links connected from the first node to the plurality of adjacent nodes respectively, the method comprising:
receiving a "Bus Initialization" (BI) signal from a second node of the plurality of adjacent nodes;
sustaining the BI signal for a period of time to propagate the BI signal from the first node to the plurality of adjacent nodes except the second node in response to said receiving the BI signal; and performing bus initialization in communication with the plurality of adjacent nodes.

14. A method as in claim 13 wherein said performing bus initialization comprises:
determining a parent-child relationship between the first node and each of the plurality of adjacent nodes.

15. A method as in claim 13 wherein said performing bus initialization comprises:
determining an unique address of the first node for communication with the plurality of adjacent nodes.

16. A method as in claim 13 further comprising:
determining a first determination that bus initialization is necessary; and sustaining a BI signal for a period of time to propagate the BI signal to the plurality of adjacent nodes in response to the first determination.

17. A method as in claim 16 wherein the first determination is in response to one of:
a) determining that a parent-child relationship between the first node and one of the plurality of adjacent nodes is to be changed;
b) determining an adjacent node becoming engaged to the first node for communication;
c) determining an adjacent node becoming disengaged from the first node for communication; and d) determining an error condition in communication through the plurality of links.