CA2430497C - Synchronous network traffic processor - Google Patents

Abstract

A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protocols on the fly. The synchronous network traffic processor includes a data compare unit (110) a data modify unit (120) an execution control unit (130) a peripheral unit (140), an input pipeline unit (150), an instruction memory (160) and a bank of general purpose registers (170). An embodiment of the synchronous network processor described has a low gate count and can be easily implemented using programmable logic. An appropriately programmed synchronous network traffic processor may replace modules traditionally implemented with hard-wired logic or ASIC.

Description

SYNCHRONOUS NETWORK TRAFFIC PROCESSOR
The present application claims priority to United States Provisional Patent Application entitled "SYNCHRONOUS NETWORK TRAFFIC PROCESSOR", filed December 8, 2000, and bearing serial number 60/254,436.
FIELD OF THE INVENTION
The present invention relates generally to data processors for high speed communication systems and networks. More particularly, the present invention relates to 1$ processors for real-time analysis and processing of network data.
BACKGROUND OF THE INVENTION
Network communication devices are, in general, protocol dependent.
Since devices which communicate within computer and storage Networks must strictly adhere to rapidly changing protocols associated with those networks, it has become clear that the use of protocol independent-network processors to analyze, generate and process traffic within these networks is of extreme practical and business importance.
As such, network communication devices typically include specially designed protocol-specific state machines and decoder logic. Protocol-specific hardware offers the advantages of high performance and cost-effectiveness. However, high-speed networking protocol standards are in a state of flux - new protocols are emerging and changing all the time. Since protocol-specific hardware designs are not reusable for different protocols, major redesigning efforts are expended in producing protocol-specific hardware for these emerging protocols. Furthermore, protocol-specific hardware designs cannot be easily updgraded to include new features and functionality. In most cases, modifications to the hardware itself must be made.

SUIVINIARY OF THE INVENTION
An embodiment of the present invention includes a network traffic processor.
The processor itself is protocol independent; it does not have any hardwired logic for recognizing packets, frames, or any other protocol-specific entities. Framing-based tasks are performed inside the processor using user-defined software instructions.
Thus, the same processor may be used to implement network data processing systems for virtually any protocol. Furthermore, new features and functionality can be easily added to the network traffic processor through software upgrades. As a result, the development cost of network data processing systems, as well as the cost of upgrading the system, can also be greatly reduced.
The network traffic processor of the present invention is capable of synchronously processing and generating data for high-speed protocols (serial or otherwise), on a wire-speed, word-by-word basis. Significantly, the processor is capable of operating data directly on its input/output busses without requiring the data to be moved in and out of registers or internal memory units. The low overhead of operating on data directly on its input/output busses, minimizes the total clock cycles required to process and generate each I/O data word. The network processor receives and transmits data on every clock, and executes instructions upon the same clock, eliminating the need for polling or interrupts to determine whether data is ready to be read or written.
According to an embodiment of the present invention, multiple synchronous network traffic processors may be implemented in a system, in a chain mode or otherwise, for providing a multitude of programmable functions. The synchronous network traffic processor may also be integrated with other hardware functions, such as other types of ~5 processors, memory controllers, FIFOs, etc.
The synchronous network traffic processor, in one embodiment, has a low gate count and can be easily implemented using programmable logic (e.g., FPGA). An appropriately programmed synchronous network traffic processor may replace modules traditionally implemented with hard-wired logic or ASIC.

BRTEF DESCRIPTION OF THE DRAWINGS
Additional features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:
Figure 1 is a block diagram illustrating the main functional units of a synchronous network data processor in accordance with an embodiment of the present invention.
Figure ZA is a block diagram illustrating an exemplary implementation of two input pipelines of the input pipeline unit in accordance with one embodiment of the invention.
Figure 2B is a block diagram illustrating an exemplary implementation of two pass-through pipelines of the input pipeline unit in accordance with one embodiment of the invention.
Figure 3A is a block diagram illustrating an exemplary implementation of the data compare unit in accordance with one embodiment of the invention.
Figure 3B is a block diagram illustrating an exemplary implementation of the source select and mask unit of Figure 3A.
Figure 3C is a block diagram illustrating an exemplary implementation of the flag update of Figure 3A.
Figure 4 is a block diagram illustrating an exemplary implementation of the data modify unit in accordance with an embodiment of the present invention.
Figure 5 is a block diagram illustrating an exemplary high-speed data modification ~0 system implemented with synchronous network data processors of the present invention.
Figure 6 is a block diagram illustrating a general network data processing system implemented with synchronous network data processors of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
~5 The present invention provides a processor for synchronously processing and generating data for high speed serial protocols on a word-by-word basis. In contrast to conventional microprocessors, whose main focus is on register and memory operations, an emphasis of the present invention is I/O processing. The processor of the present invention is capable of operating directly on the data streams in its I/O busses without requiring the 30 data to be moved in and out of registers or internal memory. In addition, the processor of the present invention has a wide instruction set. These factors reduce the total clock cycles required to process and optionally modify each I/O data word. Indeed, in one embodiment of the present invention, a data word may be processed and modified in a single instruction clock cycle.

Significantly, the processor of the present invention executes instructions synchronously with a master clock that drives the I/O busses. In one embodiment, the processor interfaces directly to the inbound serial-parallel and outbound parallel-serial converters of the receive and transmit serial interfaces. Words are received and transmitted on every clock cycle, eliminating the need for polling or interrupts to determine whether data is ready to be read or written. The processor does not have any hardwired logic for recognizing packets, frames, or any other asynchronously-arriving protocol-specific entities.
The emphasis is on individual words, which arrive synchronously with instruction execution. Any framing functionality is performed by software. Thus, the processor may be programmed to handle any network protocol.
Figure 1 is a block diagram illustrating the main functional units of a synchronous network data processor 100 in accordance with an embodiment of the present invention. As illustrated, the synchronous network data processor 100 includes a data compare unit 110, a data modify unit 120, an execution control unit 130, a peripheral unit 140, an input pipeline unit 150, an instruction memory 160, and a bank of general-purpose registers 170. The peripheral unit 140 of the illustrated embodiment includes control signal decoders 141, counters 142, control registers 144, an external memory interface 146, and a local interface 148. In the preferred embodiment, instruction memory 160 is a 128-word instruction memory, and register bank 170 includes sixteen banks of 40-bit registers. Data are communicated between the main functional units via 40-bit wide data paths, corresponding to four ten-bit undecoded input characters and four eight-bit decoded characters plus control or status bits. Forty-bit wide data paths illustrated in Figure 1 include:
PTPIPE_A, PTPIPE B, INPIPE_A, INPIPE_B, llVIIVIDATA_l, Il~QMDATA 2, REG-RD DATA1, REG-RD DATA2, PERIPH_WR, DM PERIPH_RD, DC PERIPH RD, and REG_WR DATA. Also illustrated are address busses and control signal paths such as PIPE_CTRL, CTRL REG, DM CTRL, DC_CTRL, INSTRiJCTION, COMPARE FLAGS, PERIPH FLAG, START STOP, IWR-ADDR, IWR DATA, DM PERIPH CTRL, DM_REG_CTRL, DC PERIPH_CTRL, and DC_REG CTRL For simplicity, some addresses busses and control signals are omitted in Figure 1.
The input pipeline unit 150, in the present embodiment, includes four 40-bit wide by 16-stage pipeline registers for the input busses. Two of these pipelines (INPIPE_A, INPIPE B) feed data from input bus INO and IN1 to the data compare unit 110 and data modify unit 120; the other two pipelines (PTPTPE_A, PTPIPE_B) are used for automatic Pass-through of data from the input busses INO and INl to output busses OUTO
and OUTl without program intervention. The input pipeline unit 150 is driven by an externally generated clock signal CLK. Particularly, each pipeline of the input pipeline unit 150 is operable for receiving/outputting one word during one cycle of the clock signal CLK. The pipeline stages from which the outputs are taken are selectable by control signals PIPE CTRL and CTI~L_REG. The signal PIPE CTRL is generated by the execution control unit 130 based on a currently executed instruction. The control signal CTRL_REG
is generated by the control registers 144 based on the values stored therein by the execution control unit 130 in previous execution cycles.
In the present embodiment, the execution control unit 130 executes one instruction at every instruction cycle. Instructions axe fetched and executed from the internal instruction memory 160. Any results the instruction generates may be used in the following instruction. Instruction execution may be interrupted by a trap, which can be generated either internally or from the external interrupt pins. Traps transfer control either to a fixed address or a relative offset from the current program counter (PC); the trap address, absolute/relative mode, and condition are all software-programmable. Every instruction may execute conditionally. Further, every instruction may specify up to two different conditional relative branches, each with its own destination address.
Conditional execution control fields are shared with the control fields for the second branch.
Therefore, if conditional execution is used the second branch must be disabled or use the same condition.
The processor 100 can execute two types of instructions: data compare instructions and data modify instructions. Data compare instructions are for generating control signals that control the data compare unit 110; data modify instructions are for generating control signals that control the data modify unit 120 Significantly, the execution control unit 130 is synchronous with the input pipeline unit 150. That is, both the execution control unit 130 and the input pipeline unit 150 are driven by the same externally generated clock signal CLK. During each cycle of the clock signal CLK, one data word is received by each pipeline of the input pipeline unit 150 and one instruction is executed by the execution control unit 230. This is significantly different from conventional microprocessors where data is required to be moved in and out of registers or internal memory and where the instruction clock is not synchronous with the I/O
clock.

With reference still to Figure 1, the data compare unit 110 is operable for selectively performing mask/match comparisons of two instruction-specified operands during each instruction cycle. In the present embodiment, the instruction-specified operands may come from the input pipeline unit 150 (via INPIPE_A, INP1PE B), the register bank 170 (via REG_RD DATA2), peripheral units 140 (via DM PERIPH_RD), and the execution control unit 130 (via BVllVIDATA_l, IIVIMDATA_2). The mask/match and compare operations performed by the data compare unit 110 are instruction-specified. In particular, the mask/match and compare operations performed are specified by the control signal DC CTRL, which is generated by the execution control unit 130 based on the currently executed instruction. The data compare unit 110 stores the results of the mask/match comparisons to a set of compare flags, which are provided to the execution control unit 130 and peripheral unit 140 (via COMPARE FLAGS). The set of compare flags may be used by the execution control unit 130 and the peripheral unit 140 in the next instruction cycle to conditionally branch, execute, trap, increment a counter, etc. In the present embodiment, there is one compare flag for each 8-bit byte of the 40 bit input word, allowing multiple independent byte comparisons as well as whole 40-bit word comparisons in one instruction.
Also illustrated in Figure 1 are the DC REG_CTRL and the DC PERIPH CTRL signal paths that communicate addresses and commands from the data compare unit 110 to the register bank 170 and the peripheral unit 140, respectively.
The data modify unit 120 of the present embodiment includes arithmetic logic units (ALUs) operable for performing arithmetic and logic operations using instruction-specified operands and operators. In the present embodiment, instruction-specified operands and operators may come from the input pipeline unit 150 (via INPIPE_A, INPIPE_B), the register bank 170 (via REG RD DATA1), peripheral units 140 (DM_PERIPH RD), and the execution control unit 130 (via ~ATA_l, ~ATA_2). Using the instruction-specified operands and operators, the data modify unit 120 generates output data words that are provided to the output busses OUTO and OUT1, the register bank 170 (via REG_WR DATA), and/or the peripheral units 140 (via PERIPH WR). The data modify unit 120 also allows instruction-specified data to pass through unaltered to the output busses O~'0 and OUT1. The modification operations performed by the data modify unit 120 are instruction-specified. In particular, the data modifications performed by the data modify unit 120 are specified by the control signal DM CTRL, which is generated by the execution control unit 130 according to the currently executed instruction. Also illustrated are the DM REG_CTRL and the DM PER1PH CTRL signal paths that communicate addresses and commands from the data modify unit 120 to the register bank 170 and peripheral unit 140, respectively.
With reference still to Figure 1, the peripheral unit 140 includes four 20-bit counters 142, control registers 144, an external memory/peripheral interface 146, and a local interface 148. The local interface 148 allows a host computer to download instructions to the instruction memory 160 via IWR_ADDR and IWR DATA busses, and to control the operations of the processor 100 via START STOP signals and PERIPH FLAGS. In addition, the control register 144 generates the CTRL REG signal for controlling the operations of the pass-through pipes of the input pipeline unit 150. The local interface 148 also allows the host computer to communicate with the processor 100 via shared mailbox registers (not shown). Counters 142 that maybe cascaded to give two 40-bit counters or one 40-bit and two 20-bit counters. Each counter 142 has an independently programmable increment enable, allowing it to increment in different modes: synchronously at every clock cycle, selectively when a register is written, or based on a mask/match of the compare flags generated by the data compare unit 110. Additionally, one or two counters 142 may be used as an address generator for the external memory/peripheral interface 146. The data modify unit 120 may configure the counters 142 and the control registers 144 by communicating appropriate data via the PERIPH WR bus.
An Exemplary Implementation of the Input Pipeline Unit An exemplary implementation of the input pipeline unit 150 according to one embodiment of invention is illustrated in Figures 2A and 2B. Figure 2A
illustrates two input pipelines 210 and 220, and Figure 2B illustrates two pass-through pipelines 230 and 240. Pipelines 210, 220, 230 and 240 each includes sixteen 40-bit wide registers 214 (herein called 16-stage pipeline registers) that are driven by the clock signal CLK.
As illustrated in Figure 2A, input pipeline 210 includes a multiplexes 212 that selectively provides data from either one of the input busses INO and IlV1 to the 40-bit wide byl6-stage pipeline registers 214 according to a control signal PA_SRC
provided by the control registers 144 of the peripheral unit 140. Likewise, input pipeline 220 includes a multiplexes 212 that selectively provides data from either one of the input busses INO and INl to the pipeline registers 214 according to a control signal PB SRC, which is also provided by the control registers 144.
_7_ In the illustrated embodiment, each stage of the pipeline registers 214 includes an output for outputting one of the input data words after a delay of a number of clock cycles corresponding to a position of the respective stage in the pipeline. The outputs of the pipelines 210 and 220 are determined by the pipeline stage select multiplexers 216, which select the stages from which the outputs are taken. The particular stages of the pipelines 210 and 220 from which the outputs are selected are controlled by control signals PA WORD_SEL and PB_WO1~D_SEL, which are generated by the execution control unit 130 in accordance with the currently executed instruction.
Pass-through pipelines 230 and 240 of Figure 2B are used for automatic pass-through of unmodified data from the input busses INO and IN1 to the output busses OUTO and OUT1 without program intervention. Similar to pipelines 210 and 220, each stage of the pipeline registers 214 includes an output for outputting one of the input data words after a delay of a number of instructions cycles corresponding to a position of the respective stage in the pipeline. The outputs of the pipelines 230 and 240 are determined by the pipeline stage select multiplexers 226, which select the stages from which the outputs are taken. The particular stages of the pipelines 230 and 240 from which the outputs are selected are controlled by control signals PO WORD SEL and P1 WOI~D_SEL, which are provided by the control registers 144 of the peripheral unit 140.
An Exemplar'r Implementation of the Data Compare Unit An exemplary implementation of the data compare unit 110 is illustrated in Figures 3A-3C. As shown in Figure 3A, the data compare unit 110 includes source select and mask units 310, comparators 320 and flag update units 330. Each source select and mask unit 310 is configured for receiving data from the input pipeline unit 150 (via INPIPE_A, ~'n'E B)~ the register bank 170 (via REG RD DATA2), the peripheral unit 140 (via DC PERIPH_RD) and the execution control unit 130 (via IniIMDATA_l, BATA 2).
The source select and mask units 310 perform instruction-specified masking operations on the data to generate masked data and comparands to be provided to the comparators 320.
The comparators 320 perform comparisons or "matching" operations between the masked data and the comparands to generate match outputs, which are provided to the flag update units 330. The flag update units 330 in turn generate a set of compare flags DCO, DC1, DC2, DC3 and DC4 based on instruction-specified flag update modes.
In the present embodiment, there is one compare flag for each ~-bit byte of the 40 bit input word, allowing multiple independent byte comparisons as well as whole 40-bit word _g_ comparisons in one instruction. It should be appreciated that the data to be masked and the comparands to be generated by the source select and mask units 310 are instruction-specified. Specifically, each of the select and mask units 310 receives the control signal DC_CTRL, which is generated by the execution control unit 130 according to a currently executed instruction.
Figure 3B illustrates an exemplary implementation of a source select and mask unit 310 in accordance with an embodiment of the present invention. As illustrated, the source select and mask unit 310 includes 8-bit multiplexers 342a-342f. Although it is not illustrated in Figure 3B, it is appreciated that the multiplexers 342a-342f are controlled by the signal DC_CTRL. Thus, the sources of the data, the mask and the comparand are specified by the currently executed instruction.
It should also be noted that the data paths within the illustrated source select and mask unit 310 are only eight bits wide. For example, the source select and mask unit 310 processes bit-0 to bit-7 of the 40-bit wide data. The remaining bits of the 40-bit data words are handled by the other source select and mask units 310 of the data modify unit 120.
As illustrated, multiplexes 342a-342c each includes inputs for receiving data from the input pipeline unit 150 (via INPIPE_A and INhIPE B). The output of the multiplexes 342a is coupled to one of the inputs of multiplexes 342d, which also receives data from the register bank 170 (via REG DATA2) and from the peripheral unit (via DC PERIPH
RD).
Thus, by applying the appropriate control signals, the output of the multiplexes 342d, which is the data to be masked, can be chosen from any one of these sources.
Similarly, because multiplexes 342e is coupled to receive data from input pipeline unit 150 (via multiplexes 342b), the register bank 170, or the execution control unit 130 (via ~ATA_1), the output of the multiplexes 342a, which is the mask data, may be chosen from any one of these data sources. The outputs of multiplexes 342e-342f are coupled to an AND-gate 344, which performs a masking operation on the data. In the present embodiment, the comparand may be selected from data within the input pipeline unit 150, the register bank 170, the peripheral unit 140 or the execution control unit 130 (via BATA 2) when appropriate control signals are applied to multiplexers 342c and 342f.
Figure 3C is a block diagram illustrating an exemplary flag update unit 330 in accordance with an embodiment of the present invention. The flag update unit 330 provides additional programmability and flexibility to the processor 100 by allowing the instruction to specify how the compare flags are updated. Particularly, as illustrated in Figure 3C, the flag update unit 330 includes an AND-gate 332, an OR-gate 334, and XOR-gate 336, each having an input for receiving a comparison result from a comparator 320. The outputs of the logic gates are coupled to inputs of multiplexes 338. Responsive to a flag update mode control signal generated by the execution control unit 130, the multiplexes 338 selects one of the outputs of AND-date 332, OR-gate 334, XOR-gate 336, or the comparison results from the comparator 320, to be provided to a memory element 342 (e.g., a D-flip-flop). The output of the memory element 342 is fed back to the inputs of the logic gates 332, 334 and 336 to form feed-back loops. In this way, the flag update unit 330 updates the compare flags according to the instruction and according to the state of the compare flags in a previous instruction cycle. It should be noted that the memory element 342 is synchronous with the clock signal CLK that drives the input pipeline unit 150 and the execution control unit 130. Thus, the updated compare flags are provided to the execution control unit 130 for use in the next clock cycle.
An Exemplar~plementation of the Data Modif, Figure 4 is a block diagram illustrating an exemplary implementation of the data modify unit 120 in accordance with an embodiment of the present invention.
According to the present invention, the data modify unit 120 may access any instruction-specified data stored within the input pipeline unit 150, and modify the instruction specified data using an instruction-specified operator during one instruction cycle. The data modify unit 120 may also allow data to pass-through without any modification.
Particularly, as illustrated in Figure 4, the data modify unit 120 includes two multiplexers 410a-410b, which are operable to receive data from input pipeline unit 150 - - - -(via INPIPE_A, INPIPE_B), the register bank 170 (via REG RD DATA1), or the peripheral unit 140 (via DM PERIPH RD). The outputs of the multiplexers 410a-410b are coupled to ALUs 420a-420b, which also receive data from the execution control unit 130 as operands (via ~ATA_l, BATA 2). The outputs of the ALUs 420a-420b are provided as inputs to another ALU 420c. The outputs of the ALUs 420a-420c are also provided to multiplexers 430a-430b. The multiplexers 430a-430b are also coupled to receive data directly from the pass-through pipelines PTPIPE_A and PTPIPE_B of the input pipeline unit 150. The control signals out0 src and outl src, received from the control registers, are for selecting the inputs to the output multiplexers 430a and 430b, respectively.
The output of the multiplexers 430a-430b are coupled to output registers 440a-440b, which provide data to the output busses OUTO and OUT1 of the processor 100.

According the present embodiment, the sources of the data to be modified, as well as the operators, are instruction-specified. Particularly, the data modify unit 120 receives the control signals SRC1 SEL, SRC2_SEL, opl, opt, op3 (via control signal bus DM_CTRL), which are generated by the execution control unit 130 according to the current instruction.
The control signals SRCl SEL and SRC2_SEL are for selecting the inputs of multiplexers 410a-410b. The control signals "opl", "opt", and "op3" are for controlling the logic operations of ALUs 420a-420c. Thus, by using appropriate instructions, the data modify unit 120 may be configured for performing a variety of instruction-specified data modification operations during each clock cycle to generate the desired data for output.
Exemplar,~pplications of the Processor of the Present Invention Figure 5 is a block diagram illustrating a high-speed data modification system coupled between network devices 510 and 512. As illustrated, network devices 510 and 512 communicate with one another via high speed communication paths 514 and 516.
Inserted into the high speed communication paths 514 and 516, the data modification system 520 enables real-time system-level testing of the devices 510 and 512 by injecting errors into the communication paths 514 and 516, and monitoring the responses of the devices 510 and 512.
As illustrated, data modification system 520 includes two trace memories 522 for capturing the data that are communicated between the devices 510 and 512 for output to an analyzer. Additionally, data modification system 520 includes a trigger subsystem 526 and two data jammers 524. The trigger subsystem 526 monitors the data paths 514 and 516, waiting for a datum in the streams to match a predefined pattern. When the trigger subsystem 526 detects an input datum matching the predefined pattern, the trigger subsystem 526 generates a trigger signal to the data jammers 524. The data jammers 524 respond to the trigger signal by "jamming" - altering selected portions of the input datum in a predefined manner in real time.
The trigger subsystem 526 and the data jammers 524 may be implemented with the high-speed synchronous network data processor of the present invention.
Particularly, one synchronous network data processor 100 may be used to implement the trigger subsystem 526 by loading appropriate data compare instructions and data modify instructions into the processor. Each of the data jammers 524 may also be implemented with a synchronous network data processor 100 by loading appropriate instructions therein. A
significant advantage of using the synchronous network data processor of the present invention in the data modification system 520 is that the system may be re-programmed for different types of protocols as well as to perform different tasks.
Application of synchronous network data processor of the present invention is not limited to data modification systems. Figure 6 is a block diagram illustrating a general network data processing system 600 implemented with synchronous network data processors of the present invention. As shown, the general network data processing system 600 includes four synchronous network data processor 100 interconnected by an interconnect fabric 670. Also interconnected by the interconnect fabric 670 are a FIFO
module 610, a RAM module 620, a CAM module 630, I/O modules 640, a RX data path 650, and a TX data path 660. According to the present invention, the RX data path 650 is a inbound serial-to-parallel interface, and the TX data path module 660 is an outbound parallel-to-serial interface. The I/O modules 640 are for coupling the network data processing system 600 to data analyzers and other network data processing systems.
Branch Control and Conditional Execution of Instructions by the Processor According to the present invention, the processor 100 may execute every instruction conditionally. Further, every instruction may specify up to two different conditional relative branches, each with its own destination address. In the present embodiment, conditional execution control fields are shared with the control files for the second branch. If conditional execution is used, the second branch is disabled or use the same condition.
The bits that are examined when determining whether to conditionally branch, execute, or trap are referred to as the "flags," and are held in the flags register of the execution control unit 130. There are six flags in total, which include the five flags generated by data compare instructions (DC4-DCO) and one programmable "P" flag generated by the peripheral unit 140. The "P" flag is selectable from one of several sources including counter wrap flags, the external memory interface ready signal, and the carry output of the data modify unit 120. The format of the flags register is shown below in Table 1.
Table 1 Bit 39-6 5 4 3 2 1 0 Name Reserved P DC4 DC3 DC2 DC1 DCO

A branch or execute condition is specified by three fields: Mask, Match, and TruelFalse. Mask and Match are the same width as the flags register (40-bit), and True/False is a single bit. The execution control unit 130 evaluates the condition by logically ANDing the flags with Mask, and then comparing this result to Match. If the comparison result (True if equal, False if not equal) is the same as the True/False bit, the condition is considered satisfied and the branch or conditional execution takes place.
The branch conditions and the execution conditions of an instruction are defined by its common control fields. The syntax and operations of the common control fields are described below in Table 2.

Table 2 Common Control Field Function Conditional branch control. The two conditions are evaluated as described above. If condition 1 is satisfied, a branch is taken to addrl.
Otherwise, if condition 2 is satisfied, a branch is taken to addr2.

Otherwise, control transfers to the following instruction. Legal values are any 6-bit constant for the mask and match fields, T or F
for the tf field, and a 12-bit constant or a label (string) for addrl and addr2.

The second branch condition and address may be omitted if not used. If no branch control field is given at all, control falls through to the next instruction.

The second branch condition is shared with the br(maskl, matchl, execute condition; therefore if both tfl, conditional addrl,mask2, match2, execution and the second branch are tf2, used, their addr2) conditions must be the same.

When the second branch is not specified, the assembler encodes either an always-satisfied condition or the execute condition specified by the exec on() field. In each case, the second branch target is the next instruction. When neither branch is specified, the assembler encodes always-satisfied conditions for both branches, and the next instruction for both branch targets.

Address OxF80 has a special function when used as the branch 2 address. It causes a branch to the program counter (PC) saved by a previous subroutine call and is used to return from the subroutine. The branch 2 mask/match/tf controls still function ~5 normally, allowin conditional returns.

Conditional execution control. The condition is evaluated as described above. If it is satisfied, the instruction executes; otherwise it does not execute (is treated as a no-op). All common control fields with the exception of bg_run are active regardless of exec on(mask, match, whether the instruction executes or tf) not.

The execute condition is shared with the second branch condition (see above).

If no conditional execution control field is specified, the instruction executes.

Save the current program counter (PC).
Used to implement subroutine calls. The ctrl field defines how the PC is saved:

0: don't save PC

save 1: store current address + 1 to saved pc(ctrl) PC

_ (subroutine returns to next instruction)

2: store branch address 2 to saved_PC

(subroutine returns to branch address 2. Branch 2 still behaves normally).

Others: reserved When present, causes the instruction to run in the background (i.e., execute continuously until interrupted by the execution of another instruction of the same type). If not present, the instruction executes for the present instruction cycle only. Once an instruction is running in the background, it is no longer subject to any execution condition it may have been issued with.

bg_run An interruption of a background-running instruction occurs only if the interrupting instruction actually executes; i.e., its execution condition is satisfied.

While background run mode is only supported for data compare instructions in one preferred embodiment, in an alternate embodiment background run mode is supported for both data compare and data modify instructions..

Some pseudo-control operations that can be implemented using the execution control fields are shown below in Table 3. Appropriate macros for these can be defined in a standard header file. Software written using the pseudo-contxol codes may be translated into the processor-specific common control fields using a pre-processor.
Table 3 Pseudo-controlO eration Im lementation jmp Jump to address 0, T, addr) br(0 (unconditionally) , jsr Jump to subroutine 0, T, subr) save pc(1) br(0 (unconditionally) _ , Jump to subroutine;br(0, 0, T, subr, 0, 0, T, retaddr) jsrr return to specified pc(2) save address (unconditionally)_ ret Return from subroutine0, 0, T
OxF80) br(0 F

(unconditionally) , , , , , Branch if carry bcs set br(Ox20, 0x20, T, addr) (P = DM c fla ) bcc Branch if carry br(Ox20 clear F, addr) 0x20 (P = DM carry fla , ) , loop Jump if still in br(Ox20, 0x20, F, addr) loop (P = counter wra fla ) exec loopendExecute on end of exec loop on(Ox20, 0x20, T) ( P = counter wra _ fla ) br br(Ox0l, 0x01, T/F, addr) c~t/f _ br(Ox03, 0x03, TlF, addr) br c 16t/f _ Branch on 1-5 byte br(Ox07, 0x07, T/F, addr) br c24t/f _ comparison true/falsebr(OxOf, OxOf, T/F, addr) br c32t/f _ br(Oxlf, Oxlf, T/F, addr) br c40t/f Data Compare Instructions Executable by the Processor Data compare instructions perform a three operand (data, mask, and match) comparison operation of up to 40 bits at a time. The sources of the data to be compared can be the input pipeline unit 150, the register bank 170, the peripheral unit 140, and/or the execution control unit 130. According to the present embodiment, the input pipelines are fed from the processor's input busses INO and IN1, and the pipeline stage read by the comp~.e instruction can be selected on the fly by the currently executed instruction.
Data compare instructions are carried out by the data compare unit 110 which includes five independent 8-bit comparators 330, each of which has selectable inputs for its data, mask, and match values. Each comparator 330 updates its own comparison result flag, which can be used as part of a conditional branch or execution condition. This flag can either be set to the comparison result, or to the logical AND, OR, or XOR of the comparison result and current flag value.
The syntax of a data compare instruction executable by the processor 100 is:
compare data, mask, match [data compare specific control fields]
[Common control fields];
The C-equivalent logical operation performed by a data compare instruction is described below in Table 4.
Table 4 for (comp = 0; comp < 5; comp++) // do all 5 comparators // perform ~-bit mask/match comparison if ( (data[comp] & mask[comp]) _= match[comp] ) result[comp] = 1;
else result[comp] = 0;
// update comparison result flag (SET, AND, OR, or XOR) switch(update_mode) case SET: flag[comp] = result[comp]; break;
case AND: flag[comp] &= result[comp]; break;
case OR : flag[comp] ~= result[comp]; break;
case XOR: flag[comp] ~= result[comp]; break;
The compare flags are updated one clock after the instruction executes, and therefore may be used in the following instruction. Note that if a branch or execute condition is used in the same instruction as the compare, the flag values are those that existed BEFORE the compare instruction executes.
Although data for the data compare instructions may come from numerous sources 0 and may be specified on the fly by the currently executed instruction, there are a few limitations. Table 5 below shows the legal values for the three comparator source fields.
Table 5 Input Input Register PeripheralImmediate Source 5 Pi eline Pi eline Bank Data data A B

Mnemonic ina[n] inb[n] r[n] periph[n] [value]

data YES YES YES YES NO

mask YES YES YES YES YES

match YES YES YES YES YES

The comparator source fields are also subject to the following restrictions:

(A) If an input pipe is used for the mask source, it may not be the same as that used for the data.
(B) If the same input pipe is used in more than one source, the pipe word number (n) (i.e., the point at which the input pipe is tapped) must be the same in both uses.
(C) If a register or peripheral is used in more than one source, the number (n) must be the same in both uses. The parameters of r and periph are the register or internal peripheral number. Legal values for these parameters are 0-15.
The immediate data value is a 40-bit constant specified in the instruction.
Two different values may be specified for the mask and match fields.
The parameters of the input pipelines specify the stage in the input pipelines from which data are accessed. For example, an instruction including the field "ina[4]" indicates using the word in the fourth stage of input pipeline INPIPE_A. Legal values for these P~'~eters are 0-15. The input bus feeding each pipeline and the pipeline enables are set by fields in the control registers 144. .
Table 6 shows the type-specific control fields that are supported by data compare instructions.
Table 6 Control Field Function byte sel(c4, c3, c2, Selects the byte number of the 40-bit c1, c0) source word to apply to each comparator's data input.
This field is only valid when using an input pipe as the data source, and has no effect otherwise. Legal values for c4-c0 are 4-0 (byte 4 is the msb of the 40 bit input word, and byte 0 is the lsb). For the mask and match fields, or for non input pipe data sources, the byte number of the input word is the same as the comparator number; e.g., the third comparator uses byte 3 of the mask word.

If this field is not given, the byte selects default to the previous values given, or 4,3,2,1,0 if no previous values were iven.

update mode() I Used in conjunction with the FLAG UPD_CFG field of the control registers to set the flag update mode for all comparators. The truth table for FLAG_UPD CFG can be found in Appendix-A. Legal values for mode are 0 and 1. If this field is not given, the mode defaults to the previous value given, or "0"if no previous value was Data compare instructions may be run in background mode by applying the bg_run common control field to the instruction. In background run mode, a data compare instruction runs continuously, updating the compare flags, until the next compare instruction executes. Normal conditional branching and execution may be performed based on the flags generated by the background-running instruction.
Instruction examples illustrating both legal and illegal uses of the data compare instructions are illustrated below in Table 7.
Table 7 Code Examples Description compare ina[0], Oxffffffffff, 40-bit straight comparison of the word in Ox123456789a byte sel(4, 3, the first stage of input pipe 2, l, 0) A to a update mode(SET); constant. The word was equal to Ox123456789a if all five comparator flags are true after the instruction executes.

compare ina[0], Oxfffffffff0, Same as above but with the lower 4 bits 0x1234567890; masked off (ignored in the comparison).

The control fields default to the previous values used if not specified.

compare ina[0], r[2], inb[8]; Compare the first stage of input pipe A

with the ninth stage of input pipe B, after masking the data in pipe B
with data in r[2].

compare inb[12], r[8], periph[4];Compare Pipe B stage 12 with peripheral 4, using mask in r[8].

compare ina[1], r[2], inb[0]; Compare a word in the input pipeline to the word received one clock ago.

Assumes Pipes A and B both have the same source bus (in0 or inl).
(The pipe source busses are set by bits in CTRL REG).

compare inb[4], ina[0], ina[0];See if all the bits set in the first stage of input pipe A are also set in the fifth stage of input pipe B.

compare inb[4], r[13], r[13]; Same as above, but using registers.

compare ina[0], OxOfffffffff, Bacleground run example: start SOFi3 up the bg_run; compare unit loolung for SOFi3 in the input data stream, and then let other instructions execute. "SOFi3"
is a C-style definition of the numeric value of a "start of frame" ordered set.

compare ina[3], Oxffffffffff, Byte sel example: Compare input pipe A

Ox123456789a byte sel(2, 2, stage 3 byte 2 with five different 2, 2, 2); values (0x12, 0x34, 0x56, 0x78, and Ox9a). The five flags hold the results of the five comparisons.

compare ina[3], Ox73ff3f7ff8, Same as above, but with five different Ox123456789a, byte sel(2, 2, 8-bit masks for the comparisons.
2, 2, 2);

compare ina[3], Oxffffffffff, Compare the 16-bit word in Pipe A stage Oxaa12345678 byte sel(4, 1, 3 bytes 1-0 to two different 0, 1, 0); values (Ox 1234 and 0x5678), and byte 4 to Oxaa.

compare ina[7], Oxffffffffff, Update mode example: if WORD
WORD A A, update mode(SET); WORD B, and WORD C are received in compare ina[7], Oxffffffffff, succession. The comparison WORD B flags are set update mode(AND); on the first comparison, then ANDed compare ina[7], Oxffffffffff, with the current flags. The WORD_C pipes advance update mode(AND); 1 stage per instruction, so reading the same pipe word on successive instructions has the effect of reading successive input words. This could alternatively be done with conditional branching. If the five flags are true after execution of the third compare instruction, the three specified words have been received in succession.

compare ina[1], Oxff, ina[2]; Examples of illegal usages.

compare r[2], Oxff, r[4];

compare ina[3], periph[2], periph[3];

compare inb[0], inb[0], Oxff;

compare Oxff, ina[1], r[2];

Data Modif,~! Instructions Executable by the Processor A description of the data modify instructions executable by the processor 100 of the preferred embodiment follows. Data modify instructions perform arithmetic and logic operations using up to four operands and three operation codes (opcodes), and store the results to one or more write destinations. The instructions use the same sources as data compare instructions: the input pipeline unit 150, the register bank 170, the peripheral unit 140, or immediate data from the execution control unit 130 as defined in the currently executed instruction.
Data modify instructions are performed by the data modify unit 120, which includes t~'ee two-operand arithmetic logic units ALU1-ALU3. ALUl and ALU2 have their first operand (X) selectable from among the input pipeline unit 150, the register bank 170, or the peripheral unit 140. Their second operand (Y) is an immediate data value provided by the execution control unit 130 and specified in the currently executed instruction. The operands of ALU3 are the outputs of ALU1 and ALU2. ALU3 also generates a carry flag, which can be selected as a source flag for conditional branching or execution.
An optional ALU-bypass mode is available to the instructions. In the ALU-bypass mode, the results from ALUl and ALU2 are provided to the output busses (OUTO
and OUT1), bypassing the ALU3. This mode allows both busses to be updated with one 0 instruction.
The data modify unit 120 also supports an internal pass-through mode where data from the input pipeline unit 150 are provided directly to the output busses OUTO and OUTl. In this pass-through mode, "default" data can be supplied to the output busses ~5 whenever data modify instructions are not executing. The pass-through operation is configured by fields in the control registers 144 of the peripheral unit 140.
The opcodes supported by data modify instructions are shown below in Table 8. Operations are shown as C equivalents.
30 Table 8 Supported by Opcode Operation Description ALU's and X ~Z Y Bitwise to ical AND of 1, 2, 3 X and Y

or X Y Bitwise logical OR of l, 2, 3 X and Y

xor X ~ Y Bitwise to ical XOR of 1, 2, 3 X and Y

35 nor ~(X ~ Y) Bitwise logical NOR of 1, 2 ~ X and Y

ror8a ror(X, 8) Rotate X ri ht 8 bits, 1 & Y AND with Y

rorla ror(X, 1) Rotate X right 1 bit, 1 & Y AND with Y

rol8a rol(X, 8) Rotate X left 8 bits, 2 & Y AND with Y

rol2a rol(X, 2) Rotate X left 2 bits, 2 & Y AND with Y

add X + Y Sum of X and Y 3 add 1 X + Y + Sum of X and Y, lus 1 3 ass_imrn Y Pass Y (immediate data) 1, 2 to result tbdl2 tbd tbd 1, 2 tbd3_a tbd tbd 3 tbd3_b tbd tbd 3 tbd3 c tbd tbd 3 Table 9 below shows pseudo-opcodes that may be implemented using the native opcodes. Appropriate macros for these can be defined in a standard header file.
Table 9 Pseudo- pperation Description Implementation Note no (none) No o eration null = or(0, 0) not ~A Bitwise inversexor(A, Oxffffffffff) of inc A + 1 Increment A add(A, 1) or add 1(A, 0) dec A -1 Decrement A add(A, Oxffffffffff) sub A _ B Difference addpl(A, not(B)) of A

and B

Difference subi A - B of A addpl (A, ~B) ~d B, B constant ne -A Ne ate A add 1 (0, not(A)) adc A + C Sum of A and add(A, 1) 1 carry exec on(Ox20,Ox20,T) sec C = 1 Carry = 1 add(1, Oxffffffffff) clc C = 0 Carry = 0 add(0, 0) testge A >= B B null = sub(A, B) ~ A ~ B >-~

testnz A != 0 C~'y = 1 if null = add(A, Oxffffffffff) A !=

0, OifA==0 testneg A < 0 Cue' =1 if null = add(A, A <

0, 0 if A >= 0x8000000000) ror8 ror(A Rotate A rightror8a(A, Oxffffffffff) 8) 8 , bits rol8 rol(A Rotate A left rol8a(A, Oxffffffffff) 8) 8 , bits shr A 1 Shift A ri rorla(A, Oxefffffffff) ht 1 bit shl A 1 Shift A left add(A, A) 1 bit Shift A right shr8 A 8 8 Ox00ffffffff) ror8a(A

bits , shl8 A 8 Shift A left rol8a(A, Oxffffffff00) 8 bits shrn A N Shift A right(V~ous) 2 N

bits (N =
1..39) shln A N Shift A left (V~ous) 2 N bits (N = 1..39) bset bset(A, N) Set bit N or(A, 1 N) in A

bclr bclr(A, N) Clear bit and(A, ~(1 N)) N in A

Swap bytes or(ror8a(A, 0 and bswap0l bswap(0,1) 1 in A, Ox00000000ff), zero others rol8a(A, Ox000000ff00)) Swap bytes or(ror8a(A, 1 and bswapl2 bswap(1,2) 2 in A, Ox000000ff00), zero others rol8a(A, Ox0000ff0000)) Swap bytes or(ror8a(A, 2 and bswap23 bswap(2,3) 3 in A, Ox0000ff0000), zero others rol8a(A, Ox00ff000000)) Swap bytes or(ror8a(A,

3 and bswap34 bswap(3,4) 4 in A, Ox00ff000000), zero others rol8a(A, Oxff00000000)) Notes:
(1) Assumes P flag is programmed to be the ALU3 carry flag. See the PERIPH
CTRL
register.
(2) Can be implemented with mufti-instruction macros using rorla, ror8a, rol2a, and rol8a opcodes. Worst case N requires 5 instructions.
Data modify instructions write their results to one or more of the following write destinations: either of the two output busses OUTO and OUTl, the register bank 170, or the peripheral unit 140.
The syntax of the data modify instructions in normal mode is:
destl [,dest2...] = op3(opl(srcl, imml), op2(src2, imm2)) [Common control fields];
ALU3 bypass mode is specified by assigning one or more of the output busses to the ~,Ul or ALU2 results, using the following syntax.
destl [,dst2...] = op3(out0 = opl(srcl, imml), op2(src2, imm2)) [Common control fields];
destl [,dest2...] = op3(opl(srcl, imml), outl = op2(src2, imm2)) [Common control fields];

destl [,dest2...] = op3(out0 = opl(srcl, imml), outl = op2(src2, imm2)) [Common control fields];
The first syntax places out0 in bypass mode. The second syntax places outl in bypass mode, and the third places both outputs in bypass mode. When an output is in bypass mode, it is illegal to also use it as an ALU3 destination.
The operation codes opl-op3 are for ALUs 420a-420c, respectively; srcl and src2 are the selectable source fields for ALU 420a and ALU 420b, and imml and imm2 are the two 40-bit immediate data values. The C-equivalent logic operation performed by a data modify instruction is illustrated below in Table 10.
Table 10 resultl = a1u12 operation(opl, srcl, imml);
result2 = a1u12_operation(op2, src2, imm2);
if (out0 bypass) out0 = resultl;
if (outl bypass) outl = result2;
dest(s) = alu3_operation(op3, resultl, result2);
Additionally, the ALU3 carry flag is updated if the ALU3 opcode is "add" or "addpl" (other opcodes and DC instructions do not change the carry flag value). The carry is set if the addition overflowed, and cleared otherwise. In addition to arithmetic operations, the carry flag (not shown) can be used as a general-purpose branch and execute control flag.
Table 11 below shows the legal sources for the source (src 1 and src2) and destination (dest) fields of a data modify instruction. Note that null can be specified for dest, in which case the ALU3 result is ignored. The immediate data operands (imml and imm2) are 40-bit constants specified in the instruction.
Table 11 Sourcel Input Input RegisterPeripheralOutput OutputNone Dest 0 1 Bank Data Bus Bus Pi elinePi eline Mnemonic in0[n] inl[n] r[n] eri h[n] out0 outl null src 1 YES YES YES YES NO NO NO

src2 NO YES YES NO NO NO NO

Best NO NO YES YES ~ YES YES YES
The parameters of r and periph are the register or internal peripheral number.
Legal values for these parameters are 0-15.
The parameters of in0 and inl are the word in the input pipeline register to operate on. For example, in0[4] means use the word in stage 4 of the input 0 pipeline.
Legal values for these parameters are 0-15.
In the present embodiment, the source and destination fields are subject to the following additional restrictions:
(A) ~ the same input pipe is used in more than one source, the pipe word number (n) must be the same in both uses.
(B) If two registers are used as sources and a register is also used as a destination, the register number (n) of one of the source registers must be the same as that of the destination register.
(C) ~ a peripheral is used in more than one source, the number (n) must be the same in both uses.
(D) If both a register and peripheral are used as destinations, the number (n) must be the same in both uses.
(E) No more than one register may be used as a destination.
(F) No more than one peripheral may be used as a destination.
Table 12 below illustrates some exemplary usages of the data modify instructions.
Table 12 Code Examples Description out0 = in0[0]; Pass-through data.

outl = r[4]; Output data from register.

out0 = Ox08BCB51717; Send an SOF (Start of Frame).

r[0] = 0x12345678; Initialize register to constant.

r[1] = r[0]; Move register to register.

r[2] = periph[3]; Move peripheral value to register (save DC flags).

periph[3] = r[2]; Move register to peripheral.

r[3] = in0[1]; Move input value to register.

periph[11] = Oxaa; Store constant to peripheral.

r[0] = r[0]; No operation.

r[0] = add(r[0], r[1]); Add register to register.

outl, r[6] = 0x0123456789; set output and register to 40 bit constant out0, outl, r[12] = periph[3]; set both outputs and register to peripheral value out0, outl, r[5], periph[5] Multiple destinations.
= in1 [3];

r[0] = or(out0 = l, outl = 2) ALU-3 bypass mode.

null = or(out0 = 1, outl = 2) ALU-3 results ignored.

out0 = or(r[2], periph[3]); Logical OR of register and peripheral value out0 = xor(in0[0], 1); Toggle bit 0 of input, send to output bus 0 r[3] = and(inl[6], Oxffff); Store lower 16 bits of input to r[3]

r[7] = add(r[7], 1); increment r[7]

out0 = or(and(inl[4], Oxffffff00),output = input with byte 0 OxBb); changed to OxBb out0, outl, r[3], periph[3] Example of complex data modify =

addpl(xor(in0[8], Ox123456789a),instruction.

or(periph[2], Oxfedcba9876));

r[3], periph[3] = addpl(out0 With ALU3 bypass mode on both = xor(in0[8], outputs Ox123456789a), outl = or(periph[2], pxfedcba9876));

r[3], periph[3], outl = addpl(out0With ALU3 bypass mode on OUTO
= only xor(in0[8], Ox123456789a), or(periph[2], Oxfedcba9876));

r[3], periph[3], out0 = addpl(xor(in0[8],With ALU3 bypass mode on OUT1 only Ox123456789a), outl = or(periph[2], Oxfedcba9876));

out0 = or(in0[1], in0[2]); Examples of illegal usage r[0] = and(r[1], r[2]);

r[0] = add(periph[0], periph[1]);

r[0], periph[1] = 2;

r[0],r[1] = 0;

periph[0], periph[1] = r[6];

Peripheral Unit and Control Re"isg tens The peripheral unit 140 is accessed via a set of registers referenced by the instructions as periph[n]. The peripheral unit 140 is divided into a number of subunits, which are described in more detail below. Table 13 below shows the address map of the subunits and registers in the peripheral unit.
Table 13 Register Name Address Description Subunit Read/

Write External Memory External EXT periph[0] Interface writeMemory W
WR DATA data _ kith normal Interface Unit addressin External MemoryExternal EXT periph[0] Interface read Memory R
RD DATA data _ w ith normal ~terface Unit addressin MAILBOX periph[1] M~lbox RegisterLocal InterfaceW
W to _ host Unit MAILBOX R periph[1] M~lbox RegisterLocal InterfaceR

f rom host Unit Counter 3 (upperCounter Unit CTR 32 periph[3] 20) and Counter R

2 5 lower 20 bits CTR_INC periph[3] Counter IncrementCounter Unit W

re ister ENG CTRL eri h 4] Control Re ister[Global] W

TRAP CTRL periph[5] Trap Control Trap Unit W

R e ister DATA periph[6] Counter Data Counter Unit W
CTR

_ re ister PERIPH_CTRL periph[7] Peripheral Control[Global] W

re ister External MemoryExternal WR DATA I periph[~] ~te~ace write Memory W
EXT data _ w ith ALU2 indexed~terface Unit addressin External MemoryExternal EXT periph[8] Interface read Memory R
RD DATA I data _ w ith ALU2 indexed~terface Unit addressin RESERVED others ~ Reserved The format of the peripheral subunits are described in Appendix-A.
Alternate Embodiments While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the claims below.

APPENDIX A
Peripheral Register Formats EXT_WR DATA - External Memory Interface Write Data - Write Only Field NameBits Function This value is written to the external memory interface write data bus. Writing this value also causes the interface chip select and write strobe to be asserted. The address presented to the external memory interface during the write is the concatenated value of Counter 3 (upper 20 bits) and Counter2 (lower 20 bits)).

data 39-0 The instruction writing the memory interface does not stall due to a deasserted interface RDY signal; instead, this signal can be used as part of a 1$ branch/execute/trap condition to provide software-based wait states (during which other useful instructions may execute). The write value has not necessarily been accepted by the external memory until it asserts RDY.

EXT_WR DATA I - External Memory Interface Write Data with ALU2 Indexed Addressing- Write Only Field NameBits Function This register functions equivalently to the 2$ EXT WR DATA register, except that the data 39 0 address presented to the external memory interface is Counter32 + the ALU2 result.

EXT_RD DATA - External Memory Interface Read Data - Read Only Field NameBits Function This value is read from the external memory interface read data bus. Reading this value also causes the interface chip select and read strobe to be asserted. The address presented to the external memory interface during the read is the concatenated value of Counter 3 (upper 20 bits) and Counter 2 (lower 20 bits).

data 39-0 The instruction reading the memory interface does not stall due to a deasserted interface RDY signal; instead, this signal can be used as part of a branch/execute/trap condition to provide software-based wait states (during which other useful instructions may execute). The read value is not necessarily valid until the external memor asserts RDY.

EXT_RD DATA I - External Memory Interface Read Data with ALU2 Indexed Addressing- Read Only Field NameBits Function This register functions equivalently to the EXT RD DATA register, except that the ' - -data 39-0 address presented to the external memory interface is Counter32 + the ALU2 result.

MAILBOX W - Mailbox Register to Host - Write Only (Processor), Read Only ~gost) Field NameBits Function res 3~ Reserved, write 0 Mailbox register value. This value is writeable by the PicoEngine and readable by data 31-0 the host CPU for communication between the PicoEngine and host. The data contained in this register is a lication-de endent.

MAILBOX R - Mailbox Register from Host - Read Only (Processor), Write Only (Host) Field NameSits Function res 3~ Reserved, write 0 Mailbox register value. This value is readable by the PicoEngine and writeable by data 31-0 the host CPU for communication between the PicoEngine and host. The data contained in this re inter is a plication-de endent.

CTR 32 - Counter 32 Register - Read Only Field NameBits Function Value of counter 3, also used for external counter3 39-20 memor address high bits.

Value of counter 2, also used for external counter2 19-0 memory address low bits.

1~ CTR_INC - Counter Increment Register - Write Only Field NameBits Function Writing this register increments any counter programmed to increment on a write to CTR INC (as determined by the x 39-0 ctr* inc on wr bits in the PERIPH CTRL

register).-The value written is irrelevant.

CTR_DATA - Counter Data Register - Write Only Field NameBits Function This data is written to counters 3 and 1 when those counters are enabled by the ctr 31 39-20 - corresponding ctr_wren bits in the PERIPH_CTRL re inter.

This data is written to counters 2 and 0 when those counters are enabled by the ctr 19-0 _ corresponding ctr_wren bits in the PERIPH CTRL re inter.

ENG_CTRL - Control Register - Write Only Field NameBits Function res 38 Reserved, write 0 Register bank read enable. Selects which register bank will be read when a register (r[0] through r[15]) is used as a source in Data Compare or Data Modify instructions.

Each bank includes 16 independent registers. Background-running instructions read from the bank that was active at the time the background-running instruction was reg bank 3~_ issued. [Note: Engines currently only ren 36 support Bank 0 unless specially configured during hardware synthesis. Ask PG if in doubt ] .

11: Bank 3 10: Bank 2 01: Bank 1 00: Bank 0 Write enable bits for the four register banks. Selects which banks will be written when the Data Modify unit writes a register (r[0] through r[15]). Each bank includes 16 f0 independent registers. More than one bank may be written simultaneously. [Note:

Engines currently only support Bank 0 unless specially configured during hardware reg bank 35- synthesis. Ask PG if in doubt].

wen 32 f5 lxxx: Enable bank 3 for write; Oxxx:

disable xlxx: Enable bank 2 for write; xOxx:

disable xxlx: Enable bank 1 for write; xxOx:

disable 30 xxxl: Enable bank 0 for write; xxx0:

disable Output bus 1 update enable. When this bit is 1, the output bus is in passthrough mode and passes data from its default source outl en 31 - whenever the bus is not being written by a Data Modify instruction. When 0, the bus holds its revious value.

out0 en 30 Same as above, for out ut bus 0.

Selects the default source for output bus 1. The data from this source is passed to the output bus whenever a Data Modify instruction isn't updating the bus, and the 29 bus update enable (outl en) is 1. The outl src values for src are:

0: input bus 0 passthrough pipeline 1: input bus 1 passthrough pipeline The number of clocks of input to output dela is set b the p1 word_sel field.

out0 src 28 Same as above, for output bus 0.

Word select for the in1 to output bus passthrough pipeline. This gives the number of clocks (equal to p1 word sel + 2) of p1 word _ 27- delay between input bus 1 and the output sel 24 bus in passthrough mode. An output bus is in passthrough mode whenever it isn't being updated by a DM instruction, and its out en field is 1.

p0 word- 23- Same functionality as above, for the in0 to sel 20 out ut bus passthrou h pipeline.

DC instruction compare flag update control.

Used in conjunction with the DC control field flag update() to set the compare flag update mode as follows:

flag upd cfg flan upd cfa update Update mode Selects the comparator mode (0 = equality, 1= magnitude) for each DC comparator. In equality mode, the comparator result is 1 comp mod 18- if (data & mask) -- match, otherwise 0. In a 14 magnitude mode, the result is 1 if (data &

mask) >= match, otherwise 0.

[Ma nitude mode issues and descri tion]

Enable for Data Compare input pipeline B.

0- disable pipeline (does not advance) pb_en 13 1: enable pipeline (advances 1 word per instruction) Source bus for Data Compare input pipeline B (one bit per input bus byte).

pb 12-8 src _ 0: input bus 0 1: in ut bus 1 res 7-6 Reserved, write 0 Enable for Data Compare input pipeline A.

0: disable pipeline (does not advance) pa en 5 1: enable pipeline (advances 1 word per instruction) Source bus for Data Compare input pipeline A (one bit per input bus byte).

pa_src 4-0 0: input bus 0 1: in ut bus 1 TRAP_CTRL- Trap Control Register - Write Only Field NameBits Function res 32 Reserved, write 0 Trap relative address enable. When 1, trap addr is treated as a sign-extended relative address from the current PC; a trap_rel 31 trap causes control to transfer to the PC
+

ative trap addr. When 0, trap addr is treated as an absolute address; a trap causes control to transfer to tra _addr.

Trap restore. When 1, enables restoring the state of the trap_en bit after a return tra p res 0 from the trap routine. Otherwise, trap en tor e remains disabled after the return from the tra routine.

Trap enable. Enables traps when 1, disables them when 0. When the trap is enabled and its match/mask/tf condition is satisfied, control transfers to the target address specified by the trap_addr and trap_relative fields.

Trap en is cleared upon entry to the trap trap en 29 routine, thus disabling further traps. If trap restore is set, the bit will be restored to its value before the trap upon return from the trap routine (which occurs via a branch to the saved PC). However, if software writes this bit before the trap routine returns, the bit written will be reserved a on the return.

Trap on match/mask true/false. Determines whether trap should be taken if its trap_f 28 match/mask condition is true (trap_f = 0) or false ( tra f = 1 ) .

Trap condition match bits. These bits specify the trap condition in the same manner as the branch/execute condition bits.

trap mat 27- bits 27-26 . match bits for external ch 20 interrupts 1-0 respectively bit 25 . match bit for the Peripheral flag bits 24-20 . match bits for Data Compare fla s 4-0 res ectivel Trap condition mask bits. These bits specify the trap condition in the same manner as the branch/execute condition bits.

trap mas 19- bits 19-18 . mask bits for external k 12 interrupts 1-0 respectively bit 17 . mask bit for the Peripheral flag bits 16-12 . mask bits for Data Compare flags 4-0 respectivel res 1~ Reserved, write 0 Trap destination address.

Holds the target address for traps. Control is transferred to trap addr (if trap relative = 0) or the current PC +

trap_add trap_addr (if trap relative = 1) when traps r are enabled and the trap match/mask/tf condition is satisfied. Indirect branching may be implemented by writing the target address to this field and trapping on an alwa s-satisfied condition.

PERIPH_CTRL - Peripheral Control Register - Write Only Field NameBits Function res 39 Reserved, write 0 Count on match/mask true/false. Determines whether counting should occur if the ct_f 38 match/mask condition is true (ct_f = 0) or false (ct f = 1) .

Count enable condition mask bits. These bits specify the count condition (when count enable on match/mask/tf is configured 37- by ctr* ie sel) in the same manner as the ct mask 32 branch/execute condition bits.

bit 37 . mask bit for the Peripheral flag bits 36-32 . mask bits for Data Compare flags 4-0 respectively pf_en hi 3~ (See pf en) Count enable condition match bits. These bits specify the count condition (when count enable on match/mask/tf is configured by ctr* ie_sel) in the same manner as the ct match branch/execute condition bits.

bit 29 . match bit for the Peripheral flag bits 28-24 . match bits for Data Compare flags 4-0 respectively Counter write enables. These bits enable one or more of the counters for writing when the CTR DATA register is written.

bit 23: 1 = enable write to counter 3, 0 =

disable ctr wren 2o bit 22: 1 = enable write to counter 2, 0 =

disable bit 21: 1 = enable write to counter 1, 0 =

disable bit 20: 1 = enable write to counter 0, 0 =

disable Peripheral flag enable bits, used in combination with pf en hi. Selects the sources) of the Peripheral flag (the P bit of the Flags register) used in branch, execute, trap, and count conditions. All sources with an enable bit of 1 are logically ANDed to generate the P bit;

sources with an enable bit of 0 are ignored.

pf en hi, pf_en, source:

1x xxxx: Data Modify unit ALU3 carry flag x1 xxxx: EXT RDY (ready flag) signal from External Memory Interface pf en xx lxxx: Counter 3 wrap flag; 1 when counter 3 wraps from Oxfffff to 0 xx xlxx: Counter 2 wrap flag; 1 when counter 2 wraps from Oxfffff to 0 xx xxlx: Counter 1 wrap flag; 1 when counter 1 wraps from Oxfffff to 0 xx xxxl: Counter 0 wrap flag; 1 when counter 0 wraps from Oxfffff to 0 Note: each counter wrap flag maintains its state until the counter is next updated, either by an increment or software write.

Software writes to the CTR DATA register reset the wrap flags of any counters written to.

Counter 3 increment enable on peripheral register write. If this bit is 1, counter ~5 will be incremented on any write to the inc CTR_INC register as well as any conditions ctr3 _ 15 on wr generated due to the ctr3 ie_sel bits. If this bit is 0 or whenever CTR_INC is not written, counting is controlled by the ctr3 ie sel bits.

Counter 3 default increment enable bits.

Selects the condition for incrementing counter 3.

111: increment when previous counter wraps (cascade with previous) ctr3 ie_ 14- 110: increment always sel 12 100: increment when counter mask/match/tf condition is satisfied 000: increment on external memory interface read or write (memory address autoincrement) others: reserved inc Same functionality as ctr3 inc on wr, for ctr2 _ 11 _on_wr counter 2.

Same functionality as ctr3 ie sel, for - -ctr2 ie - - 10-8 counter 2, with the following exception:

sel 0111: don't increment inc Same functionality as ctr3_inc on wr, for ctrl _ 7 _on wr counter 1.

ctrl ie_ Same functionality as ctr3_ie_sel, for sel counter 1.

ctr0 inc Same functionality as ctr3_inc on wr, for _on_wr counter 0.

Same functionality as ctr3_ie_sel, for ctr0 ie - - 2-0 counter 0, with the following exception:

sel 111: don't increment

Claims (39)

WHAT IS CLAIMED IS:

1. A processor synchronous with an instruction clock signal, comprising:
an execution control unit synchronous with the instruction clock signal and operable to execute an instruction per clock cycle of the instruction clock signal;
an input pipeline unit synchronous with the instruction clock signal and operable to receive a stream of input data words one data word per clock cycle of the instruction clock signal, the input pipeline unit further operable to selectively output one input data word per clock cycle of the instruction clock signal;
a data modify unit coupled to the input pipeline unit, the data modify unit operable to selectively modify input data words received form the input pipeline unit according to instruction-specified operators to generate modified data words one modified data word per clock cycle of the instruction clock signal; and a processor output selector operable to selectively output, at each clock cycle of the instruction clock signal, an instruction-specified one of the input data words and the modified data words; and a data compare unit coupled to the input pipeline unit, the data compare unit operable to selectively compare input data words received from the input pipeline unit to instruction-specified operands to generate compare flags, and the execution control unit being operable to configure during each clock cycle of the instruction clock signal at least one of the data modify unit and the data compare unit according to a current instruction.

2. The processor of claim 1, wherein the execution control unit is operable to determine a next instruction to be processed according to compare flags generated by the data compare unit during a current clock cycle of the instruction clock signal and a branch operator specified in the current instruction.

3. The processor of claim 1, wherein the input pipeline unit comprises:
a plurality of successive stages each having an output, each respective stage operable to output a respective one of the input data words after a delay of a number of clock cycles of the instruction clock signal corresponding to a position of the respective stage in the input pipeline unit; and an output multiplexes coupled to at least a subset of the stages of the input pipeline unit, the output multiplexes operable to select for output to the data modifying unit and the data compare unit an instruction-specified one of the outputs from the subset of the stages of the input pipeline unit.

4. The processor of claim 1, further comprising:
a register bank accessible by the execution control unit, the data compare unit and the data modify unit, the register bank operable to store data for the execution control unit, the data compare unit and the data modify unit; and a peripheral unit accessible by the data modify unit, the peripheral unit for storing instruction-specified data therein.

5. The processor of claim 1, wherein the processor output selector comprises a multiplexes coupled to the input pipeline unit and the data modify unit to receive, respectively, the input data words and the modified data words.

6. The processor of claim 1, wherein the data modify unit comprises arithmetic logic units operable to perform instruction-specified operations on the input data words.

7. The processor of claim 1, wherein the execution control unit is operable to execute one instruction having at least two branch control operators during each clock cycle of the instruction clock signal.

8. The processor of claim 1, wherein the execution control unit is operable to execute one conditional instruction during each clock cycle of the instruction clock signal.

9. The processor of claim 1, wherein the execution control unit is operable to repeat execution of a current instruction having a background mode operator during a next clock cycle of the instruction clock signal.

10. A processor synchronous with an instruction clock signal, the processor comprising:
an input pipeline unit operable to receive a plurality of input data words at a rate of one input data word per clock cycle of the instruction clock signal;
an execution control unit;
an instruction memory storing instructions for execution by the execution control unit, wherein the execution control unit is operable to execute, during each clock cycle of the instruction clock signal, one of the instructions so as to control an instruction-specified operation on an instruction-specified one of the input data words in the input pipeline unit;
a data modify unit coupled to the input pipeline unit, the data modify unit operable to selectively modify, during each clock cycle of the instruction clock signal, an input data word received from the input pipeline unit in accordance with an instruction specified operator, the data modify unit further operable to generate a modified output data word; and a processor output selector coupled to the input pipeline unit and the data modify unit, the processor output selector operable to selectively output, at each clock cycle of the instruction clock signal, one of the input data words and the modified data words.

11. The processor of claim 10, further comprising:
a data compare unit coupled to the input pipeline unit, the data compare unit operable to selectively compare during each clock cycle of the instruction clock signal an input data word received from the input pipeline unit with an instruction specified operand and generating a resultant set of compare flags.

12. The processor of claim 11, wherein the execution control unit is operable to configure, during each clock cycle of the instruction clock signal, at least one of the data modify unit and the data compare unit in accordance with a current instruction.

13. The processor of claim 12, wherein the execution control unit is operable to determine a next instruction to be executed in accordance with the compare flags generated by the data compare unit in a current clock cycle of the instruction clock signal and a branch control operator in the current instruction.

14. The processor of claim 10, wherein the input pipeline unit comprises:
a plurality of successive stages each having an output, each respective stage outputting a respective one of the input data words after a delay of a number of clock cycles of the instruction clock signal corresponding to a position of the respective stage in the input pipeline unit; and an output multiplexer coupled to at least a subset of the stages of the input pipeline unit, the output multiplexer operable to select for output to the data modifying unit an instruction-specified one of the outputs from the subset of the stages of the input pipeline unit.

15. The processor of claim 11, further comprising:
a register bank accessible by the execution control unit, the data compare unit and the data modify unit, the register bank operable to store data for the execution control unit, the data compare unit and the data modify unit; and a peripheral unit accessible by the data modify unit, the peripheral unit for storing instruction-specified data therein.

16. The processor of claim 10, wherein the data modify unit comprises arithmetic logic units operable to perform instruction-specified operations on the input data words.

17. The processor of claim 10, wherein the execution control unit is operable to execute one instruction having at least two branch control operators during each clock cycle of the instruction clock signal.

18. The processor of claim 10, wherein the execution control unit is operable to execute one conditional instruction during each clock cycle of the instruction clock signal.

19. The processor of claim 10, wherein the execution control unit is operable to repeat execution of a current instruction having a background mode operator during a next clock cycle of the instruction clock signal.

20. A processor synchronous with an instruction clock signal, comprising:
an input pipeline unit operable to continuously receive a stream of input data words including one data word during each clock cycle of the instruction clock signal, the input pipeline unit further operable to output successive ones of the data words during successive clock cycles of the instruction clock signal;
a data modify unit coupled to the input pipeline unit, said data modify unit operable to selectively modify during each clock cycle of the instruction clock signal an input data word received from the input pipeline unit in accordance with an instruction specified operator and generating a resultant output data word;
a data compare unit coupled to the input pipeline unit, said data compare unit operable to selectively compare during each clock cycle of the instruction clock signal an input data word received from the input pipeline unit with an instruction specified operand and generating a resultant set of compare flags; and an execution control unit, coupled to the data modify unit and data compare unit, the execution control unit operable to configure during each clock cycle of the instruction clock signal at least one of the data modify unit and the data compare unit in accordance with a current instruction, the execution control unit further being operable to repeat execution of a current instruction having a background mode operator during a next clock cycle of the instruction clock signal.

21. The processor of claim 20, the execution control unit operable to determine a next instruction to be processed by the execution control unit in accordance with the compare flags generated during a current clock cycle of the instruction clock signal and a branch control operator in the current instruction.

22. The processor of claim 20, wherein the input pipeline unit comprises: a plurality of successive stages each having an output, each respective stage operable to output a respective one of the input data words after a delay of a number of clock cycles of the instruction clock signal corresponding to a position of the respective stage in the input pipeline unit; and an output multiplexer coupled to at least a subset of the stages of the input pipeline unit, the output multiplexer operable to select for output to the data modifying unit an instruction-specified one of the outputs from the subset of the stages of the input pipeline unit.

23. The processor of claim 22, wherein the output multiplexer is operable to select for output to the data compare unit an instruction-specified one of the outputs from the subset of the stages of the input pipeline unit.

24. The processor of claim 20, wherein the input pipeline unit comprises:
first and second input pipelines, each pipeline having a plurality of successive stages each having an output, each respective stage operable to output a respective input data word of a first stream and a second stream of input data words after a delay of a number of clock cycles of the instruction clock signal corresponding to a position of the respective stage in the input pipeline unit;
a first output multiplexer coupled to at least a first subset of the stages of the first input pipeline, the first output multiplexer operable to select for output to the data modify unit an instruction-specified one of the outputs from the first subset of the stages of the first input pipeline; and a second output multiplexer coupled to at least a second subset of the stages of the second pipeline, the second output multiplexer operable to select for output to the data modify unit an instruction-specified one of the outputs from the second subset of the stages of the second input pipeline.

25. The processor of claim 24, further comprising:
a register bank accessible by the execution control unit, the data compare unit and the data modify unit, the register bank storing data for the execution control unit, the data compare unit and the data modify unit; and a peripheral unit accessible by the data modify unit, the peripheral unit for storing instruction-specified data therein.

26. The processor of claim 25, wherein the data modify unit comprises:
a first input multiplexer coupled to the first and second output multiplexers of the input pipeline unit, the register bank and the peripheral unit, the first input multiplexer operable to selectively receive data from an instruction-specified one of the first and second output multiplexers, a memory location of the register bank and a memory location of the peripheral unit; and a second input multiplexer coupled to the first and second output multiplexers of the input pipeline unit, the register bank and the peripheral unit, the second input multiplexer operable to selectively receive data from an instruction-specified one of the first and second output multiplexers, a memory location of the register bank and a memory location of the peripheral unit.

27. The processor of claim 26, wherein the data modify unit comprises:
a first arithmetic logic unit coupled to the output of the first input multiplexer of the data modify unit, the first arithmetic logic unit selectively performing an instruction-specified operation on data provided by the first input multiplexer of the data modify unit; and a second arithmetic logic unit coupled the output of the second input multiplexer of the data modify unit, the second arithmetic logic unit selectively performing an instruction-specified operation on data provided by the second input multiplexer of the data modify unit.

28. The processor of claim 27, wherein the data modify unit comprises:
a third arithmetic logic unit coupled to the outputs of the first and second arithmetic logic units, the third arithmetic logic unit performing an instruction-specified operation on data provided by outputs of the first and second arithmetic logic units.

29. The processor of claim 28, wherein the input pipeline unit comprises:
first and second pass-through pipelines, each pipeline having a plurality of successive stages each having an output, each respective stage outputting a respective input data word of the first and second streams of input data words after a delay of a number of clock cycles of the instruction clock signal corresponding to a position of the respective stage in the input pipeline unit;
a third output multiplexer coupled to at least a third subset of the stages of the first pass-through pipeline, the third output multiplexer operable to select for output to the data modify unit an instruction-specified one of the outputs from the third subset of the stages of the first pass-through pipeline; and a fourth output multiplexer coupled to at least a fourth subset of the stages of the second pass-through pipeline, the fourth output multiplexer operable to select for output to the data modify unit an instruction-specified one of the outputs from the fourth subset of the stages of the second pass-through pipeline.

30. The processor of claim 29, wherein the data modify unit comprises:
a first data modify unit output multiplexer coupled to outputs of the first and third arithmetic logic units, and coupled to outputs of the third and fourth output multiplexers of the input pipeline unit, the first data modify unit output multiplexer operable to select for output an instruction-specified one of the outputs of the first and third arithmetic logic units and the outputs of the third and fourth output multiplexers of the input pipeline unit; and a second data modify unit output multiplexes coupled to outputs of the second and third arithmetic logic units, and coupled to outputs of the third and fourth output multplexers of the input pipeline unit, the second data modify unit output multiplexes operable to select for output an instruction-specified one of the outputs of the second and third arithmetic logic units and the outputs of the third and fourth output multiplexers of the input pipeline unit.

31. The processor of claim 25, wherein the data compare unit comprises:
a plurality of source select and mask units, each source select and mask unit operable to select as mask operands instruction-specified ones of the outputs of the first and second output multiplexers of the input pipeline unit, an output of the register bank, an output of the peripheral unit, and an immediate data output of the execution control unit, each source select and mask unit generating a masked output;
each source select and mask unit operable to select as compare operands instruction-specified ones of the outputs of the first and second output multiplexers of the input pipeline unit, an output of the register bank, an output of the execution control unit and an immediate data output of the execution control unit, each source select and mask unit generating a compare output; and a plurality of comparators coupled to the outputs of the source select and mask units, the comparators generating compare results of comparing the masked outputs and the compare outputs of the source select and mask units.

32. The processor of claim 31, wherein the data compare unit comprises:
a plurality of flag update units coupled to the outputs of the comparators, the flag update units performing an instruction-specified logic operation on the compare results and a set of compare flags generated in a previous clock cycle of the instruction clock signal to generate the resultant compare flags.

33. The processor of claim 20, wherein the execution control unit is operable to executing one instruction having at least two branch control operators during each clock cycle of the instruction clock signal.

34. The processor of claim 20, wherein the execution control unit is operable to executing one conditional instruction during each clock cycle of the instruction clock signal.

35. A protocol independent unit synchronous processor for processing network data, comprising:
a plurality of components that are collectively operable to implement I/O
processing of network data, the plurality of components comprising:
an execution control unit synchronous with an instruction clock signal, the execution control unit operable to execute an instruction per clock cycle of the instruction clock signal;
an input interface synchronous with the instruction clock signal, the input interface operable to receive network data at a rate of one data word per clock cycle of the instruction clock signal; and a plurality of configurable units synchronous with the instruction clock signal, the plurality of configurable units operable to process the received network data in real time under control of the execution control unit.

36. The protocol independent synchronous processor of claim 35 further comprising a plurality of configurable connections operable to interconnect the plurality of configurable units in real time under control of the execution control unit.

37. The protocol independent synchronous processor of claim 36 wherein the execution control unit is operable to configure the plurality of configurable units and the plurality of configurable connections in accordance with any selected network protocol of a multiplicity of predefined network protocols so as to configure the processor to process the received network data in real time in a manner consistent with the selected network protocol.

38. The protocol independent synchronous processor of claim 37 further comprising an instruction memory configured to store software instructions for the execution control unit, wherein the instructions define a procedure executable by the execution control unit, the procedure corresponding to the selected network protocol.

39. A protocol independent synchronous processor for processing network data, comprising: an input interface for receiving the network data; a plurality of software configurable units for processing a sequence of data words of the network data in real time, at a rate corresponding to a rate at which the network data is received at the input interface;
software configurable connections for interconnecting the plurality of software configurable units and input interface; and a software execution unit, coupled to the plurality of software configurable units and software configurable connections, the software execution unit operable for configuring the plurality of software configurable units and software configurable connections in accordance with any selected network protocol of a predefined multiplicity of network protocols so as to configure the processor to process the received network data in real time in a manner consistent with the selected network protocol.