CA2432322A1 - Packet encrypton system and method - Google Patents
Packet encrypton system and method Download PDFInfo
- Publication number
- CA2432322A1 CA2432322A1 CA002432322A CA2432322A CA2432322A1 CA 2432322 A1 CA2432322 A1 CA 2432322A1 CA 002432322 A CA002432322 A CA 002432322A CA 2432322 A CA2432322 A CA 2432322A CA 2432322 A1 CA2432322 A1 CA 2432322A1
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- data
- processor
- packet
- processing
- processors
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9036—Common buffer combined with individual queues
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
- H04L63/0485—Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/34—Network arrangements or protocols for supporting network services or applications involving the movement of software or configuration parameters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/329—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the application layer [OSI layer 7]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
Abstract
A processor has an input port for receiving packets of data to be processed for encryption. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. the packet with the appended header information is stored within a buffer. A buffer controller acts to dtermine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.
Claims (46)
1. A data encryption system comprising:
a control process which modifies a received packet to include control data which identifies processes to be performed on the packet;
a plurality of processors which perform the processes identified by the control data, including an encryption process;
an interconnection which responds to control data in the packet to forward the packet with control data from processor to processor; and an output from which the processed packet is forwarded without the control data.
a control process which modifies a received packet to include control data which identifies processes to be performed on the packet;
a plurality of processors which perform the processes identified by the control data, including an encryption process;
an interconnection which responds to control data in the packet to forward the packet with control data from processor to processor; and an output from which the processed packet is forwarded without the control data.
2. The system as claimed in Claim 1 wherein the interconnection comprises a packet buffer including a buffer controller which determines a next processor of the plurality of processors to process the data packet.
3. A system as claimed in Claim 2 wherein the buffer controller includes a resource manager which maintains information on resource processor availability.
4. A system as claimed in any of Claims 1-3 wherein the control data includes code to be processed in at least one of the processors.
5. A system as claimed in any of Claims 1-4 wherein the control data further includes an encryption or authentication key.
6. A system as claimed in any of Claims 1-5 wherein individual processors add result data to the control data.
7. The system as claimed in any of Claims 1-6 wherein the processors perform IPSEC protocol processing.
8. A system as claimed in any of Claims 1-7 wherein respective processors perform IP header manipulation and encryption.
9. A system as claimed in any of Claims 1-8 wherein a processor performs authentication processing.
10. A method of encrypting or decrypting data packets comprising:
modifying a received packet to include control data which identifies processes to be performed on the packet; and in successive processors, performing the processes identified by the control data, including an encryption or decryption process.
modifying a received packet to include control data which identifies processes to be performed on the packet; and in successive processors, performing the processes identified by the control data, including an encryption or decryption process.
11. A method as claimed in Claim 10 wherein the packet is forwarded from processor to processor through an interconnection which responds to control data in the packets.
12. A method as claimed in Claim 11 wherein the interconnection comprises a packet buffer including a buffer controller which determines a next processor of the plurality of processors to process the data packet.
13. A method as claimed in Claim 12 wherein the buffer controller includes a resource manager which maintains information on resource processor availability.
14. A method as claimed in any of Claims 10-13 wherein the control data includes code to be, processed in at least one of the processors.
15. A method as claimed in any of Claims 10-14 wherein the control data further includes an encryption or authentication key.
16. A method as claimed in any of Claims 10-15 wherein individual processors add result data to the control data.
17. The method as claimed in any of Claims 10-16 wherein the processors perform IPSEC protocal processing.
18. A method as claimed in any of Claims 10-17 wherein respective processors perform IP header manipulation and encryption.
19. A method as claimed in any of Claims 10-18 wherein a processor performs authentication processing.
20. A data processor for processing data comprising:
an input port for receiving packets of data;
at least a port for communication with each of a plurality of processors;
a first processor in communication with the at least a port and for processing received data to provide a header including a list of processes to perform on the packet of data and an ordering thereof, the header stored within a packet of data to which the header relates;
a buffer for storing data received from the at least a port ;
a buffer controller for determining based on the header within a packet a next processor of the plurality of processors to process said data packet and for providing said data packet to the at least a port for provision to the next processor.
an input port for receiving packets of data;
at least a port for communication with each of a plurality of processors;
a first processor in communication with the at least a port and for processing received data to provide a header including a list of processes to perform on the packet of data and an ordering thereof, the header stored within a packet of data to which the header relates;
a buffer for storing data received from the at least a port ;
a buffer controller for determining based on the header within a packet a next processor of the plurality of processors to process said data packet and for providing said data packet to the at least a port for provision to the next processor.
21. A data processor for processing data as defined in claim 20 wherein first processor includes means for providing executable code to the next processor, the executable code for being executed to process an associated packet.
22. A data processor for processing data as defined in claim 20 wherein first processor includes means for providing an indication of executable code to provide to the next processor, the executable code for being. executed to process an associated packet.
23. A data processor for processing data as defined in claim 20 wherein the buffer controller is for determining the next processor from a plurality of available processors each of which is a possible next processor.
24. A data processor for processing data as defined in claim 20 further comprising the plurality of processors.
25. A data processor for processing data as defined in claim 24 wherein the plurality of processors is a plurality of special propose processors.
26. A data processor for processing data as defined in claim 25 wherein the plurality of special purpose processors includes cryptographic processors having secret keys stored therein and inaccessible from outside the cryptographic processor device.
27. A data processor for processing data as defined in claim 26 wherein the plurality of special purpose processors includes a plurality of processors for performing aspects of network security protocol processing in order to support at least a network security protocol.
28. A data processor for processing data comprising:
a buffer for storing data;
a plurality of special purpose processors, each for processing data from within the buffer;
a buffer controller in communication with each special purpose processor, for determining a next processor of the special purpose processors to process the data, and for providing the data to the determined next processor.
a buffer for storing data;
a plurality of special purpose processors, each for processing data from within the buffer;
a buffer controller in communication with each special purpose processor, for determining a next processor of the special purpose processors to process the data, and for providing the data to the determined next processor.
29. A data processor for processing data as defined in claim 28 wherein the plurality of special purpose processors includes at least a server processor for formatting data into a data structure including a header having a list of processes to perform on the data and an ordering thereof.
30. A data processor for processing data as defined in claim 29 wherein the buffer controller is for determining a next process in dependence upon the list of processes to perform on the data and the ordering thereof.
31. A data processor for processing a packet of data comprising:
an addressing network;
a plurality of special purpose processors, each for processing data received via the addressing network and for providing processed data to the addressing network, the addressing network interconnecting the plurality of special purpose processors;
a first processor for providing data for use in directing a packet of data through the addressing network to a plurality of processors one after another in a predetermined order, the data associated with the packet, wherein different packets are provided with different data for directing them differently through the addressing network and wherein each special purpose processor is for performing a function absent knowledge of the overall high level packet processing operation.
an addressing network;
a plurality of special purpose processors, each for processing data received via the addressing network and for providing processed data to the addressing network, the addressing network interconnecting the plurality of special purpose processors;
a first processor for providing data for use in directing a packet of data through the addressing network to a plurality of processors one after another in a predetermined order, the data associated with the packet, wherein different packets are provided with different data for directing them differently through the addressing network and wherein each special purpose processor is for performing a function absent knowledge of the overall high level packet processing operation.
32. A data processor for processing a packet of data as defined in claim 31 wherein each processor is for receiving executable instructions and for executing same, the executable instructions provided to the processor along a different data path than the data packet.
33. A data processor for processing a packet of data as defined in claim 31 wherein each processor is for receiving executable instructions and for executing same, the executable instructions provided to the processor along a same data path than the data packet.
34. A method for processing stream data comprising:
receiving stream data including packets of data at an input port;
processing received data packets to provide for each a header including a list of processes to perform on the packet and an ordering thereof, the header stored within the packet to which the header relates;
providing the packet with the associated header to a buffer for storage;
for each packet within the buffer:
determining based on the header within the packet a next processor to process the packet;
providing the packet to the determined next processor for processing;
receiving the processed packet from the processor and storing it in the buffer, the stored packet including one of an indication that processing by the next processor is complete and that no processing by the next processor is required; and, when no further processes are indicated in a header of a packet, providing the packet to an output port.
receiving stream data including packets of data at an input port;
processing received data packets to provide for each a header including a list of processes to perform on the packet and an ordering thereof, the header stored within the packet to which the header relates;
providing the packet with the associated header to a buffer for storage;
for each packet within the buffer:
determining based on the header within the packet a next processor to process the packet;
providing the packet to the determined next processor for processing;
receiving the processed packet from the processor and storing it in the buffer, the stored packet including one of an indication that processing by the next processor is complete and that no processing by the next processor is required; and, when no further processes are indicated in a header of a packet, providing the packet to an output port.
35. A method for processing stream data as defined in claim 34 wherein prior to providing the packet to the output port, the header information is stripped therefrom.
36. A method for processing stream data as defined in claim 35 wherein the method is implemented within a single integrated device.
37. A method for processing stream data as defined in claim 35 wherein the method is implemented within a single integrated device absent at least some of the next processors and wherein the at least some next processors are in communication with the integrated device.
38. A method for processing stream data as defined in claim 37 wherein the integrated device includes an input port, an output port, a server processor for providing the header information and a data buffer for storing packet data and for routing the packet data between next processors.
39. A method for processing stream data as defined in claim 38 wherein the server processor is programmable.
40. A method for processing stream data as defined in claim 38 wherein the input poet and the output port include data elements for ingress and outgress processing respectively.
41. An architecture for processing data comprising:
a first processing element for receiving data and for formatting the data with a list of processes selected from available processes and an ordering thereof, the list of processes for being performed on the data;
further processors for performing at least one process from the available processes; and, a routing memory for providing data to processors for performing the processes according to the ordering of the listed processes.
a first processing element for receiving data and for formatting the data with a list of processes selected from available processes and an ordering thereof, the list of processes for being performed on the data;
further processors for performing at least one process from the available processes; and, a routing memory for providing data to processors for performing the processes according to the ordering of the listed processes.
42. An architecture for processing data according to claim 41 wherein the routing memory comprises a packet buffer memory for buffering packets and a processor for determining an appropriate processor for processing the formatted data and for providing the data to said processor.
43. An architecture for processing data according to claim 41 wherein the routing memory comprises an address switching network for routing a packet between processors in a predetermined order according to the list of processes and the ordering thereof wherein the address switching network is dynamic allowing a packet to be routed between further processors in accordance with any of a variety of process lists and orders.
44. An architecture for processing data according to claim 41 wherein some of the further processors are dedicated single function processors for processing the data.
45. An architecture for processing data according to claim 44 wherein a majority of the further processors are dedicated single function processors for processing the data.
46. An architecture for processing data according to claim 45 wherein a majority of the further processors are processor modules for interfacing with the routing memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA2777505A CA2777505C (en) | 2000-12-22 | 2001-12-21 | Packet processing system and method |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/741,829 | 2000-12-22 | ||
US09/741,829 US6959346B2 (en) | 2000-12-22 | 2000-12-22 | Method and system for packet encryption |
PCT/CA2001/001858 WO2002052777A2 (en) | 2000-12-22 | 2001-12-21 | Packet encrypton system and method |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA2777505A Division CA2777505C (en) | 2000-12-22 | 2001-12-21 | Packet processing system and method |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2432322A1 true CA2432322A1 (en) | 2002-07-04 |
CA2432322C CA2432322C (en) | 2012-07-24 |
Family
ID=24982383
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA2777505A Expired - Fee Related CA2777505C (en) | 2000-12-22 | 2001-12-21 | Packet processing system and method |
CA2432322A Expired - Fee Related CA2432322C (en) | 2000-12-22 | 2001-12-21 | Packet encrypton system and method |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA2777505A Expired - Fee Related CA2777505C (en) | 2000-12-22 | 2001-12-21 | Packet processing system and method |
Country Status (7)
Country | Link |
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US (4) | US6959346B2 (en) |
EP (2) | EP1354442A2 (en) |
KR (1) | KR100908765B1 (en) |
CN (2) | CN1284327C (en) |
AU (1) | AU2002218909A1 (en) |
CA (2) | CA2777505C (en) |
WO (1) | WO2002052777A2 (en) |
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-
2000
- 2000-12-22 US US09/741,829 patent/US6959346B2/en not_active Expired - Lifetime
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2001
- 2001-12-21 EP EP01271934A patent/EP1354442A2/en not_active Withdrawn
- 2001-12-21 CA CA2777505A patent/CA2777505C/en not_active Expired - Fee Related
- 2001-12-21 WO PCT/CA2001/001858 patent/WO2002052777A2/en not_active Application Discontinuation
- 2001-12-21 CN CNB018217931A patent/CN1284327C/en not_active Expired - Lifetime
- 2001-12-21 AU AU2002218909A patent/AU2002218909A1/en not_active Abandoned
- 2001-12-21 EP EP10184867A patent/EP2299653A1/en not_active Withdrawn
- 2001-12-21 KR KR1020037008413A patent/KR100908765B1/en active IP Right Grant
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2005
- 2005-10-25 US US11/257,525 patent/US7631116B2/en not_active Expired - Fee Related
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2009
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AU2002218909A1 (en) | 2002-07-08 |
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CA2432322C (en) | 2012-07-24 |
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CN1486555A (en) | 2004-03-31 |
CN1964251B (en) | 2012-07-25 |
US9325811B2 (en) | 2016-04-26 |
EP2299653A1 (en) | 2011-03-23 |
CA2777505A1 (en) | 2002-07-04 |
KR100908765B1 (en) | 2009-07-22 |
CN1964251A (en) | 2007-05-16 |
US20020087708A1 (en) | 2002-07-04 |
CN1284327C (en) | 2006-11-08 |
US7631116B2 (en) | 2009-12-08 |
US8639912B2 (en) | 2014-01-28 |
WO2002052777A3 (en) | 2002-09-26 |
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