CA2438871A1 - Solid-state quantum dot devices and quantum computing using nanostructured logic gates - Google Patents

Solid-state quantum dot devices and quantum computing using nanostructured logic gates Download PDF

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Publication number
CA2438871A1
CA2438871A1 CA002438871A CA2438871A CA2438871A1 CA 2438871 A1 CA2438871 A1 CA 2438871A1 CA 002438871 A CA002438871 A CA 002438871A CA 2438871 A CA2438871 A CA 2438871A CA 2438871 A1 CA2438871 A1 CA 2438871A1
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layer
quantum dot
dot device
quantum
gates
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French (fr)
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CA2438871C (en
Inventor
Mark A. Eriksson
Mark G. Friesen
Robert J. Joynt
Max G. Lagally
Daniel W. Van Der Weide
Paul Rugheimer
Donald E. Savage
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Wisconsin Alumni Research Foundation
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/933—Spintronics or quantum computing

Abstract

Semiconductor dot devices include a multiple layer semiconductor structure having a substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate, and a barrier layer above the quantum well layer. Multiple electrode gates are formed on the multi-layer semiconductor with the gates spaced from each other by a region beneath which quantum dots may be defined. Appropriate voltages applied to the electrodes allow the development and appropriate positioning of the quantum dots, allowing a large number of quantum dots be formed in a series with appropriate coupling between the dots.

Claims (23)

1. A semiconductor quantum dot device comprising:

(a) a multi-layer semiconductor structure including a semiconductor substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate layer, and an upper barrier layer above the quantum well layer; and (b) a plurality of spaced electrode gates formed on the multi-layer semiconductor structure, the electrode gates spaced from each other by a region beneath which quantum dots may be defined.
2. A semiconductor quantum dot device comprising:

(a) a multi-layer semiconductor structure including a semiconductor substrate, a back gate electrode layer, a quantum well layer, a tunnel barrier layer between the quantum well layer and the back gate layer, and a barrier layer above the quantum well layer;

(b) a plurality of spaced electrode gates formed on the multi-layer semiconductor structure, the electrode gates spaced from each other by a region beneath which quantum dots may be defined; and (c) a bias voltage supply connected to the back gate layer to apply a bias voltage thereto and a voltage source connected to apply selected voltages to one or more of the electrode gates.
3. The quantum dot device of Claim 1 or 2 whereby the multi-layer semiconductor structure is a heterostructure.
4. The quantum dot device of Claim 1 or 2 wherein the semiconductor structure includes a capping layer as a top layer and wherein the gates are formed on the capping layer.
5. The quantum dot device of Claim 4 wherein the capping layer is formed of silicon.
6. The quantum dot device of Claim 4 wherein the capping layer is formed of gallium-arsenide.
7. The quantum dot device of Claim 1 or 2 wherein there are at least two pairs of opposed gates.
8. The quantum dot device of Claim 1 or 2 wherein the substrate is formed of silicon-germanium, the back gate layer is formed of doped silicon-germanium, and the barrier layers are formed of silicon-germanium.
9. The quantum dot device of Claim 8 including a capping layer formed of silicon as the top layer formed over the barrier layer, the gates formed on the capping layer.
10. The quantum dot device of Claim 8 wherein the quantum well layer comprises two layers of semiconductor material, one layer of silicon-germanium and another layer of germanium.
11. The quantum dot device of Claim 8 wherein the quantum well layer is formed of pure silicon.
12. The quantum dot device of Claim 8 wherein the silicon-germanium barrier layers are formed with a graded silicon-germanium composition for strain relaxation.
13. The quantum dot device of Claim 12 wherein the composition of the barrier layers is graded in discrete steps.
14. The quantum dot device of Claim 8 wherein the quantum well layer has a thickness of about 6 nm, and the barrier layers have a thickness in the range of 10 to 20 nm.
15. The quantum dot device of Claim 1 or 2 wherein the substrate is formed of gallium-arsenide, the back gate is formed of doped gallium arsenide, and the barrier layers are formed of aluminum-gallium-arsenide.
16. The quantum dot device of Claim 15 including a capping layer formed of gallium arsenide as a top layer formed over the barrier layer, the gates formed on the capping layer.
17. The quantum dot device of Claim 15 wherein the quantum well layer is formed of gallium arsenide.
18. The quantum dot device of Claim 17 wherein the quantum well layer has a thickness of about 15 nm, and the barrier layers have a thickness in the range of 10 to 30 nm.
19. The quantum dot device of Claim 1 further including a bias voltage supply connected to the back gate layer to apply a bias voltage thereto and a voltage source connected to apply selected voltages to one or more of the electrode gates.
20. The quantum dot device of Claim 2 or 19 including a charge sensor coupled to a gate to detect changes in charge.
21. The quantum dot device of Claim 20 wherein the charge sensor includes an FET having a gate that is electrically connected to the gate of the quantum dot device.
22. The quantum dot device of Claim 1 or 2 wherein the electrode gates are spaced from each other a distance in the range of 10 nm to 50 nm.
23. The quantum dot device of Claim 1 or 2 wherein there are an array of quantum dots, and the electrode gates include gates that extend to positions between quantum dots and have inwardly extending portions that squeeze qubits and further including electrode gates that extend to positions spaced from each other on opposite sides of each quantum dot.
CA2438871A 2001-03-09 2002-03-08 Solid-state quantum dot devices and quantum computing using nanostructured logic gates Expired - Lifetime CA2438871C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US27485301P 2001-03-09 2001-03-09
US60/274,853 2001-03-09
PCT/US2002/007356 WO2002073527A2 (en) 2001-03-09 2002-03-08 Solid-state quantum dot devices and quantum computing using nanostructured logic dates

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CA2438871A1 true CA2438871A1 (en) 2002-09-19
CA2438871C CA2438871C (en) 2011-01-04

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US (1) US6597010B2 (en)
EP (1) EP1386283A2 (en)
JP (1) JP2004533107A (en)
AU (1) AU2002306692A1 (en)
CA (1) CA2438871C (en)
WO (1) WO2002073527A2 (en)

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Also Published As

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JP2004533107A (en) 2004-10-28
WO2002073527A2 (en) 2002-09-19
CA2438871C (en) 2011-01-04
US6597010B2 (en) 2003-07-22
AU2002306692A1 (en) 2002-09-24
EP1386283A2 (en) 2004-02-04
US20020179897A1 (en) 2002-12-05
WO2002073527A3 (en) 2003-11-27

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