CA2447204A1 - Error correction scheme for memory - Google Patents
Error correction scheme for memory Download PDFInfo
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- CA2447204A1 CA2447204A1 CA002447204A CA2447204A CA2447204A1 CA 2447204 A1 CA2447204 A1 CA 2447204A1 CA 002447204 A CA002447204 A CA 002447204A CA 2447204 A CA2447204 A CA 2447204A CA 2447204 A1 CA2447204 A1 CA 2447204A1
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- parity
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- column
- word
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M13/095—Error detection codes other than CRC and single parity bit codes
Abstract
An embedded DRAM ECC architecture for purging data errors is disclosed. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation in order to identify parity failure for the word.
Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus. A method for initializing the memory upon power up in order to prepare the memory for writing data, and methods and circuits for generating the corresponding row and column parity bits during a write operation are also disclosed.
Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus. A method for initializing the memory upon power up in order to prepare the memory for writing data, and methods and circuits for generating the corresponding row and column parity bits during a write operation are also disclosed.
Claims (54)
1. An error detection system for a memory comprising:
a memory block for storing a data word and a corresponding row parity bit; and a row parity circuit for receiving the data word and the corresponding row parity bit from the memory block in response to a memory block access operation, the row parity circuit comparing parity of the data word against the corresponding row parity bit for generating an active local parity fail flag in response to parity failure.
a memory block for storing a data word and a corresponding row parity bit; and a row parity circuit for receiving the data word and the corresponding row parity bit from the memory block in response to a memory block access operation, the row parity circuit comparing parity of the data word against the corresponding row parity bit for generating an active local parity fail flag in response to parity failure.
2. The error detection system of claim 1, further including a local data I/O
circuit for coupling the data word between the memory block and global datalines, and for coupling the corresponding row parity bit between the memory block and the row parity circuit.
circuit for coupling the data word between the memory block and global datalines, and for coupling the corresponding row parity bit between the memory block and the row parity circuit.
3. The error detection system of claim 2, wherein the row parity circuit includes a serial parity chain for receiving the data word from the local data I/O
circuit and for providing a parity output corresponding to parity of the local data, and a sense circuit for receiving the parity output and the corresponding row parity bit, for providing the active local parity fail flag if the logic state of the parity output and the logic state of the local row parity bit mismatch.
circuit and for providing a parity output corresponding to parity of the local data, and a sense circuit for receiving the parity output and the corresponding row parity bit, for providing the active local parity fail flag if the logic state of the parity output and the logic state of the local row parity bit mismatch.
4. The error detection system of claim 3, wherein the serial parity chain includes an even parity line driven to a first logic level at one end thereof, and an odd parity line driven to a second logic level at one end thereof, the parity output being provided from the other end of the even parity line, and each parity circuit includes cross-over transistors for coupling the parity output to one of the first and second logic levels.
5. The error detection system of claim 4, wherein the sense circuit includes a cross-coupled latch for receiving and latching the parity output, and a comparator circuit for comparing the latched parity output to the local row parity bit.
6. The error detection system of claim 5, wherein the sense circuit includes switching means for coupling the latched parity output to the memory block during a write operation.
7. The error detection system of claim 3, wherein the serial parity chain is segmented into at least two serially connected sub-parity circuits.
8. The error detection system of claim 1, wherein the memory block includes one of redundant rows and columns, and corresponding redundancy circuits.
9. The error detection system of claim 2, further including a parity block for storing a column parity word, each bit of the column parity word representing column parity for a corresponding bit position of the data word, a column parity circuit coupled to the local data I/O circuit and the parity block for receiving the data word and the column parity word and for comparing column parity of each bit position of the data word to a corresponding bit of the column parity word in response to the active local parity fail flag, the column parity circuit inverting data of each bit position of the data word that fails column parity.
10. The error detection system of claim 9, wherein the memory block ,the row parity circuit, the parity block and the column parity circuit are integrated in an embedded DRAM.
11. The error detection system of claim 9, wherein the parity block has a configuration identical to that of the memory block, and a parity block data I/O circuit for coupling the word of column parity bits between the parity block and the column parity circuit.
12. The error detection system of claim 10, wherein the column parity circuit includes a multiplexor circuit coupled between the local data I/O circuit and the global datelines for receiving the bits of the data word and for iteratively providing each bit of the data word to the global datelines, a parity block multiplexor circuit coupled to the parity block data I/O
circuit for receiving the bits of the column parity word and for providing one bit of the column parity word in each iteration, a parity evaluator circuit coupled to the global datelines for receiving the one bit of the column parity word, the parity evaluator circuit comparing parity of the global datelines to the one column parity bit in each iteration and generating an active global parity fail flag in response to column parity failure, and a global dateline inverting circuit for receiving and then inverting data of the global datelines in response to the active global parity fail flag.
circuit for receiving the bits of the column parity word and for providing one bit of the column parity word in each iteration, a parity evaluator circuit coupled to the global datelines for receiving the one bit of the column parity word, the parity evaluator circuit comparing parity of the global datelines to the one column parity bit in each iteration and generating an active global parity fail flag in response to column parity failure, and a global dateline inverting circuit for receiving and then inverting data of the global datelines in response to the active global parity fail flag.
13. The error detection system of claim 12, wherein the multiplexor circuit and the parity block multiplexor circuit each include a counter for controlling operation thereof.
14. The error detection system of claim 12, wherein the parity evaluator circuit includes a serial parity chain coupled to the global datelines for providing a parity output corresponding to parity of the global datelines, and a sense circuit for receiving the parity output and the one bit of the column parity word, for providing the active local parity fail flag if the logic state of the parity output and the logic state of the one bit of the column parity word mismatch.
15. The error detection system of claim 12, wherein the global dateline inverting circuit includes a flip-flop having an input coupled to one global dateline, an output coupled to a complementary global dateline of the one global dateline, a complementary output coupled to the global dateline, and a clock input for receiving the active global parity fail flag.
16. The error detection system of claim 2, further including a column parity check circuit for selectively inverting bits of the column parity word on the global datalines in a write operation for writing a new word to an address of the data word stored in the memory block, the column parity check circuit including, a parity comparison circuit for storing the data word and the new word and for comparing each bit position of the stored data word to each corresponding bit position of the stored new word, the parity comparison circuit providing a mismatch flag signal for each bit position having mismatching logic states, and a parity inverting circuit coupled to the global datalines and for receiving the mismatch flag signals, the parity inverting circuit inverting the logic state of the global datalines in response to the corresponding received mismatch flag signals.
17. The error detection system of claim 1, wherein the memory is a DRAM and the memory block access operation includes a refresh operation.
18. The error detection system of claim 1, wherein the memory is one or an SRAM
and an FeRAM, and the memory block access operation includes a data purge operation.
and an FeRAM, and the memory block access operation includes a data purge operation.
19. A method of detecting and purging bit errors in a memory, comprising:
a) executing a read operation to read a data word and corresponding row parity bit from a memory block of the memory;
b) comparing row parity of the data word against the corresponding row parity bit and generating a row parity fail flag in response to row parity failure;
c) comparing column parity of each bit of the data word against a corresponding bit of a column parity word stored in a parity block of the memory, in response to the row parity fail flag; and, d) inverting bits of the data word that fail column parity.
a) executing a read operation to read a data word and corresponding row parity bit from a memory block of the memory;
b) comparing row parity of the data word against the corresponding row parity bit and generating a row parity fail flag in response to row parity failure;
c) comparing column parity of each bit of the data word against a corresponding bit of a column parity word stored in a parity block of the memory, in response to the row parity fail flag; and, d) inverting bits of the data word that fail column parity.
20. The method of claim 19, wherein the step of executing includes suppressing the data word from global I/O circuits.
21. The method of claim 19, wherein the step of executing includes providing the data word and the corresponding row parity bit to a local databus.
22. The method of claim 21, wherein the step of comparing row parity includes executing a row parity check of the local databus against the corresponding row parity bit.
23. The method of claim 21, wherein the step of comparing column parity includes iteratively multiplexing bits of the data word from the local databus to a corresponding global dataline in response to row failure.
24. The method of claim 23, wherein the step of comparing column parity includes executing a column parity check of the global datalines against a corresponding column parity bit in each iteration.
25. The method of claim 24, wherein the step of comparing column parity includes inverting the data bits of the global datalines if column parity failure is detected in each iteration.
26. The method of claim 19, wherein the background read operation includes a refresh operation.
27. The method of claim 19, wherein the background read operation includes a data purge operation.
28. The method of claim 25, wherein the step of inverting includes inverting the data bit of a local databus line coupled to one of the global data lines for purging the bit error of the data word stored in the memory block.
29. The method of claim 23, wherein the step of iteratively multiplexing includes selectively activating column access transistors for coupling a different local databus line to the corresponding global dateline in each iteration.
30. The method of claim 29, wherein the step of selectively activating includes incrementing a counter to address and activate a different column access transistor in each iteration.
31. The method of claim 30, further including maintaining activation of the column access transistor corresponding to the memory block having row parity failure.
32. An error detection and purging system for a memory comprising:
a plurality of memory blocks for storing data words and corresponding row parity bits, one of the memory blocks being a parity block for providing a column parity word;
a local data I/O circuit coupled to each memory block for transferring the data words to global datelines;
a row parity circuit coupled to the local data I/O circuit of each memory block for receiving the data words and the corresponding row parity bits in a memory block access operation, and for comparing parity of the data words against the corresponding row parity bits for generating a corresponding active local parity fail flag in response to row parity failure; and, a column parity circuit coupled to all the local data I/O circuits, the global datelines, and the parity block for receiving the data words and the column parity word, the column parity circuit iteratively transferring a bit from each of the data words to a different global dateline for comparing parity of the global datelines to a corresponding bit of the column parity word, the column parity circuit inverting data of the global datelines in response to column parity failure in each iteration.
a plurality of memory blocks for storing data words and corresponding row parity bits, one of the memory blocks being a parity block for providing a column parity word;
a local data I/O circuit coupled to each memory block for transferring the data words to global datelines;
a row parity circuit coupled to the local data I/O circuit of each memory block for receiving the data words and the corresponding row parity bits in a memory block access operation, and for comparing parity of the data words against the corresponding row parity bits for generating a corresponding active local parity fail flag in response to row parity failure; and, a column parity circuit coupled to all the local data I/O circuits, the global datelines, and the parity block for receiving the data words and the column parity word, the column parity circuit iteratively transferring a bit from each of the data words to a different global dateline for comparing parity of the global datelines to a corresponding bit of the column parity word, the column parity circuit inverting data of the global datelines in response to column parity failure in each iteration.
33. The error detection and purging system of claim 32, wherein each row parity circuit includes a serial parity chain for receiving the data word from the local data I/O
circuit and for providing a parity output corresponding to parity of the data word, and a sense circuit for receiving the parity output and the corresponding row parity bit, for providing the active local parity fail flag if the parity output and the corresponding row parity bit mismatch.
circuit and for providing a parity output corresponding to parity of the data word, and a sense circuit for receiving the parity output and the corresponding row parity bit, for providing the active local parity fail flag if the parity output and the corresponding row parity bit mismatch.
34. The error detection and purging system of claim 33, wherein the serial parity chain includes an even parity line driven to a first logic level at one end thereof, and an odd parity line driven to a second logic level at one end thereof, the parity output being provided from the other end of the even parity line, and each parity circuit includes cross-over transistors for coupling the parity output to one of the first and second logic levels.
35. The error detection and purging system of claim 34, wherein the sense circuit includes a cross-coupled latch for receiving and latching the parity output, and a comparator circuit for comparing the latched parity output to the local row parity bit.
36. The error detection and purging system of claim 35, wherein the comparator circuit includes an exclusive OR gate.
37. The error detection and purging system of claim 32, wherein each memory block includes one of redundant rows and columns, and corresponding redundancy circuits.
38. The error detection and purging system of claim 32, wherein the parity block has a configuration identical to that of each memory block, and a parity block data I/O circuit for coupling bits of the column parity word to the column parity circuit.
39. The error detection and purging system of claim 38, wherein the column parity circuit includes a multiplexor circuit coupled between each local data I/O circuit and the global datalines for receiving the bits of the data word and for iteratively providing each bit of the data word to the global datalines, a parity block multiplexor circuit coupled to the parity block data I/O
circuit for receiving the bits of the column parity word and for providing one bit of the column parity word in each iteration, a parity evaluator circuit coupled to the global datalines and for receiving the one bit of the column parity word, the parity evaluator circuit comparing parity of the global datalines to the one column parity bit in each iteration and generating an active global parity fail flag in response to column parity failure, and a global dataline inverting circuit for receiving and inverting data of the global datalines in response to the active global parity fail flag.
circuit for receiving the bits of the column parity word and for providing one bit of the column parity word in each iteration, a parity evaluator circuit coupled to the global datalines and for receiving the one bit of the column parity word, the parity evaluator circuit comparing parity of the global datalines to the one column parity bit in each iteration and generating an active global parity fail flag in response to column parity failure, and a global dataline inverting circuit for receiving and inverting data of the global datalines in response to the active global parity fail flag.
40. The error detection system of claim 39, wherein the multiplexor circuit and the parity block multiplexor circuit each include a counter for controlling operation thereof.
41. The error detection and purging system of claim 39, wherein the global dataline inverting circuit includes a flip-flop having an input coupled to one global dataline, an output coupled to a complementary global dataline of the one global dataline, a complementary output coupled to the one global dataline, and a clock input for receiving the active global parity fail flag.
42. The error detection and purging system of claim 32, further including a column parity check circuit for selectively changing bits of the column parity word on the global datalines in a write operation, for writing a new word to an address of the data word stored in the memory block, the column parity check circuit including, a parity comparison circuit for storing the data word and the new word and comparing each bit position of the stared data word to each corresponding bit position of the stored new word, the parity comparison circuit providing a mismatch flag signal for each bit position having mismatching logic states, and a parity inverting circuit coupled to the global datalines and for receiving the mismatch flag signals, the parity inverting circuit inverting the logic state of the global datelines in response to the corresponding received mismatch flag signals.
43. A method for writing row and column parity bits to a memory system in a write operation, the memory system having a memory block for storing a data word and a corresponding row parity bit, and a parity block for storing column parity bits, the method comprising:
a. latching a stored data word read out from an address to which a new data word is to be written;
b. writing the new data word to the address and generating a corresponding row parity bit;
c. comparing data between each bit position of the stored data word and the new word; and, d. inverting the column parity bits corresponding to mis-matching bit positions.
a. latching a stored data word read out from an address to which a new data word is to be written;
b. writing the new data word to the address and generating a corresponding row parity bit;
c. comparing data between each bit position of the stored data word and the new word; and, d. inverting the column parity bits corresponding to mis-matching bit positions.
44. The method of claim 43, wherein the step of latching includes reading the stored data word onto a global databus.
45. The method of claim 43, wherein the step of writing includes latching the new data word.
46. The method of claim 43, wherein the step of inverting includes reading the column parity bits onto a global databus.
47. The method of claim 46, wherein the step of inverting includes inverting the column parity bits of the global databus that correspond to bits of the stored data word that mis-match hits of the new data word.
48. The method of claim 43, further including a memory initialization step prior to the step of latching.
49. The method of claim 48, wherein the memory initialization step includes i. writing preset logic values to memory cells of an activated wordline, ii. reading out the preset logic values for latching by bitline sense amplifiers, and iii. activating all wordlines of the memory block to write the latched preset logic values thereto.
50. The method of claim 49, wherein the step of reading includes disabling bitline;
precharge and equalize circuits after the preset logic values are latched by the bitline sense amplifiers.
precharge and equalize circuits after the preset logic values are latched by the bitline sense amplifiers.
51. The method of claim 49, wherein the step of activating includes iteratively activating individual wordlines.
52. The method of claim 51, wherein the step of iteratively activating individual wordlines includes addressing each wordline with a refresh counter.
53. The method of claim 49, wherein the step of activating includes iteratively activating multiple wordlines simultaneously.
54. The method of claim 49, wherein the step of activating includes simultaneously activating all wordlines.
The method of claim 50, wherein the activated wordline includes a master wordline and the step of writing includes activating all column access devices to write the preset logic value to all the memory cells coupled to the master wordline.
The method of claim 50, wherein the activated wordline includes a master wordline and the step of writing includes activating all column access devices to write the preset logic value to all the memory cells coupled to the master wordline.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US42955602P | 2002-11-29 | 2002-11-29 | |
| US60/429,556 | 2002-11-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2447204A1 true CA2447204A1 (en) | 2004-05-29 |
| CA2447204C CA2447204C (en) | 2010-03-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2447204A Expired - Fee Related CA2447204C (en) | 2002-11-29 | 2003-10-28 | Error correction scheme for memory |
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| Country | Link |
|---|---|
| US (2) | US7266747B2 (en) |
| CA (1) | CA2447204C (en) |
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| US20040117723A1 (en) | 2004-06-17 |
| CA2447204C (en) | 2010-03-23 |
| US20070300100A1 (en) | 2007-12-27 |
| US7266747B2 (en) | 2007-09-04 |
| US7636880B2 (en) | 2009-12-22 |
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