CA2456220A1 - Controlling processor clock rate based on thread priority - Google Patents

Controlling processor clock rate based on thread priority Download PDF

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Publication number
CA2456220A1
CA2456220A1 CA002456220A CA2456220A CA2456220A1 CA 2456220 A1 CA2456220 A1 CA 2456220A1 CA 002456220 A CA002456220 A CA 002456220A CA 2456220 A CA2456220 A CA 2456220A CA 2456220 A1 CA2456220 A1 CA 2456220A1
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Canada
Prior art keywords
clock
processor
thread
variable frequency
frequency
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002456220A
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French (fr)
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CA2456220C (en
Inventor
Kinney Bacon
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Scientific Atlanta LLC
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Individual
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Publication of CA2456220A1 publication Critical patent/CA2456220A1/en
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Publication of CA2456220C publication Critical patent/CA2456220C/en
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Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention varies the speed of processor execution, including associating a clock rate (135) with each thread in a plurality of threads (2 8a- 28n) and executing each thread in the plurality of threads on the processor (12) at the clock rate associated with the thread.

Claims (13)

1. A method for varying speed of processor execution, comprising:
associating a clock rate with each thread in a plurality of threads;
scheduling a thread to be executed from said plurality of threads;
setting the processor to execute at said clock rate associated with said thread; and executing said thread on said processor at said clock rate associated with said thread.
2. The method of claim 1, further comprising associating a priority with each thread; and determining which of said threads scheduled for execution has a highest priority.
3. The method of claim 2, wherein the step of associating a priority with each of said plurality of threads allows the same priority to be assigned to multiple threads.
4. The method of claim 2, wherein the step of scheduling a thread to be executed includes scheduling the thread with said highest priority.
5. The method of claim 2, wherein said clock rate is chosen from a set of discrete values, said priority is chosen from a set of discrete values, and each clock rate corresponds to a range of priorities,
6. The method of claim 1, further comprising executing an interrupt service routine, such that start of said interrupt service routine sets said processor to execute at a highest clock rate, and end of said interrupt service routine sets said processor to execute at a clock rate used by a thread that was interrupted by said interrupt service routine.
7. A device for varying speed of processor execution, comprising:
a variable frequency clock, wherein said variable frequency clock is capable of generating pulses of at least a highest frequency and a lowest frequency;
a processor connected to said variable frequency clock, where said processor controls the frequency of said variable frequency clock;
a memory configured to define a scheduler and a plurality of threads, where said scheduler selects a thread for execution and sets frequency of said variable frequency clock before executing said thread on said processor; and a local interface connecting said processor and said memory.
8. The device of claim 7, further comprising:
interrupt logic comprising:
a plurality of interrupt inputs; and logic configured to control said variable frequency clock such that said variable frequency clock outputs a clock signal at said highest clock frequency when any one of said plurality of interrupt inputs is asserted.
9. The device of claim 7, wherein said local interface uses said variable frequency clock to provide clocking signal to said memory.
10. The device of claim 7, wherein said variable frequency clock comprises:
a clock generator capable of generating pulses of at least a highest frequency and a lowest frequency;
a divider connected to said clock generator; and a multiplexer connected to said divider, where the output of said multiplexer provides the clock input to said processor, and said processor selects the output of said multiplexer.
11. A processor-based system comprising:
a variable frequency clock, wherein said variable frequency clock is capable of generating pulses of at least a highest frequency and a lowest frequency;
a processor connected to said variable frequency clock, where said processor controls the frequency of said variable frequency clock;
a memory configured to define a scheduler and a plurality of threads, where said scheduler selects a thread for execution and sets frequency of said variable frequency clock before executing said thread on said processor; and a local interface connecting said processor and said memory.
12. The system of claim 11, wherein the system is a set-top terminal for cable television.
13. The system of claim 11, wherein the system is a conditional access module used in conjunction with a set-top terminal for cable television.
CA002456220A 2001-08-02 2002-07-25 Controlling processor clock rate based on thread priority Expired - Fee Related CA2456220C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/920,692 2001-08-02
US09/920,692 US6622253B2 (en) 2001-08-02 2001-08-02 Controlling processor clock rate based on thread priority
PCT/US2002/023658 WO2003012610A1 (en) 2001-08-02 2002-07-25 Controlling processor clock rate based on thread priority

Publications (2)

Publication Number Publication Date
CA2456220A1 true CA2456220A1 (en) 2003-02-13
CA2456220C CA2456220C (en) 2009-12-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA002456220A Expired - Fee Related CA2456220C (en) 2001-08-02 2002-07-25 Controlling processor clock rate based on thread priority

Country Status (5)

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US (1) US6622253B2 (en)
EP (1) EP1421462A4 (en)
CA (1) CA2456220C (en)
DE (1) DE02752579T1 (en)
WO (1) WO2003012610A1 (en)

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Also Published As

Publication number Publication date
CA2456220C (en) 2009-12-22
EP1421462A1 (en) 2004-05-26
US6622253B2 (en) 2003-09-16
US20030028816A1 (en) 2003-02-06
DE02752579T1 (en) 2004-10-21
WO2003012610A1 (en) 2003-02-13
EP1421462A4 (en) 2007-04-04

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