CA2460299C - Amplitude and phase modulation using dual digital delay vectors - Google Patents

Amplitude and phase modulation using dual digital delay vectors Download PDF

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Publication number
CA2460299C
CA2460299C CA002460299A CA2460299A CA2460299C CA 2460299 C CA2460299 C CA 2460299C CA 002460299 A CA002460299 A CA 002460299A CA 2460299 A CA2460299 A CA 2460299A CA 2460299 C CA2460299 C CA 2460299C
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Prior art keywords
delay
vector
digital
phase
amplitude
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CA002460299A
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French (fr)
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CA2460299A1 (en
Inventor
Gerald Harron
Surinder Kumar
Jason T. Tucker
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Vecima Networks Inc
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Vecima Networks Inc
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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03CMODULATION
    • H03C5/00Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K7/00Modulating pulses with a continuously-variable modulating signal
    • H03K7/10Combined modulation, e.g. rate modulation and amplitude modulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/32Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/36Modulator circuits; Transmitter circuits
    • H04L27/365Modulation using digital generation of the modulated carrier (not including modulation of a digitally generated carrier)

Abstract

The present invention provides a means to implement amplitude and phase modulation digitally and directly at an RF frequency that benefits from high output power using non-linear amplifiers. This is accomplished by the combination of two constant amplitude phase varying vectors. A reference oscillator produces a carrier signal, which is supplied to two digital delay lines composed of a sequence of delay banks. The delay lines are controlled by lookup tables that are updated by the vector control circuit used to determine the delay of each digital delay line. The delay of the lines are set in such a way as to produce two vectors with the desired phase shift that, when summed together, produce a vector with the desired phase and amplitude characteristics.

Description

AMPLITUDE AND PHASE MODULATION USING DUAL DIGITAL DELAY
VECTORS

This application is related to Application Serial No. 2,460,298 filed simultaneously with this application by the same inventors and entitled "Modulation using Discrete Amplitude Adjustment and Dual Digital Delay Lines".

FIELD OF THE INVENTION

This invention relates generally to teler,ommunication systems. The present invention relates specifically to data transmission using analog signals, more specifically, to a unique method for providing amplitude and phase modulation of a signal using dual digital delay lines.

BACKGROUND OF THE INVENTION

The following references may be relevant to the present invention:
5,329,259 - Stengel, "Efficient Amplitude/Phase Modulation Amplifier"
5,612,651 - Chethik, "Modulating Array QAM Transmitter"

5,659,272 - Linguet, "Ampiitude Modulation Method and Apparatus using Two Phase Modulated Signals"

5,852,389 - Kumar, "Direot QAM Modulator"

5,867,071 - Chethik, "High Power Transmitter Employing a high Power QAM Modulator"

6,147,553 - Kolanek, "Amplification Using Amplitude Reconstruction of Ampiitude and/or Angle Moduiated Carrier"

6,160,856 - Gershon, "System For Providing Amplitude and Phase Modutation of Line Signals Using Delay Lines"
2 6,313,703 - Wright et al., "Use of Antiphase Signals For Predistortion Training Within An Amplifier System 6,366,177 - McCune, "High-Efficiency Power Modulators"

With the ever increasing demand for the high speed transfer of information digital systems are becoming very common. In its simplest form the modem telecommunication system requires circuits for modulation, frequency conversion, transmission and detection.

The basis for signal transmission is a continuous time varying constant-frequency signal known as a carrier. The carrier signal can be represented as S(t) = A cos (2nft + a), where f is the frequency, A is the amplitude, and v is the phase of the signal. 8(t) is a deterministic signal, and alone carries no useful information. However, information could be encoded on S(t) if one or more of the fbilowing characteristics of the carrier were altered: amplitude, frequency or phase.
In essence modulation is the process of encoding an information source onto a high-frequency, carrfer signal S(t).

Bandpass digital systems can be divided into two main categories;
binary digital systems or multilevel digital systems. Binary digitai systems are limited in that they can only represent a one bit symbol (0 or 1) at any given time.
The most common binary bandpass signal techniques are Amplitude Shift Keying (ASK), Phase Shift Keying (PSK), and Frequency Shift Keying (FSK). For example, a binary digital system using ASK might have a signal range from 0 to 3 Volts.
Any value less than 1.5 Vofts would represent a digital 0 and anything greater than 1.5 Volts would represent a digital 1, Alternatively, FSK would use two different
3 frequencies and PSK would use two different phases to represent a digital 0 or 1.
However, binary digital systems are not as practical as multilevel systems since digital transmission is notoriously wasteful of RF bandwidth, and regulatory authorities usually require a minimum bandwidth efficiency.

With multilevel digital systems, inputs with more than two modulation levels are used. In cases like this multiple bits can be sent with each symbol, increasing the speed and efficiency. In keeping with the previous example of an ampiitude modulated signal with a range from 0 to 3 Volts, the signal amplitude could be broken into 4 distinct points; 0.75V could correspond to binary 00, 1.5V

corresponds to 01, 2.25V corresponds to 10, and 3V corresponds to binary 11.
In this case each symbol represents a two bit binary number. Altematively, such transformations can be implemented by adjusting the phase or frequency of the carrier.

More advanced techniques for a multilevel digital system would include a combination of amplitude and phase modulation of a carrier signal. In this case a single multi-b+t symbol could be represented by a signal with a certain phase and amplitude. Each symbol of digital data could be defined as a vector with a specified amplitude and angle and visualized on a polar axis. In one of its simplest fomm a three bit digital symbol could be represented by two distinct ampiitudes and four distinct phases.

There are various common modulation techniques which require the amplitude and phase adjustment of a carrier signal. Solutions to these modulation teohniques are typically buitt in ei#her analog or digital circuitry. One such solution
4 which is shown and described hereinafter will be recognized by those skilled in the art as a 10 modulator, Due to its requirements for digital to analog conversion and linear power amplification before transmission, modulators of this form typically consume lots of power.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an apparatus for ampiitude and phase modulation of a signal.

According to the invention there is provided an apparatus for amplitude and phase modulation of a signal comprising:

a reference pulse oscillator arranged to provide a signal in the form of a series of input pulses;

an input for input modulating data including desired amplitude and phase modulation;

a vector logic circuit responsive to the input modulating data;

two digital delay lines each coupled to said reference oscillator and each having multiple delay cells for selectively delaying respective pulses of said signal;

two lookup tables each of which contains information for controlling the delay cells of a respective one of the delay lines so as to control an overall delay of the respective one of the digital delay lines so as to generate therefrom a component vector which is dependent upon the input modulating data;

and a summer that is coupled to the two digital delay lines and arranged to combine together the component vectors from both of the delay lines to provide an output vector.

Preferably said vector logic circuit utilizes the desired ampiitude and phase modulation to determine the phase of the two fixed magn'rkude component vectors.
5 Preferably said component vectors are assumed to have the same magnitude and be equidistant, radially, from the resultant vector.

Preferably the formula :tCos'[r/(21)] govems the phase offfset of the component vectors from the desired output phase, where, in the goveming formula, r represents the desired output magnitude and V is the magnitude of the component vectors.

Preferably said vector logic circuit compensates for the special cases where the phase of the leading or trailing vectors cross the 3600 barrier, where compensation is accomplished by either adding or subtracting 2n from the absolute phase of the vector.

Preferably said vector logic circuit converts the phase information into an equivalent delay.

Preferably said vector logic circuit updates lookup tables with the information required to reproduce the required delay.

Preferably said delay lines contain a finite number of sequential or parallel delay cells capabte of covering 360 of phase.

Preferably said delay cells have equivalent or weighted delay periods.
Preferably said delay lines contain a finite number of additional delay cells for the purpose of compensation in the range of the finest resolution step.
6 Preferably said delay cells contain a feedback edge detedor whereupon detection of a falling edge enables the delay cell to confirm its next status from a lookup table.

Preferably said lookup tables contain the information required to reproduce a specified delay.

Preferably said tables are directly referenced by the digital delay lines in order to control which delay cells are enabled at a given time, Preferably said tables contain redundant registers which contain both delay and compensation infvrmation.

Preferably said summer is coupled to the two digital delay lines for the purpose of combining two constant amplitude component vectors into a resultant vector containing a desired ampiitude and phase.

Preferably said reference puises are a high power pulse train.

The invention may provide one or more of the foiiowing advantages:

Digitai data is converted into an analog signal without the use of digital to analog converters.

Digital data is converted into an analog signal which requires minimal amplification before transmission.

Digitai data is converted into an analog signal which uses non-linear amplifiers.

ft removes all digital to analog converters (DACs) from the modulation process.

It also provides a novel method for ampiitude and phase modulation
7 which does not require linear amplification.

Removal of the DACs and linear amplifier, results in a significant power reduction compared to conventional techniques.

The previously stated advantages are achieved, in part, by providing an ampiitude and phase modulated system that produces two high power constant amplitude phase modulated vectors that, when summed together, will produce the desired ampiitude and phase-modulated signal. In order to facilitate this action, an input reference pulse is fed into two digital delay lines (DDL) containing a specified number (N) of delay blocks. Unlike typical IQ modulator techniques, the reference signal, that is fed to the DDLs, does not have to be scaled back to maintain linearity.
Each delay line is controlled by a lookup table, which contains the required delay to shift the input reference pulse to the desired phase. The phases of the two vectors ane chosen by the vector logic block. The vector logic block updates the lookup tables for each delay line, thus establishing the phase of each vector. The phases of the vectors are chosen in such a way that when summed together they produce a resufting vector that contains both the desired phase and amplitude modulation.
Although the invention has general application in the field of signal modulation, the most direct use of the method described in the invention is the realization of a transmitter that converts digital data into an amplitude and phase modulated signal to be transmitted over a communications line. In this case, the vector produced by the invention represents a binary symbol. The number of bits in the symbol are determined by the encoding technique implemented.
8 BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic block diagram of a prior art of IQ modulator.
Figure 2 is a schematic block diagram of one embodiment of an apparatus according to the present invention, Figure 3 is a graphical representation of the vector math for the embodiment of Figure 2.

Figure 4 is a block diagram of the lookup table for the embodiment of Figure 2.

DETAILED DESCRIPTION

The present invention synthesizes a vector with the desired amplitude and phase using two fixed magnitude vectors that have dynamically controlled phases. Figure 2 illustrates a block diagram of an embodiment of the Invention. The apparatus consists of five major blocks; input pulses 200, a vector logic circuit 201, two digital delay lines 202a and 202b, two lookup tables 203a and 203b, and a signal combiner 204.

The vector logic circuit 201 is supplied with digital data corresponding to the desired magnitude and phase of the output vector. Once the data has been received the logic circuit determines the phase of the two vectors needed to generate the desired output vector. The vector logic circuit 201 determines the phase of each vector by using the following assumptions:

Both vectors will have the same magnitude.

Each vector will be equidistant, radially, from the resultant vector.

Having defined the vectors in the above manner the veotor logic circuit
9 201 can determine the phase of each vector. if the desired output vector 300 (Figure 3) has a magnitude r and phase 9 the required angle of rotation away from e would be equal to (D - Cos''[r/(2V)], where V is the magnitude of the each vector 301. The absolute phase of the leading vector would be 0+(1), while the absolute phase of the trailing vector would be 9-(D. Special consideration must be taken when the leading or trailing vector crosses over the 2n or 3600 barrier. In such cases 2n is either added to, or subtracted from, the absolute phase of the vector depending upon whether it is the leading or trailing vector that has crossed the bound. Figure 3 shows a graphical example of the vector math.

Once the phase of both vectors required to reproduce the desired output magnitude and phase is determined, the vector logic circuit 201 converts the phase to a required delay time and updates the lookup tables 203a and 203b.
Each table is used to select the delay cells required by the delay lines 202 to synthesize the desired phase. The tables must be updated no less than twice the speed of the symbol rate. Lookup table 203a contains the delay information for the vector A, while 203b contains the information for vector B. The preferred implementation of the invention would also include redundant blocks in each table to allow for compensation of the digital delay lines 202. The compensation could take on a form shown in Figure 4, wherein a N bit binary number controls 2N registers containing both the delay and compensation information. The compensation would ensure that both digital delay lines 202 would have equivalent phase coverage over 360 .

In order to produce the necessary vectors, the digital delay lines 202 require a reference signal. As amplitude compression is not an issue, the reference can be a high power signal. This high power pulse train 200, at the carrier frequency, is supplied to both delay lines. The digital delay lines 202 consist of a finite number (N) of sequential fixed delay cells. The delay of each cell may be 5 equivalent or weighted. Even though the preferred actualization of the invention is to utilize fixed equivalent sequential ceiis, it could also be implemented using (N) weighted parallel delay cells. The number and weight of the delay cells determine the resolution of the synthesized phase. N should be chosen to realize 360 coverage with the desired resolution, The preferred realization of the invention
10 would also include a finite number of extra delay cells which can be used for compensation for the time resolution steps.

An example of the delay cell implementation is to use an inverter and an edge feedback detector which delays the input pulse by a known amount Delta T.
A delayed signal from an output of each delay cell is supplied to the input of the next delay cell, The delay of the digital delay lines 202 is set in such a way as to produce the desired phase for the vector. This is accomplished by enabling or disabling specified delay cells in the delay line. The status of each delay cell is set by the lookup tables 203. As the delay cell encounters a falling edge it confirms its status with the table and has half a pulse cycle to update its status if required.

The pulses exiting 202a will have the phase that the vector logic circuit 201 deemed necessary for vector A, while the pulses exifing 202b have the phase deemed necessary for vector B. The pulses then enter the summer 204, which combines both vectors 302. The resuldng vector has the phase and amplitude
11 corresponding to the desired modulation.

Since various modifications can be made in my Invention as herein above described, and many apparently widely different embodiments of same made within the spirit and scope of the claims without department from such spirit and scope, f# is intended that all matter contained in the accompanying specification shall be interpreted as iilustrative only and not in a limiting sense.

Claims (18)

CLAIMS:
1. An apparatus for amplitude and phase modulation of a signal comprising:

a reference pulse oscillator arranged to provide a signal defined by a series of input pulses;

an input connection for input modulating data including desired amplitude and phase modulation;

a vector logic circuit responsive to the input modulating data;

two digital delay lines each coupled to said reference oscillator and each having multiple delay cells for selectively delaying respective pulses of said signal;

two lookup tables each of which contains information for controlling the delay cells of a respective one of the delay lines so that the vector logic circuit controls an overall delay of the respective one of the digital delay lines using the information so as to generate therefrom a component vector which is dependent upon the input modulating data;

and a summer that is coupled to the two digital delay lines and arranged to combine together the component vectors from both of the delay lines to provide a resultant vector.
2. The apparatus according to Claim 1 wherein said vector logic circuit is arranged to utilize desired amplitude and phase modulation to determine the two component vectors' phase.
3. The apparatus according to Claim 2 wherein the vector logic circuit is arranged such ~Cos-1[r/(2V)] governs the component vectors' phase offset from a desired output phase, where r represents a desired output magnitude and V
is the component vectors' magnitude.
4. The apparatus according to Claim 2 or 3 wherein the vector logic circuit is arranged such that said component vectors have magnitudes which are equal and are equidistant, radially, from the resultant vector.
5. The apparatus according to any one of Claims 1 to 4 wherein said vector logic circuit is arranged to compensate for special cases where leading or trailing vectors have a phase which crosses 360°, where compensation is accomplished by either adding or subtracting 2.pi. from the vector's absolute phase.
6. The apparatus according to any one of Claims 1 to 5 wherein said vector logic circuit is arranged to convert phase modulation into an equivalent required delay.
7. The apparatus according to Claim 6 wherein said vector logic circuit is arranged to update the lookup tables with information required to reproduce the required delay.
8. The apparatus according to any one of Claims 1 to 7 wherein said delay lines contain a number of sequential or parallel delay cells capable in combination of covering 360° of phase.
9. The apparatus according to Claim 8 wherein said delay cells have equivalent or weighted delay periods.
10. The apparatus according to any one of Claims 1 to 9 wherein said delay cells contain a feedback edge detector whereupon detection of a falling edge enables the delay cell to confirm its next status from a lookup table.
11. The apparatus according to any one of Claims 1 to 10 wherein said lookup tables contain the information required to reproduce a specified delay.
12. The apparatus according to any one of Claims 1 to 11 wherein said lookup tables are directly referenced by the digital delay lines in order to control which delay cells are enabled at a given time.
13. The apparatus according to any one of Claims 1 to 12 wherein said lookup tables contain redundant registers which contain both delay and compensation information.
14. The apparatus according to any one of Claims 1 to 13 wherein said digital delay lines generate component vectors of constant amplitude and wherein the summer is coupled to the two digital delay lines for combining the two constant amplitude component vectors into a resultant vector containing a desired amplitude and phase.
15. The apparatus according to any one of Claims 1 to 14 wherein said input pulses form a high power pulse train.
16. The apparatus according to any one of Claims 1 to 15 in which said input modulating data is digital and is converted into the resultant vector which is an analog signal, without digital to analog converters,
17. The apparatus according to any one of Claims 1 to 16 in which said input modulating data is digital such that digital data is converted into the resultant vector which is an analog signal, and wherein the resultant vector is transmitted with minimal amplification.
18. The apparatus according to any one of Claims 1 to 17 in which said input modulating data is digital such that digital data is converted into the resultant vector which is an analog signal, and wherein the resultant vector is amplified utilizing non-linear amplifiers.
CA002460299A 2003-11-28 2004-03-09 Amplitude and phase modulation using dual digital delay vectors Expired - Lifetime CA2460299C (en)

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US52511703P 2003-11-28 2003-11-28
US60/525,117 2003-11-28

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8018276B2 (en) * 2006-09-28 2011-09-13 Motorola Mobility, Inc. Signal processing method and power amplifier device
US7755443B2 (en) * 2008-02-15 2010-07-13 Panasonic Corporation Delay-based modulation of RF communications signals
US9382843B2 (en) 2012-10-08 2016-07-05 General Electric Company Flow balancing ventilation system and method of balancing a flow

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2690794B1 (en) 1991-06-07 1995-06-16 Thomson Csf METHOD AND DEVICE FOR AMPLITUDE MODULATION OF A SIGNAL.
US5329259A (en) 1993-02-11 1994-07-12 Motorola, Inc. Efficient amplitude/phase modulation amplifier
US5612651A (en) 1996-01-02 1997-03-18 Loral Aerospace Corp. Modulating array QAM transmitter
CA2202458C (en) 1997-04-11 2001-02-06 Surinder Kumar Direct qam modulator
US5867071A (en) 1997-08-15 1999-02-02 Lockheed Martin Aerospace Corp. High power transmitter employing a high power QAM modulator
US6160856A (en) 1997-12-18 2000-12-12 Advanced Micro Devices, Inc. System for providing amplitude and phase modulation of line signals using delay lines
US5886573A (en) 1998-03-06 1999-03-23 Fujant, Inc. Amplification using amplitude reconstruction of amplitude and/or angle modulated carrier
US6054896A (en) 1998-12-17 2000-04-25 Datum Telegraphic Inc. Controller and associated methods for a linc linear power amplifier
DE10000958B4 (en) * 2000-01-12 2004-04-29 Infineon Technologies Ag Circuit arrangement for generating a quadrature amplitude modulated transmission signal
US6366177B1 (en) 2000-02-02 2002-04-02 Tropian Inc. High-efficiency power modulators
FR2809266B1 (en) * 2000-05-19 2002-10-11 St Microelectronics Sa METHOD AND DEVICE FOR CONTROLLING THE PHASE BETWEEN FOUR MUTUALLY PHASE QUADRATURE SIGNALS

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US6982607B2 (en) 2006-01-03
CA2460299A1 (en) 2005-05-28
US20050116786A1 (en) 2005-06-02

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