CA2481260A1 - Method and device for conditioning semiconductor wafers and/or hybrids - Google Patents
Method and device for conditioning semiconductor wafers and/or hybrids Download PDFInfo
- Publication number
- CA2481260A1 CA2481260A1 CA002481260A CA2481260A CA2481260A1 CA 2481260 A1 CA2481260 A1 CA 2481260A1 CA 002481260 A CA002481260 A CA 002481260A CA 2481260 A CA2481260 A CA 2481260A CA 2481260 A1 CA2481260 A1 CA 2481260A1
- Authority
- CA
- Canada
- Prior art keywords
- space
- wafer
- fluid
- line
- hybrid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Abstract
The invention relates to a method for conditioning semiconductor wafers and/ or hybrids, comprising the following steps: an at least partly closed space (1) containing a wafer/hybrid-receiving unit (10) is provided for receiving a semiconductor wafer and/or hybrid; and a dry fluid is directed through the wafer/hybrid-receiving unit (10) in order to temper the wafer/hybrid-receivi ng unit (10), at least part of the fluid leaving the wafer/hybrid-receiving uni t (10) being used for conditioning the atmosphere inside the space (1). Also disclosed is a corresponding device for conditioning semiconductor wafers and/or hybrids.
Claims (20)
1. Method for conditioning semiconductor wafers and/or hybrids having the steps:
preparation of a space (1) which is at least partially enclosed and has a wafer/hybrid holding device (10) which is located therein and has the purpose of holding a semiconductor wafer and/or hybrid; and conduction of a dry fluid through the wafer/hybrid holding device (10) in order to heat-treat the wafer/hybrid holding device (10);
wherein at least a portion of the fluid leaving the wafer/hybrid holding device (10) is used to condition the atmosphere within the space (1).
preparation of a space (1) which is at least partially enclosed and has a wafer/hybrid holding device (10) which is located therein and has the purpose of holding a semiconductor wafer and/or hybrid; and conduction of a dry fluid through the wafer/hybrid holding device (10) in order to heat-treat the wafer/hybrid holding device (10);
wherein at least a portion of the fluid leaving the wafer/hybrid holding device (10) is used to condition the atmosphere within the space (1).
2. Method according to Claim 1, characterized in that the space (1) is essentially enclosed by a container (5).
3. Method according to Claim 1 or 2, characterized in that the portion is firstly heat-treated and then allowed to flow out within the space (1).
4. Method according to Claim 1, 2 or 3, characterized in that the portion is heat-treated outside the space (1) and then fed back to the space (1).
5. Method according to Claim 1, characterized in that the portion is allowed to flow out within the space (1) directly after it leaves the wafer/hybrid holding device (10).
6. Method according to Claim 1, characterized in that a first portion of the fluid leaving the sample stage (10) is firstly heat-treated and then allowed to flow out within the space (1), and a second portion is allowed to flow out within the space (1) directly after it leaves the wafer/hybrid holding device (10).
7. Method according to Claim 1, characterized in that at least one of the first and second portions can be regulated as a function of the flow rate.
8. Method according to Claim 3. characterized in that the portion is heat-treated in that it is used for precooling, in particular for precooling the fluid, outside the space (1) before said portion is allowed to flow out within the space (1).
9. Device for conditioning semiconductor wafers and/or hybrids having:
an at least partially enclosed space (1) having a wafer/hybrid holding device (10) which is located therein and has the purpose of holding a semiconductor wafer and/or hybrid; and a line device (r2, r3, r4, r5, i3, i4) for conducting a dry fluid through the wafer/hybrid holding device (10) for heat-treating the wafer/hybrid holding device (10) and for conducting at least a portion of the fluid leaving the wafer/hybrid holding device (10) into the space (1) for conditioning the atmosphere in the space (1).
an at least partially enclosed space (1) having a wafer/hybrid holding device (10) which is located therein and has the purpose of holding a semiconductor wafer and/or hybrid; and a line device (r2, r3, r4, r5, i3, i4) for conducting a dry fluid through the wafer/hybrid holding device (10) for heat-treating the wafer/hybrid holding device (10) and for conducting at least a portion of the fluid leaving the wafer/hybrid holding device (10) into the space (1) for conditioning the atmosphere in the space (1).
10. Device according to Claim 9, characterized in that the line device (r2, r3, r4, r5, i3, i4) has:
a first line (r2) via which the fluid can be conducted into the wafer/hybrid holding device (10) from outside the space (1);
a second line (r3) via which the fluid can be conducted from the wafer/hybrid holding device (10) to outside the space (1); and a third line (r4) via which the fluid can be fed back from outside the space (1) into the space (1);
wherein a temperature regulating device (70; 70, 80'') is provided between the second and third lines (r3, r4).
a first line (r2) via which the fluid can be conducted into the wafer/hybrid holding device (10) from outside the space (1);
a second line (r3) via which the fluid can be conducted from the wafer/hybrid holding device (10) to outside the space (1); and a third line (r4) via which the fluid can be fed back from outside the space (1) into the space (1);
wherein a temperature regulating device (70; 70, 80'') is provided between the second and third lines (r3, r4).
11. Device according to Claim 10, characterized in that outflow elements (40) are provided at the end of the third line (r4).
12. Device according to Claim 9, characterized in that the line device (r2, r3, r4, r5, i3, i4) has:
a first line (r2) via which the fluid can be conducted from outside the space (1) into the wafer/hybrid holding device (10); and a fourth line (r5) via which the fluid can be conducted from the wafer/hybrid holding device (10) into the space (1).
a first line (r2) via which the fluid can be conducted from outside the space (1) into the wafer/hybrid holding device (10); and a fourth line (r5) via which the fluid can be conducted from the wafer/hybrid holding device (10) into the space (1).
13. Device according to Claim 12, characterized in that the line device (r2, r3, r4, r5, i3, i4) has:
a second line (r3) via which the fluid can be conducted out of the wafer/hybrid holding device (10) to outside the space (1); and a third line (r4) via which the fluid can be fed back into the space (1) from outside the space (1);
wherein a temperature regulating device (70; 70, 80'') is provided between the second and third lines (r3, r4).
a second line (r3) via which the fluid can be conducted out of the wafer/hybrid holding device (10) to outside the space (1); and a third line (r4) via which the fluid can be fed back into the space (1) from outside the space (1);
wherein a temperature regulating device (70; 70, 80'') is provided between the second and third lines (r3, r4).
14. Device according to one of Claims 12 or 13, characterized in that a valve (45) is provided for regulating the flow rate of the fourth line (r5).
15. Device according to one of Claims 10 to 14, characterized in that the temperature regulating device (70; 70, 80'') has a heating device (105).
16. Device according to one of Claims 10 to 15, characterized in that the temperature regulating device (70; 70, 80'') has a heat exchanger (95) to which at least a portion of the fluid leaving the space (1) can be conducted.
17. Device according to Claim 16, characterized in that the heat exchanger (95) is used to precool the fed-in fluid.
18. Device according to Claim 13, characterized in that the line device (r2, r3, r4, r5, i3, i4) is designed in such a way that the portion leaving the heat exchanger (95) can be fed back at least partially into the space in order to condition the atmosphere.
19. Device according to one of Claims 9 to 18, characterized in that a further line (r1) is provided via which dry fluid can additionally be conducted directly into the space (1) from outside the space (1).
20. Device according to one of Claims 9 to 19, characterized in that the space (1) is essentially enclosed by a container (5).
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10216786.9 | 2002-04-15 | ||
DE10216786A DE10216786C5 (en) | 2002-04-15 | 2002-04-15 | Method and apparatus for conditioning semiconductor wafers and / or hybrids |
PCT/EP2003/003937 WO2003088323A1 (en) | 2002-04-15 | 2003-04-15 | Method and device for conditioning semiconductor wafers and/or hybrids |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2481260A1 true CA2481260A1 (en) | 2003-10-23 |
CA2481260C CA2481260C (en) | 2010-10-12 |
Family
ID=28798441
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA2481260A Expired - Fee Related CA2481260C (en) | 2002-04-15 | 2003-04-15 | Method and device for conditioning semiconductor wafers and/or hybrids |
Country Status (16)
Country | Link |
---|---|
US (1) | US7900373B2 (en) |
EP (1) | EP1495486B3 (en) |
JP (1) | JP4070724B2 (en) |
KR (1) | KR100625631B1 (en) |
CN (1) | CN100378903C (en) |
AT (1) | ATE341831T1 (en) |
AU (1) | AU2003224079A1 (en) |
CA (1) | CA2481260C (en) |
DE (2) | DE10216786C5 (en) |
DK (1) | DK1495486T5 (en) |
ES (1) | ES2274225T7 (en) |
NO (1) | NO336896B1 (en) |
PL (1) | PL211045B1 (en) |
PT (1) | PT1495486E (en) |
RU (1) | RU2284609C2 (en) |
WO (1) | WO2003088323A1 (en) |
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RU2284609C2 (en) | 2006-09-27 |
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CN100378903C (en) | 2008-04-02 |
DE10216786C5 (en) | 2009-10-15 |
US20050227503A1 (en) | 2005-10-13 |
CA2481260C (en) | 2010-10-12 |
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