CA2505165A1 - Reconfiguration of the programmable logic of an integrated circuit - Google Patents

Reconfiguration of the programmable logic of an integrated circuit Download PDF

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Publication number
CA2505165A1
CA2505165A1 CA002505165A CA2505165A CA2505165A1 CA 2505165 A1 CA2505165 A1 CA 2505165A1 CA 002505165 A CA002505165 A CA 002505165A CA 2505165 A CA2505165 A CA 2505165A CA 2505165 A1 CA2505165 A1 CA 2505165A1
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CA
Canada
Prior art keywords
memory
programmable logic
processor
configuration
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002505165A
Other languages
French (fr)
Other versions
CA2505165C (en
Inventor
Derek R. Curd
Punit S. Kalra
Richard J. Leblanc
Vincent P. Eck
Stephen W. Trynosky
Jeffrey V. Lindholm
Trevor J. Bauer
Brandon J. Blodget
Scott P. Mcmillan
Philip B. James-Roxby
Prasanna Sundararajan
Eric R. Keller
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Xilinx Inc
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Individual
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Filing date
Publication date
Priority claimed from US10/319,051 external-priority patent/US6907595B2/en
Application filed by Individual filed Critical Individual
Publication of CA2505165A1 publication Critical patent/CA2505165A1/en
Application granted granted Critical
Publication of CA2505165C publication Critical patent/CA2505165C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17752—Structural details of configuration resources for hot reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17732—Macroblocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17756—Structural details of configuration resources for partial configuration or partial reconfiguration

Abstract

A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information;
and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.

Claims (20)

1. A method for reconfiguring an integrated circuit, comprising a plurality of programmable logic modules, a processor, a memory array having configuration information for the plurality of programmable logic modules, and a memory module, the method comprising:
reading a section of the configuration information from the memory array;
storing the section in the memory module;
the processor modifying at least some of the section; and writing the modified section of the configuration information to the memory array.
2. The method of claim 1 wherein the processor comprises at least one of the plurality of programmable logic modules that is not being reconfigured.
3. The method of claim 1 wherein the processor comprises a hardware microprocessor.
4. The method of claim 1 wherein the programmable logic module comprises a configurable logic block (CLB).
5. The method of claim 1 wherein the integrated circuit comprises a field programmable gate array having a processor.
6. A programmable logic device comprising:
a configuration memory array having a plurality of frames, wherein the configuration memory array stores configuration data values for controlling the configuration of the programmable logic device;
a processor configured to implement a partial reconfiguration of the programmable logic device by reading a frame from the configuration memory array, modifying only a select subset of the frame, thereby creating a modified frame, and writing the modified frame back to the configuration memory array.
7. The programmable logic device of Claim 6, further comprising an internal configuration access port (ICAP) coupled between the processor and the configuration memory array, wherein the ICAP retrieves the frame from the configuration memory array under control of the processor.
8. The programmable logic device of Claim 7, further comprising a first memory coupled to the processor and the ICAP, wherein the first memory stores the frame and modified frame.
9. The programmable logic device of Claim 8, further comprising a direct memory access (DMA) engine coupled between the first memory and the ICAP.
10. The programmable logic device of Claim 9, further comprising a register coupled to the DMA engine and the processor, wherein the processor controls the DMA engine via the register.
11. The programmable logic device of Claim 7, further comprising:
a processor local bus coupled to the processor; and control logic coupled between the processor local bus and the ICAP.
12. The programmable logic device of Claim 11, further comprising a memory block coupled to the processor local bus, wherein the memory block stores the frame and modified frame.
13. The programmable logic device of Claim 12, further comprising a communications interface coupled to the processor local bus, wherein the communications interface provides an interface for an internal or external stimulus.
14. An integrated circuit having programmable logic components, further comprising:
a first memory storing configuration information for the programmable logic components;
an access port having access to the first memory;
a processor connected by a first bus to a second memory; and a control module connected to the access port and the first bus, the control module receiving control information from the processor via the first bus, the control information configuring the control module to transfer part of the configuration information to the second memory from the first memory via the access port.
15. The integrated circuit of claim 14 further comprising a second bus directly connecting the control module to the second memory, and wherein the transfer of part of the configuration information to the second memory is further via the second bus.
16. The integrated circuit of claim 14 wherein the first memory comprises a configuration memory array and the second memory comprises a block random accessmemory (BRAM).
17. The integrated circuit of claim 14 wherein the access port comprises a internal configuration access port (ICAP), and wherein the control module comprises a register, the register having memory elements mapping to control and data signals of the ICAP.
18. The integrated circuit of claim 14 wherein the control module comprises:
an address module configured to determine one or more addresses in the second memory for storing part of the configuration information from the first memory;
a first register indicating a read from or write to the access port of the part of the configuration information; and a second register for indicating when the transfer of part of the configuration information is complete.
19. The integrated circuit of claim 14 wherein the control module comprises:
an address module coupled to the processor and configured to determine one or more addresses in the second memory for storing part of the configuration information from the first memory; and a packet register coupled to the processor and comprising a data packet having a number of bytes to be read.
20. A programmable logic device comprising:
a configuration memory array configured to store frames of configuration data values that define the configuration of the programmable logic device;
means for reading a first frame from the configuration memory array;
means for modifying a subset of the configuration data values in the first frame, thereby creating a first modified frame; and means for overwriting the first frame of the configuration memory array with the first modified frame, thereby partially reconfiguring the programmable logic device.
CA2505165A 2002-12-13 2003-12-12 Reconfiguration of the programmable logic of an integrated circuit Expired - Lifetime CA2505165C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10/319,051 2002-12-13
US10/319,051 US6907595B2 (en) 2002-12-13 2002-12-13 Partial reconfiguration of a programmable logic device using an on-chip processor
US10/377,857 2003-02-28
US10/377,857 US6920627B2 (en) 2002-12-13 2003-02-28 Reconfiguration of a programmable logic device using internal control
PCT/US2003/039610 WO2004055986A2 (en) 2002-12-13 2003-12-12 Reconfiguration of the programmable logic of an integrated circuit

Publications (2)

Publication Number Publication Date
CA2505165A1 true CA2505165A1 (en) 2004-07-01
CA2505165C CA2505165C (en) 2010-05-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CA2505165A Expired - Lifetime CA2505165C (en) 2002-12-13 2003-12-12 Reconfiguration of the programmable logic of an integrated circuit

Country Status (5)

Country Link
US (2) US6920627B2 (en)
EP (1) EP1573919B1 (en)
JP (1) JP4500772B2 (en)
CA (1) CA2505165C (en)
WO (1) WO2004055986A2 (en)

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EP1573919B1 (en) 2010-07-21
US6920627B2 (en) 2005-07-19
US20050193358A1 (en) 2005-09-01
JP2006510332A (en) 2006-03-23
WO2004055986A3 (en) 2004-11-25
US7227378B2 (en) 2007-06-05
WO2004055986A2 (en) 2004-07-01
US20040117755A1 (en) 2004-06-17
CA2505165C (en) 2010-05-04
JP4500772B2 (en) 2010-07-14
EP1573919A2 (en) 2005-09-14

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