CA2516347A1 - Hdl co-simulation in a high-level modeling system - Google Patents
Hdl co-simulation in a high-level modeling system Download PDFInfo
- Publication number
- CA2516347A1 CA2516347A1 CA002516347A CA2516347A CA2516347A1 CA 2516347 A1 CA2516347 A1 CA 2516347A1 CA 002516347 A CA002516347 A CA 002516347A CA 2516347 A CA2516347 A CA 2516347A CA 2516347 A1 CA2516347 A1 CA 2516347A1
- Authority
- CA
- Canada
- Prior art keywords
- hdl
- states
- hlms
- components
- data value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2117/00—Details relating to the type or aim of the circuit design
- G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Debugging And Monitoring (AREA)
Abstract
Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL
simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
Claims (13)
1. A method for simulating operations of a circuit design that includes high-level components and one or more HDL components, comprising:
simulating the high-level components of the design in a high-level modeling system (HLMS);
co-simulating the one or more HDL components of the design with an HDL simulator;
converting a data value from a data type of the HLMS
to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator;
converting a logic vector from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator; and scheduling an event for the HDL simulator as a function of a time of at least one HLMS event and a maximum response time of at least one HDL component.
simulating the high-level components of the design in a high-level modeling system (HLMS);
co-simulating the one or more HDL components of the design with an HDL simulator;
converting a data value from a data type of the HLMS
to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator;
converting a logic vector from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator; and scheduling an event for the HDL simulator as a function of a time of at least one HLMS event and a maximum response time of at least one HDL component.
2. The method of claim 1, wherein the HDL components support a set of signal states, the method further comprising:
implementing a set of states for each data type of the high-level components, one or more of the sets of states including a non-representable state;
for states of a set of output signals of the HDL
components that are representable as a data value in the high-level components, setting an output data value to a value corresponding to the states of the set of output signals;
for states of a set of output signals of the HDL
components that are not representable as a data value in the high-level components, setting the output data value to a non-representable state; and propagating non-representable states of data values in simulating the high-level components.
implementing a set of states for each data type of the high-level components, one or more of the sets of states including a non-representable state;
for states of a set of output signals of the HDL
components that are representable as a data value in the high-level components, setting an output data value to a value corresponding to the states of the set of output signals;
for states of a set of output signals of the HDL
components that are not representable as a data value in the high-level components, setting the output data value to a non-representable state; and propagating non-representable states of data values in simulating the high-level components.
3. The method of claim 2, further comprising:
translating states of the output signals to a translated set of states according to a map of the set of HDL signal states to a set of intermediate states; and setting the output data value to a non-representable state if the state of at least one signal in the translated set of states is equal to a predetermined value.
translating states of the output signals to a translated set of states according to a map of the set of HDL signal states to a set of intermediate states; and setting the output data value to a non-representable state if the state of at least one signal in the translated set of states is equal to a predetermined value.
4. The method of claim 2, further comprising:
translating states of the output signals to a translated set of states according to a map of the set of HDL signal states to a set of intermediate states; and signaling an error to the HLMS if the state of at least one signal in the translated set of states is equal to a predetermined value.
translating states of the output signals to a translated set of states according to a map of the set of HDL signal states to a set of intermediate states; and signaling an error to the HLMS if the state of at least one signal in the translated set of states is equal to a predetermined value.
5. The method of claim 2, further comprising:
translating states of the output signals to a translated set of states according to a map of the set of HDL signal states to a set of intermediate states; and converting the translated set of states to an output value if the states of the signals in the translated set of states are representable as a data value in the HLMS.
translating states of the output signals to a translated set of states according to a map of the set of HDL signal states to a set of intermediate states; and converting the translated set of states to an output value if the states of the signals in the translated set of states are representable as a data value in the HLMS.
6. The method of claim 2, further comprising if a data value to be input to the HDL simulator is in a non-representable state, setting states of elements in a logic vector to an analogous signal state.
7. The method of claim 1, further comprising:
maintaining an HLMS current time and an HDL
simulator current time; and selectively advancing the HDL simulator current time on a plurality of timescales, wherein at least a first one of the timescales is a function of the maximum response time of the HDL components, and at least a second one of the timescales is a function of the maximum response time and a maximum number of events queued to the HDL simulator during an HLMS timeslot.
maintaining an HLMS current time and an HDL
simulator current time; and selectively advancing the HDL simulator current time on a plurality of timescales, wherein at least a first one of the timescales is a function of the maximum response time of the HDL components, and at least a second one of the timescales is a function of the maximum response time and a maximum number of events queued to the HDL simulator during an HLMS timeslot.
8. The method of claim 1, further comprising:
maintaining an HLMS current time and an HDL
simulator current time, wherein each unit of HLMS time corresponds to K units of HDL simulator time, and K
satisfies the inequality K*.DELTA.Q > N*.DELTA.t MRT, where .DELTA.Q is a selected minimum period of time between HLMS events, N is an expected maximum number of events of the HDL simulator in any one HLMS timeslot, and .DELTA.t MRT is greater than the maximum response time;
advancing the HDL simulator current time by a period of time that is equal or greater than the maximum response time; and advancing the HLMS current time after processing all events scheduled in an HLMS timeslot and if the HDL
simulator current time is less than K times the HLMS
current time, then advancing the HDL simulator current time to K times the HLMS current time.
maintaining an HLMS current time and an HDL
simulator current time, wherein each unit of HLMS time corresponds to K units of HDL simulator time, and K
satisfies the inequality K*.DELTA.Q > N*.DELTA.t MRT, where .DELTA.Q is a selected minimum period of time between HLMS events, N is an expected maximum number of events of the HDL simulator in any one HLMS timeslot, and .DELTA.t MRT is greater than the maximum response time;
advancing the HDL simulator current time by a period of time that is equal or greater than the maximum response time; and advancing the HLMS current time after processing all events scheduled in an HLMS timeslot and if the HDL
simulator current time is less than K times the HLMS
current time, then advancing the HDL simulator current time to K times the HLMS current time.
9. The method of claim 8, wherein the HDL components support a set of signal states, the method further comprising:
implementing a set of states for each data type of the high-level components, one or more of the sets of states including a non-representable state;
for states of a set of output signals of the HDL
components that are representable as a data value in the high-level components, setting an output data value to a value corresponding to the states of the set of output signals;
for states of a set of signals of the HDL components that are not representable as a data value in the high-level components, setting the output data value to a non-representable state; and propagating non-representable states of data values in simulating the high-level components.
implementing a set of states for each data type of the high-level components, one or more of the sets of states including a non-representable state;
for states of a set of output signals of the HDL
components that are representable as a data value in the high-level components, setting an output data value to a value corresponding to the states of the set of output signals;
for states of a set of signals of the HDL components that are not representable as a data value in the high-level components, setting the output data value to a non-representable state; and propagating non-representable states of data values in simulating the high-level components.
10. An apparatus for simulating operations of a circuit design that includes high-level components and one or more HDL components, comprising:
means for simulating the high-level components of the design in a high-level modeling system (HLMS);
means for co-simulating the one or more HDL
components of the design with an HDL simulator;
means for converting a data value from a data type of the HLMS to a logic vector compatible with the HDL
simulator for each data value to be input to the HDL
simulator;
means for converting a logic vector from the HDL
simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL
simulator; and means for scheduling events for input to the HDL
simulator as a function of a data rate of the HLMS and response time of the HDL components.
means for simulating the high-level components of the design in a high-level modeling system (HLMS);
means for co-simulating the one or more HDL
components of the design with an HDL simulator;
means for converting a data value from a data type of the HLMS to a logic vector compatible with the HDL
simulator for each data value to be input to the HDL
simulator;
means for converting a logic vector from the HDL
simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL
simulator; and means for scheduling events for input to the HDL
simulator as a function of a data rate of the HLMS and response time of the HDL components.
11. A high level modeling system (HLMS) adapted to co-simulate with an HDL simulator operations of a circuit design that includes high-level components and one or more HDL components, comprising:
a first type converter configured to convert a data value from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator;
a second type converter configured to convert a logic vector from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator; and a co-simulation event scheduler configured to schedule events for input to the HDL simulator as a function of a data rate of the HLMS and response time of the HDL components.
a first type converter configured to convert a data value from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator;
a second type converter configured to convert a logic vector from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator; and a co-simulation event scheduler configured to schedule events for input to the HDL simulator as a function of a data rate of the HLMS and response time of the HDL components.
12. The system of claim 11, wherein the HDL components support a set of signal states, the system further comprising:
wherein the HLMS is configured to implement a set of states for each data type of the high-level components, one or more of the sets of states including a non-representable state;
the second type converter is further configured to, for states of a set of output signals of the HDL
components that are representable as a data value in the high-level components, set an output data value to a value corresponding to the states of the set of output signals;
the second type converter is further configured to, for states of a set of signals of the HDL components that are not representable as a data value in the high-level components, set the output data value to a non-representable state; and the HLMS is further configured to propagate non -representable states of data values in simulating the high-level components.
wherein the HLMS is configured to implement a set of states for each data type of the high-level components, one or more of the sets of states including a non-representable state;
the second type converter is further configured to, for states of a set of output signals of the HDL
components that are representable as a data value in the high-level components, set an output data value to a value corresponding to the states of the set of output signals;
the second type converter is further configured to, for states of a set of signals of the HDL components that are not representable as a data value in the high-level components, set the output data value to a non-representable state; and the HLMS is further configured to propagate non -representable states of data values in simulating the high-level components.
13. The system method of claim 12, wherein the first type converter is further configured to, if a data value to be input to the HDL simulator is in a non-representable state, set states of elements in a logic vector to an analogous signal state.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/389,161 US7203632B2 (en) | 2003-03-14 | 2003-03-14 | HDL co-simulation in a high-level modeling system |
| US10/389,161 | 2003-03-14 | ||
| PCT/US2004/007824 WO2004084027A2 (en) | 2003-03-14 | 2004-03-12 | Mixed-level hdl/high-level co-simulation of a circuit design |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2516347A1 true CA2516347A1 (en) | 2004-09-30 |
| CA2516347C CA2516347C (en) | 2011-01-04 |
Family
ID=32962213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2516347A Expired - Lifetime CA2516347C (en) | 2003-03-14 | 2004-03-12 | Hdl co-simulation in a high-level modeling system |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7203632B2 (en) |
| EP (1) | EP1604312B1 (en) |
| CA (1) | CA2516347C (en) |
| WO (1) | WO2004084027A2 (en) |
Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7065481B2 (en) * | 1999-11-30 | 2006-06-20 | Synplicity, Inc. | Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer |
| US7072818B1 (en) | 1999-11-30 | 2006-07-04 | Synplicity, Inc. | Method and system for debugging an electronic system |
| US7222315B2 (en) | 2000-11-28 | 2007-05-22 | Synplicity, Inc. | Hardware-based HDL code coverage and design analysis |
| US7827510B1 (en) | 2002-06-07 | 2010-11-02 | Synopsys, Inc. | Enhanced hardware debugging with embedded FPGAS in a hardware description language |
| US7184946B2 (en) * | 2003-06-19 | 2007-02-27 | Xilinx, Inc. | Co-simulation via boundary scan interface |
| US7873506B2 (en) * | 2003-06-30 | 2011-01-18 | Agere Systems Inc. | Simulation framework with support for multiple integrated circuits having potentially differing characteristics |
| US7840949B2 (en) * | 2003-11-03 | 2010-11-23 | Ramal Acquisition Corp. | System and method for data transformation using dataflow graphs |
| US7207027B2 (en) * | 2003-12-30 | 2007-04-17 | Xilinx, Inc. | Algorithmic and dataflow graphical representation of MATLAB |
| US7284225B1 (en) | 2004-05-20 | 2007-10-16 | Xilinx, Inc. | Embedding a hardware object in an application system |
| US7433813B1 (en) | 2004-05-20 | 2008-10-07 | Xilinx, Inc. | Embedding a co-simulated hardware object in an event-driven simulator |
| US7346481B1 (en) * | 2004-08-31 | 2008-03-18 | Xilinx, Inc. | Hardware co-simulation breakpoints in a high-level modeling system |
| US7437280B1 (en) * | 2004-12-16 | 2008-10-14 | Xilinx, Inc. | Hardware-based co-simulation on a PLD having an embedded processor |
| US7386814B1 (en) | 2005-02-10 | 2008-06-10 | Xilinx, Inc. | Translation of high-level circuit design blocks into hardware description language |
| US8036873B2 (en) * | 2005-02-28 | 2011-10-11 | Synopsys, Inc. | Efficient clock models and their use in simulation |
| US7346482B1 (en) * | 2005-03-08 | 2008-03-18 | Xilinx, Inc. | Shared memory for co-simulation |
| US7493578B1 (en) * | 2005-03-18 | 2009-02-17 | Xilinx, Inc. | Correlation of data from design analysis tools with design blocks in a high-level modeling system |
| US7343572B1 (en) | 2005-03-31 | 2008-03-11 | Xilinx, Inc. | Vector interface to shared memory in simulating a circuit design |
| US7685554B1 (en) * | 2005-07-20 | 2010-03-23 | Xilinx, Inc. | Determination of data rate and data type in a high-level electronic design |
| US7496869B1 (en) | 2005-10-04 | 2009-02-24 | Xilinx, Inc. | Method and apparatus for implementing a program language description of a circuit design for an integrated circuit |
| US7363599B1 (en) | 2005-10-04 | 2008-04-22 | Xilinx, Inc. | Method and system for matching a hierarchical identifier |
| US7895564B1 (en) * | 2005-11-08 | 2011-02-22 | Xilinx, Inc. | Using XTables to communicate in a high level modeling system |
| US7797677B1 (en) * | 2005-11-08 | 2010-09-14 | Xilinx, Inc. | Using scripts for netlisting in a high-level modeling system |
| US8402409B1 (en) | 2006-03-10 | 2013-03-19 | Xilinx, Inc. | Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit |
| US7380232B1 (en) | 2006-03-10 | 2008-05-27 | Xilinx, Inc. | Method and apparatus for designing a system for implementation in a programmable logic device |
| US7761272B1 (en) | 2006-03-10 | 2010-07-20 | Xilinx, Inc. | Method and apparatus for processing a dataflow description of a digital processing system |
| GB0619537D0 (en) * | 2006-10-04 | 2006-11-15 | Mephisto Design Automation Nv | Method and apparatus for the simultaneous multi-level and/or multi-simulator design optimization of electronic circuits |
| US8284772B1 (en) * | 2007-05-03 | 2012-10-09 | Xilinx, Inc. | Method for scheduling a network packet processor |
| US8600722B1 (en) * | 2007-05-22 | 2013-12-03 | Xilinx, Inc. | Method and apparatus for providing program-based hardware co-simulation of a circuit design |
| US7904850B2 (en) * | 2007-11-30 | 2011-03-08 | Cebatech | System and method for converting software to a register transfer (RTL) design |
| US8239850B2 (en) * | 2007-12-14 | 2012-08-07 | GM Global Technology Operations LLC | Computer-implemented method of releasing battery state estimation software |
| JP2009193165A (en) * | 2008-02-12 | 2009-08-27 | Toshiba Corp | Debugging device and method |
| US8265917B1 (en) * | 2008-02-25 | 2012-09-11 | Xilinx, Inc. | Co-simulation synchronization interface for IC modeling |
| US20090222253A1 (en) * | 2008-03-03 | 2009-09-03 | Thomas Jay Sheffler | System and Method for Switch-Level Linear Simulation Using Verilog |
| US8079013B1 (en) * | 2008-12-19 | 2011-12-13 | Xilinx, Inc. | Hardware description interface for a high-level modeling system |
| TW201301135A (en) * | 2011-06-16 | 2013-01-01 | Hon Hai Prec Ind Co Ltd | System and method for converting component data |
| US10176276B2 (en) * | 2012-09-05 | 2019-01-08 | Cadence Design Systems, Inc. | Determining an optimal global quantum for an event-driven simulation |
| US10191828B2 (en) * | 2015-05-07 | 2019-01-29 | Vmware, Inc. | Methods and apparatus to control a monitoring agent in a computing environment |
| US10067854B2 (en) * | 2016-10-25 | 2018-09-04 | Xilinx, Inc. | System and method for debugging software executed as a hardware simulation |
| US10409321B2 (en) | 2017-02-03 | 2019-09-10 | Raytheon Company | Simulation system with clock and messaging synchronization |
| US10949586B1 (en) * | 2020-07-01 | 2021-03-16 | Xilinx, Inc. | Post-synthesis insertion of debug cores |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5572437A (en) * | 1990-04-06 | 1996-11-05 | Lsi Logic Corporation | Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models |
| US5493508A (en) * | 1994-06-01 | 1996-02-20 | Lsi Logic Corporation | Specification and design of complex digital systems |
| EP1059593A3 (en) | 1999-06-07 | 2003-09-10 | Easics N.V. | Deterministic level model and method |
| US20020049576A1 (en) * | 2000-07-05 | 2002-04-25 | Meyer Steven J. | Digital and analog mixed signal simulation using PLI API |
| US7260517B2 (en) * | 2001-06-17 | 2007-08-21 | Brian Bailey | Synchronization of multiple simulation domains in an EDA simulation environment |
| US7110935B1 (en) | 2001-10-16 | 2006-09-19 | Xilinx, Inc. | Method and system for modeling and automatically generating an electronic design from a system level environment |
-
2003
- 2003-03-14 US US10/389,161 patent/US7203632B2/en active Active
-
2004
- 2004-03-12 EP EP04720491A patent/EP1604312B1/en not_active Expired - Lifetime
- 2004-03-12 CA CA2516347A patent/CA2516347C/en not_active Expired - Lifetime
- 2004-03-12 WO PCT/US2004/007824 patent/WO2004084027A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| EP1604312B1 (en) | 2011-06-15 |
| CA2516347C (en) | 2011-01-04 |
| US7203632B2 (en) | 2007-04-10 |
| US20040181385A1 (en) | 2004-09-16 |
| WO2004084027A3 (en) | 2005-09-29 |
| EP1604312A2 (en) | 2005-12-14 |
| WO2004084027A2 (en) | 2004-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2516347A1 (en) | Hdl co-simulation in a high-level modeling system | |
| US20150022236A1 (en) | Apparatus and Methods for Time-Multiplex Field-Programmable Gate Arrays | |
| EP3407145B1 (en) | Fpga-based square-wave generator and square-wave generation method | |
| US7973584B2 (en) | Waveform generator | |
| US20030018462A1 (en) | Multi-clock system simulation | |
| US8156452B1 (en) | Method and apparatus for importing hardware description language into a system level design environment | |
| Lipasti et al. | End-to-end stochastic computing | |
| BenSaleh et al. | Field programmable gate array realization of microprogrammed controller based parallel digital FIR filter architecture | |
| Grimm et al. | Refinement of mixed-signal systems with SystemC | |
| CN110764492B (en) | Multichannel switching value signal generating device and SOE event simulator | |
| Guillaud et al. | From basic concept to real-time implementation: prototyping WCDMA downlink receiver algorithms-a case study | |
| Note et al. | Rapid prototyping of DSP systems: requirements and solutions | |
| Karner et al. | Heterogeneous co-simulation platform for the efficient analysis of FlexRay-based automotive distributed embedded systems | |
| CN102004811A (en) | Simulation test method and device of chip circuit | |
| US8417505B1 (en) | System and method for simulating a transmission gate network and a bi-directional connect module within an analog and mixed-signal circuit | |
| Alecsa et al. | An FPGA implementation of the time domain deadbeat algorithm for control applications | |
| SU1543417A1 (en) | Device for simulating of node of electric circuit | |
| Brich et al. | The digital signal processing using fpga | |
| Schirner et al. | Accurate yet fast modeling of real-time communication | |
| Sobot et al. | Behavioral modeling of continuous time/spl Delta//spl Sigma/modulators | |
| Padma et al. | Design & Development of micro-controlled system using VHDL with the help of UART Tx & Rx | |
| JP2005165747A (en) | Verification system | |
| CN115549641A (en) | Design method of full-rate symmetric multi-channel FIR filter | |
| Ameur et al. | FPGA-based design Δ–Σ audio D/A converter with a resolution clock generator enhancement circuit | |
| Subramanian et al. | Staying ahead of the game in silicon for digital mobile communications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request |