CA2535878A1 - Adaptive load balancing in a multi-processor graphics processing system - Google Patents

Adaptive load balancing in a multi-processor graphics processing system Download PDF

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CA2535878A1
CA2535878A1 CA002535878A CA2535878A CA2535878A1 CA 2535878 A1 CA2535878 A1 CA 2535878A1 CA 002535878 A CA002535878 A CA 002535878A CA 2535878 A CA2535878 A CA 2535878A CA 2535878 A1 CA2535878 A1 CA 2535878A1
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graphics
graphics processors
display area
gpu
feedback data
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French (fr)
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Franck R. Diard
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Nvidia Corp
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Nvidia Corporation
Franck R. Diard
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/005General purpose rendering architectures
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/393Arrangements for updating the contents of the bit-mapped memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2210/00Indexing scheme for image generation or computer graphics
    • G06T2210/52Parallel processing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00Parallel handling of streams of display data

Abstract

Systems and methods for balancing a load among multiple graphics processors that render different portions of a frame. A display area is partitioned into portions for each of two (or more) graphics processors. The graphics processors render their respective portions of a frame and return feedback data indicating completion of the rendering. Based on the feedback data, an imbalance can be detected between respective loads of two of the graphics processors. In the event that an imbalance exists, the display area is re-partitioned to increase a size of the portion assigned to the less heavily loaded processor and to decrease a size of the portion assigned to the more heavily loaded processor.

Description

ADAPTIVE LOAD BALANCING IN A MULTI-PROCESSOR
GRAPHICS PROCESSING SYSTEM
CROSS-REFERENCES TO RELATED APPLICATIONS
[0001] The present disclosure is related to the following commonly-assigned co-pending U.S. Patent Applications: No. (Attorney Docket No. 019680-006000US), filed on the same date as the present application, entitled "Private Addressing in a Multi-Processor Graphics Processing System" and No. (Attorney Docket No. 019680-005900US), filed , entitled "Programming Multiple Chips from a Command Buffer," the respective disclosures of which are incorporated herein by reference for all purposes.
BACKGROUND OF THE INVENTION
[0002] The present invention relates generally to graphics processing subsystems with multiple processors and in particular to adaptive load balancing for such graphics processing subsystems.
[0003] Graphics processing subsystems are designed to render realistic animated images in real time, e.g., at 30 or more frames per second. These subsystems are most often implemented on expansion cards that can be inserted into appropriately configured slots on a motherboard of a computer system and generally include one or more dedicated graphics processing units (GPUs) and dedicated graphics memory. The typical GPU is a highly complex integrated circuit device optimized to perform graphics computations (e.g., matrix transformations, scan-conversion and/or other rasterization techniques, texture blending, etc.) and write the results to the graphics memory. The GPU is a "slave" processor that operates in response to commands received from a driver program executing on a "master"
processor, generally the central processing unit (CPU) of the system.
[0004] To meet the demands for realism and speed, some GPUs include more transistors than typical CPUs. In addition, graphics memories have become quite large in order to improve speed by reducing traffic on the system bus; some graphics cards now include as much as 256 MB of memory. But despite these advances, a demand for even greater realism and faster rendering persists.
[0005] As one approach to meeting this demand, some manufacturers have begun to develop "mufti-chip" graphics processing subsystems in which two or more GPUs, usually on the same card, operate in parallel. Parallel operation substantially increases the number of rendering operations that can be carried out per second without requiring significant advances in GPU design. To minimize resource conflicts between the GPUs, each GPU is generally provided with its own dedicated memory area, including a display buffer to which the GPU
writes pixel data it renders.
[0006] In a mufti-chip system, the processing burden may be divided among the GPUs in various ways. For example, each GPU may be instructed, to render pixel data for a different portion of the displayable image, such as a number of lines of a raster-based display. The image is displayed by reading out the pixel data from each GPU's display buffer in an appropriate sequence. As a more concrete example, a graphics processing subsystem may use two GPUs to generate a displayable image consisting of M rows of pixel data; the first GPU can be instructed to render rows 1 through P, while the second GPU is instructed to render rows P+1 through M. To preserve internal consistency of the displayed image ("frame coherence"), each GPU is prevented from rendering a subsequent frame until the other GPU
has also finished the current frame so that both portions of the displayed image are updated in the same scanout pass.
[000'7] Ideally, the display area (or screen) is partitioned in such, a way that each GPU
requires an equal amount of time to render its portion of the image. If the rendering times are unequal, a GPU that finishes its portion of the frame first will be idle, wasting valuable computational resources. In general, simply partitioning the display area equally among the GPUs is not an optimal solution because the rendering complexity of different parts of an image can vary widely. For example, in a typical scene from a video game, the foreground characters and/or vehicles - which are often complex objects rendered from a large number of primitives - tend to appear near the bottom of the image, while the top portion of the image is often occupied by a relatively static background that can be rendered from relatively few primitives and texture maps. When such an image is split into top and bottom halves, the GPU that renders the top half will generally complete its portion of the image, then wait for the other GPU to finish. To avoid this idle time, it would be desirable to divide the display area unequally, with the top portion being larger than the bottom portion. In general, the optimal division depends on the particular scene being rendered and may vary over time even within a single video game or other graphics application.
[0008] It would, therefore, be desirable to provide a mechanism whereby the processing load on each GPU can be monitored and the division of the display area among the GPUs can be dynamically adjusted to balance the loads.
BRIEF SUMMARY OF THE INVENTION
[0009] The present invention provides systems and methods for balancing a load among multiple graphics processors that render different portions of a frame.
[0010] According to one aspect of the invention, a method is provided for load balancing for graphics processors configured to operate in parallel. A display area is partitioned into at least a first portion to be rendered by a first one of the graphics processors and a second portion to be rendered by a second one of the graphics processors. The graphics processors are instructed to render a frame, wherein the first and second graphics processors perform rendering for the first and second portions of the display area, respectively.
Feedback data for the frame is received from the first and second graphics processors, the feedback data reflecting respective rendering times for the first and second graphics processors. Based on the feedback data, it is determined whether an imbalance exists between respective loads of the first and second graphics processors. In the event that an imbalance exists, based on the feedback data, the one of the first and second graphics processors that is more heavily loaded is identified; the display area is re-partitioned to increase a size of the one of the first and second portions of the display area that is xendered by the more heavily loaded one of the first and second graphics processors and to decrease a size of the other of the first and second portions of the display area.
[0011] According to another aspect of the invention, a method is provided for load balancing for graphics processors configured to operate in parallel. A display area is partitioned into at least a first portion to be rendered by a first graphics processor and a second portion to be rendered by a second graphics processor. The graphics processors are instructed to render a number of frames, wherein the first and second graphics processors perform rendering for the first and second portions of the display area, respectively.
Feedback data for each of the frames is received from the first and second graphics processors, the feedback data for each frame indicating which of the first and second graphics processors was last to finish rendering the frame. Based on the feedback data, it is determined whether an imbalance exists between respective loads of the first and second graphics processors. In the event that an imbalance exists, based on the feedback data, the one of the first and second graphics processors that is more heavily loaded is identified; the display area is re-partitioned to increase a size of the one of the first and second portions of the display area that is rendered by the more heavily loaded one of the first and second S graphics processors and to decrease a size of the other of the first and second portions of the display area.
[0012] In some embodiments, a storage location is associated with each one of the frames, and receiving the feedback data for each of the frames includes instructing the first graphics processor to store a first processor identifier in the associated one of the storage locations for i 0 each of the frames after rendering the fixst portion of the display area for that frame; and instructing the second graphics processor to store a second processor identifier different from the first processor identifier in the associated one of the storage locations for each of the frames after rendering the second portion of the display area for that frame.
Each of the first and second identifiers may have a different numeric value and determination of whether an 15 imbalance exists may include computing a load coefficient from the numeric values stored in the storage locations. The load coefficient may be, e.g., an average of the recorded numeric values that can be compared to an arithmetic mean of the numeric values of the processor identifiers in order to determine whether an imbalance exists.
[0013] In some embodiments, during the act of re-partitioning, an amount by which the size 20 of the first portion of the display area is reduced depends at least in part on a magnitude of the difference between the load coefficient and the arithmetic mean.
[0014] In some embodiments, the plurality of graphics processors further includes a third graphics processor. During the act of partitioning, the display area may be partitioned 'into at least three bands including a first band that corresponds to the first portion of the display 25 area, a second band that corresponds to the second portion of the display area, and a third band that corresponds to a third portion of the display area to be rendered by the third graphics processor, wherein the first band is adjacent to the second band and the second band is adjacent to the third band. Additional feedback data may be received for each of the frames, the additional feedback data indicating which of the second and third graphics 30 processors was last to finish rendering the frame. Based on the feedback data, it may be determined whether an imbalance exists between respective loads of the second and third graphics processors. In the event that an imbalance exists, it may be determined which of the second and third graphics processors is more heavily loaded, and the display area may be re-partitioned to increase a size of the one of the second and third portions of the display area that is rendered by the more heavily loaded one of the second and third graphics processors and to decrease a size of the other of the second and third portions of the display area.
[0015] According to yet another aspect of the invention, a driver for a graphics processing subsystem having multiple graphics processors includes a command stream generator, an imbalance detecting module, and a partitioning module. The command stream generator is configured to generate a command stream for the graphics processors, the command stream including a set of rendering commands for a 'frame and an instruction to each of a first one and a second one of the graphics processors to transmit feedback data indicating that the respective processor has executed the set of rendering commands. The imbalance detecting module is configured to receive the feedback data transmitted by the first and second graphics processors and to determine from the feedback data whether an imbalance exists between respective loads of the first and second graphics processors. The partitioning module is configured to partition a display area into a plurality of portions, each portion to be rendered by a different one of the graphics processors, the plurality of portions including a first portion to be rendered by the first graphics processor and a second portion to be rendered by the second graphics processor. The partitioning module is further configured such that, in response to a determination by the imbalance detecting module that an imbalance exists, the partitioning module increases a size of the one of the first and second portions of the display area that is rendered by the more heavily loaded one of the first and second graphics processors and decreases a size of the other of the fixst and second portions of the display area.
[0016] The following detailed description together with the accompanying drawings will provide a better understanding of the nature and advantages of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
(0017] Fig. 1 is a simplified block diagram of a computer system according to an embodiment of the present invention;
[0018] Fig. 2 is an illustration of a display area showing spatial parallelism according to an embodiment of the present invention;
[0019] Fig. 3 is an illustration of a command stream according to an embodiment of the present invention;
[0020] Fig. 4 is a flow diagram of a process for providing feedback data from a graphics processing unit according to an embodiment of the present invention;
S [0021] Fig. 5 is a flow diagram of a process for balancing a load between two graphics processing units according to an embodiment of the present invention;
[0022] Fig. 6 is an illustration of a display area showing three-way spatial parallelism according to an embodiment of the present invention;
[0023] Fig. 7 is an illustration of a pair of feedback arrays for three-way spatial parallelism according to an embodiment of the present invention;
(0024] Fig. 8 is an illustration of a display area showing four-way spatial parallelism according to an embodiment of the present invention;
[0025] Fig. 9 'is a simplified block diagram of a mufti-card graphics processing system according to an embodiment of the present invention; and [0026] Fig. 10 is an illustration of command streams for a mufti-card graphics processing system according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0027] The present invention provides systems and methods for balancing a load among multiple graphics processors that render different portions of a frame. In some embodiments, load balancing is performed by determining whether one of two graphics processors finishes rendering a frame last more often than the other. If one of the processors finishes last more often, a portion of the processing burden (e.g., a number of lines of pixels to render) is shifted from that processor to the other processor. The comparison can be repeated and the load adjusted as often as desired. The technique of pairwise load comparisons and balancing can be extended to systems with any number of graphics processors.
[0028] Fig. 1 is a block diagram of a computer system 100 according to an embodiment of the present invention. Computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 communicating via a bus 106. User input is received from one or more user input devices 108 (e.g., keyboard, mouse) coupled to bus 106. Visual output is provided on a pixel based display device 110 (e.g., a conventional CRT or LCD
based monitor) operating under control of a graphics processing subsystem 112 coupled to system bus 106. A system disk 128 and other components, such as one or more removable storage devices 129 (e.g., floppy disk drive, compact disk (CD) drive, and/or DVD
drive), may also be coupled to system bus 106.
[0029] Graphics processing subsystem 112 is advantageously implemented using a printed circuit card adapted to be connected to an appropriate bus slot (e.g., PCI or AGP) on a motherboard of system 100. , In this embodiment, graphics processing subsystem includes two (or more) graphics processing units (GPUs) 114a, 114b, each of which is advantageously implemented as a separate integrated circuit device (e.g., programmable processor or application-speck integrated circuit (ASIC)). GPUs 114a, 114b are configured to perform vaxious rendering functions in response to instructions (commands) received via system bus 106. In. some embodiments, the rendering functions correspond to various steps in a graphics processing pipeline by which geometry data describing a scene is transformed to pixel data for displaying on display device 110. These functions can include, for example, lighting transformations, coordinate transformations, scan-conversion of geometric primitives to rasterized data, shading computations, shadow rendering, texture blending, and so on.
Numerous implementations of rendering functions are known in the art and may be implemented in GPUs 114a, 114b. GPUs 114a, 114b are advantageously configured identically so that any graphics processing instruction can be executed by either GPU with substantially identical results.
[0030] Each GPU 114a,114b has an associated graphics memory 116a, 116b, which may be implemented using one or more integrated-circuit memory devices of generally conventional design. Graphics memories 116a, 116b may contain various physical or logical subdivisions, such as display buffers 122a, 122b and command buffers 124a, 124b. Display buffers 122a, 122b store pixel data for an image (or for a part of an image) that is read by scanout control logic 120 and transmitted to display device 110 for display.
This pixel data may be generated from scene data provided to GPUs 114a, 114b via system bus 106 or generated by various processes executing on CPU 102 and provided to display buffers 122a, 122b via system bus 106. In some embodiments, display buffers 122a,122b can be double buffered so that while data for a first image is being read for display from a "front" buffer, data for a second image can be written to a "back" buffer without affecting the currently displayed image. Command buffers 124a, 124b are used to queue commands received via system bus 106 for execution by respective GPUs 114a, 114b, as described below. Other portions of graphics memories 116x, 116b may be used to store data required by respective GPUs 114a,114b (such as texture data, color lookup tables, etc.), executable program code for GPUs 114a, 114b, and so on.
S [0031] For each graphics memory 116x, 116b, a memory interface 123a, 123b is also provided for controlling access to the respective graphics memory. ~ Memory interfaces 123a, 123b can be integrated with respective GPUs 114a, 114b or with respective memories 116a, 116b, or they can be implemented as separate integrated circuit devices. In one embodiment, all memory access requests originating from GPU 114a are sent to memory interface 123a. If the target address of the request corresponds to a location in memory 116a, memory interface 123a accesses the appropriate location; if not, then memory interface 123a forwards the request to a bridge unit 130, which is described below. Memory interface 123a also receives all memory access requests targeting locations in memory 116a; these requests may originate from scanout control logic 120, CPU 102, or other system components, as well as from GPU
114a or 114b. Similarly, memory interface 123b receives all memory access requests that originate from GPU 114b or that target locations in memory 116b.
[0032] Bridge unit 130 is configured to manage communication between components of graphics processing subsystem 112 (including memory interfaces 123a, 123b) and other components of system 100. For example, bridge unit 130 may receive all incoming data transfer requests from system bus 106 and distribute (or broadcast) the requests to one or more of memory interfaces 123a,123b: Bridge unit 130 may also receive data transfer requests originating from components of graphics processing subsystem 112 (such as GPUs 114a,114b) that reference memory locations external to graphics processing subsystem 112 and transmit these requests via system bus 106. In addition, in some embodiments, bridge unit 130 facilitates access by either of GPUs 114a, 114b to the memory 116b, 116a associated with the other of GPUs 114a, 114b. Examples of implementations of bridge unit 130 are described in detail in the above-referenced co-pending application No.
(Attorney Docket No. 019680-006000US); a detailed description is omitted herein as not being critical to understanding the present invention.
[0033] In operation, a graphics driver program (or other program) executing on delivers rendering commands and associated data for processing by GPUs 114a, 114b. In some embodiments, CPU 102 communicates asynchronously with each of GPUs 114a, 114b using a command buffer, which may be implemented in any memory accessible to both the CPU 102 and the GPUs 114a, 114b. In one embodiment, the command buffer is stored in system memory 104 and is accessible to GPUs 114a, 114b via direct memory access (DMA) transfers. In another embodiment, each GPU 114a, 114b has a respective command buffer 124a, 124b in its memory 116a, 116b; these command buffers are accessible to CPU 102 via DMA transfers. The command buffer stores a number of rendering commands and sets of rendering data. In one embodiment, a rendering command may be associated with rendering data, with the rendering command defining a set of rendering operations to be performed by the GPU on the associated rendering data. In some embodiments, the rendering data is stored in the command buffer adjacent to the associated rendering command.
[4034] CPU 102 writes a command stream including rendering commands and data sets to the command buffer for each GPU 114a,114b (e.g., command buffers 124a,124b).
In some, embadiments, the same rendering commands and data are written to each GPU's command buffer (e.g., using a broadcast mode of bridge chip.130); in other embodiments, CPU 102 writes to each GPU's command buffer separately. Where the same command stream is provided to both GPUs 114a, 114b, the command stream may include tags or other parameters to indicate which of.the GPUs should process a particular command.
[0035) Each command buffer 124a, 124b is advantageously implemented as a first-in, first-out buffer (FIFO) that is written by CPU 102 and read by the respective one of GPUs 114a, 114b; reading and writing can occur asynchronously. In one embodiment, periodically writes new commands and data to each command buffer at a location determined by a "put" pointer, which CPU 102 increments after each write. Asynchronously, each of GPUs 114a, 114b continuously reads and processes commands and data sets previously stored in its command buffer 124a,124b; each GPU 114a,114b maintains a "get"
pointer to identify the read location in its command buffer 124a, 124b, and the get pointer is incremented after each read. Provided that CPU 102 stays sufficiently far ahead of GPUs 114a, 114b, the GPUs are able to render images without incurring idle time waiting for CPU
102. In some embodiments, depending on the size of the command bufFer and the complexity of a scene, CPU 102 may write commands and data sets for frames several frames ahead of a frame being rendered by GPUs 114a,114b.
[0036] The command buffer may be of fixed size (e.g., 5 megabytes) and may be written and read in a wraparound fashion (e.g., after writing to the last location, CPU 102 may reset the "put" pointer to the first location). A more detailed description of embodiments of command buffers and techniques for writing commands and data to command buffers in a mufti-chip graphics processing system is provided in the above-referenced co-pending application No. (Attorney Docket No. 019680-005900US).
[0037] Scanout control logic 120 reads pixel data for an image from frame buffers 122a, 122b and transfers the data to display device 110 to be displayed. Scanout can occur at a constant refresh rate (e.g., 80 Hz); the refresh rate can be a user selectable parameter and need not correspond to the rate at which new frames of image data are written to display buffers 122a, 122b. Scanout control logic 120 may also perform other operations such as adjustment of color values, generating composite screen images by combining the pixel data in either of the display buffers 122a,122b with data. for a video or cursor overlay image or the like obtained from either of graphics memories 116a, 116b or another data source (not shown), digital to analog conversion, and so on.
[0038] GPUs 114a, 114b are advantageously operated in parallel to increase the rate at which new frames of image data can be rendered. In one embodiment, referred to herein as "spatial parallelism," each GPU 114a, 114b generates pixel data for a different portion (e.g., a horizontal or vertical band) of each frame; scanout control logic 120 reads a first portion (e.g., the top portion) of the pixel data for a frame from display buffer 122a and a second portion (e.g., the bottom portion) from display buffer 122b. For spatial parallelism; rendering.
commands and accompanying data may be written in parallel to both command buffers 124a, 124b (e.g., using a broadcast mode of bridge unit 130), but commands andlor data can also be selectively written to one or more of the command buffers (e.g., different parameters for a command that defines the viewable area might be written to the different command buffers so that each GPU renders the correct portion of the image).
[0039] An example of spatial parallelism is shown in Fig. 2. A display area 200 consists of M lines (horizontal rows) of pixel data. Lines 1 through P (corresponding to top portion 202 of display area 200) are rendered by GPU 114a of Fig. 1, while lines P+1 through M
(corresponding to bottom portion 204 of display area 200) are rendered by GPU
114b. In this embodiment, each GPU 114a, 114b allocates a display buffer 122x, 122b in its local memory 116a, 116b that is large enough to store an entire frame (M lines) of data but only fills the lines it renders (lines 1 through P for GPU 114a and lines P+1 through M for GPU 114b).
During each display refresh cycle, scanout control logic 120 reads the first P
lines from display buffer 122a, then switches to display buffer 122b to read lines P+1 through M. To determine which lines each GPU renders, a "clip rectangle" is set for each GPU; for example, GPU 114a may have a clip rectangle corresponding to top portion 202 of frame 200 while GPU 114b has a clip rectangle corresponding to bottom portion 204 of frame 200.
[0040] In accordance with an embodiment of the present invention, each GPU
provides feedback data to the graphics driver program (or another program executing on CPU 102).
The feedback data provides information about the time taken by a particular GPU to render its portion of the image. The graphics driver program uses this feedback to dynamically balance the load among the GPUs by modifying the clip rectangle from time to time, e.g., by changing the dividing line to a different line P', based on the relative loads on the two GPUs.
[0041] An example of a command stream 300 that may be written to either (or both) of command buffers 124a, 124b is shown in Fig. 3. The stream starts with a "clip rectangle"
(CR) command 302, which defines the viewable area of the image. For example, the clip rectangle for GPU 114a may be defined to include lines 1 through P of display area 200 (Fig.
2), while the clip rectangle for GPU 114b includes lines P+1 through M. As used herein, the term "clip rectangle" is to be understood as including any particular command or terminology associated with defining the visible portion of the image plane far a frame or image, or more specifically, the portion of the image plane that a particular GPU is instructed to render.
[0042] The clip rectangle command is followed by one or more rendering commands 304 and associated rendering data for a frame F0. These commands and data may include, for instance, definitions of primitives andlor objects making up the scene, coordinate transformations, lighting transformations, shading commands, texture commands, and any other type of rendering commands and/or data, typically culminating in the writing of pixel data to display buffers 122a, 122b (and reading of that data by scanout control logic 120).
[0043] Following the Iast rendering command 304 for frame FO is a "write notifier" (WIC
command 306. The write notifier command instructs the GPU to write feedback data to system memory indicating that it has finished the frame F0. This feedback data can be read by the graphics driver program and used to balance the load among the GPUs.
Specific embodiments of feedback data are described below.
[0044] Write notifier command 306 is followed by rendering commands 308 and associated rendering data for the next frame F1, which in turn are followed by another write notifier command 310, and so on. After some number (Q) of frames, there is a write notifier command 322 followed by a new clip rectangle command 324. At this point, the clip rectangles for each GPU may be modified by the graphics driver program based on the feedback data received in response to the various write notifier commands (e.g., commands 306, 310). For example, where the display area is divided as shown in Fig. 2, the value of P
may be modified (e.g., to P') in response to feedback data: if the GPU that processes top portion 202 tends to finish its frames first, the value of P is increased, and if the GPU that processes bottom portion 204 tends to finish first, the value of P is decreased. Specific embodiments of re-partitioning a display area in response to feedback data are described below.
[0045) It will be appreciated that the system described herein is illustrative and that variations and modifications are possible. For instance, while two GPUs, with respective memories, are shown, any number of GPUs can be used, and multiple GPUs might share a memory. The memory interfaces described herein may be integrated with a GPU
andlor a memory in a single integrated, circuit device (chip) or implemented as separate chips. The bridge unit may be integrated with any of the memory interface and/or GPU
chips, or may be implemented on a separate chip. The various memories can be implemented using one or more integrated circuit devices. Graphics processing subsystems can be implemented using various expansion card formats, including PCI, PCIX (PCI Express), AGP
(Accelerated Graphics Port), and so on. Some or all of the components of a graphics processing subsystem may be mounted directly on a motherboard; for instance, one of the GPUs can be a motherboard-mounted graphics co-processor. Computer systems suitable for practicing the present invention may also include various other components, such as high-speed DMA
(direct memory access) chips, and a single system may implement multiple bus protocols (e.g., PCI and AGP buses may both be present) with appropriate components provided for interconnecting the buses. One or more command buffers may be implemented in the main system memory rather than graphics subsystem memory, and commands may include an additional parameter indicating which GPU(s) is (are) to receive or process the command.
While the present description may refer to asynchronous operation, those skilled in the art will recognize that the invention may also be implemented in systems where the CPU
communicates synchronously with the GPUs.
[0046] Embodiments of feedback data and load balancing techniques based on the feedback data will now be described. In one embodiment, each GPU 114a, 114b is assigned an identifier that it stores in a designated location in its local memory 116a, 116b; the identifier may also be stored in an on-chip register of each GPU 114a, 114b. For example, GPU 114a can be assigned an identifier "0" while GPU 114b is assigned an identifier "1." These identifiers, which advantageously have numerical values, may be assigned, e.g., at system startup or application startup. As described below, the identifier may be used as feedback data for purposes of load balancing.
[0047] Fig. 4 illustrates a process 400 for recording feedback data including the identifiers of the GPUs. At step 402, the graphics driver program creates a feedback array (referred to herein as feedback[O:B-1]) of dimension B (e.g., 5,10, 20, 50, etc.) in system main memory, and at step 404, a frame counter k is initialized (e.g., to zero). In this embodiment, the write notifier command following each frame k instructs the GPU to copy its identifier from its local memory to the location feedback[k] in system main memory, e.g., using a DMA block transfer operation ("Blit") or any other operation by which a GPU can write data to system main memory. Thus, at step 406, the first GPU to finish rendering frame k writes its identifier to the array location feedback[k]. At step 408, the second GPU to finish rendering the frame k writes its identifier to the array location feedback[k], overwriting the first GPU's identifier. It is to be understood that either GPU 114a, 114b might finish first, and that a GPU that is first to finish one frame first might be last to finish another frame.
(0048] It should be noted that in this embodiment each GPU is instructed to write to the same location in system memory; as a result, the second GPU to finish frame k overwrites the identifier of the first GPU in array element feedback[k]. Thus, after both GPUs have finished a particular frame k, the value stored in feedback[k] indicates which GPU was last to finish the frame k.
[004] At step 410, the frame counter is incremented to the next frame, modulo B. This causes the feedback array to be overwritten in a circular fashion every B
frames, so that the contents of the array generally reflect the last B frames that have been rendered. In one embodiment, the frame counter value for each frame is provided with the write notification command to each GPU; in another embodiment, each GPU maintains its own frame counter and updates the frame counter after writing the identifier to the appropriate location in system memory in response to the write notifier command.
[0050] The information in the feedback array can be used by a graphics driver program (or another program executing on CPU 102) for load balancing, as illustrated in Fig. 5. Process 500 is a shown as a continuous loop in which the relative load on the GPUs is estimated from time to time by averaging values stored in the feedback array and the load is adjusted based on the estimate. In this embodiment, there are two GPUs (e.g., GPUs 114a, 114b of Fig. 1) operating in spatial parallelism and the display area is divided as shown in Fig. 2. The GPU
assigned to the top portion 202 of the display area has identifier "0" and is referred to herein as GPU-0, and the GPU assigned to the bottom portion 204 has identifier "1"
and is referred to herein as GPU-1. Load balancing is done by adjusting the clip rectangle for each GPU, determined in this example by the location of the boundary line P in Fig. 2.
[0051) At step SO1, a clip rectangle command is issued (e.g., placed in the command stream) for each GPU. This initial clip rectangle command may partition the display area equally between the GPUs (e.g., using P = M/2) or unequally. For example, a developer of an application program may empirically determine a value of P that approximately balances that load and provide that value to the graphics driver program via an appropriate command.
The initial size of the portion of the display area allocated to each GPU is not critical, as the sizes will typically be changed from time to time to balance the load.
[0052) At step 502, the graphics driver determines whether it is time to balance the load between the GPUs. Various criteria may be used in this determination; for example, the graphics driver may balance the load after some number (Q) of frames, where Q
might be, e.g., 1, 2, 5, 10, 20, etc. Q advantageously does not exceed the number of entries B in the feedback array, but Q need not be equal to B. Alternatively, load balancing may be performed at regular time intervals (e.g., once per second) or according to any other criteria. .
If it is not time to balance the load, process 500 waits (step 504), then checks the load balancing criteria again at step 502.
[0053) When it is time to balance the load, the graphics driver averages Q
values from the feedback array at step 506, thereby computing a load coefficient. In one embodiment Q is equal to B (the length of the feedback array), but other values may be chosen.
It should be noted that the graphics driver and the GPUs may operate asynchronously with the CPU as described above, so that the graphics driver might not know whether the GPUs have finished a particular frame and the GPUs may be rendering a frame that is several frames earlier in the command stream than a current frame in the graphics driver. Where the feedback array is written in a circular fashion, as in process 400 described above, selecting Q
to be equal to B
provides an average over the B most recently rendered frames. In some embodiments, a weighted average may be used, e.g., giving a larger weight to more recently-rendered frames.

[0054] The load coefficient is used to determine whether an adjustment to the clip rectangles for the GPUs needs to be made. If the GPUs are equally loaded, the likelihood of either GPU finishing a frame first is about 50%, and the average value over a suitable number of frames (e.g., 20) will be about 0.5 if identifier values of 0 and 1 axe used. An average value in excess of 0.5 indicates that GPU-1 (which renders the bottom portion of the image) is more heavily loaded than GPU-0, and an average value below 0.5 indicates that GPU-0 (which renders the top portion of the image) is more heavily loaded than GPU-1.
[0055] Accordingly, at step S 10 it is determined whether the load coefficient exceeds a "high" threshold. The high threshold is preselected and may be exactly 0.5 or a somewhat higher value (e.g., 0.55 ox 0.6). If the load coefficient exceeds the high threshold, then the loads are adjusted at step 512 by moving the boundary line P in Fig. 2 down by a preset amount (e.g., one line, five lines, ten lines). This reduces the fraction of the display area that is rendered by GPU-1, which will tend to reduce the load on GPU-1 and increase the load on GPU-0. Otherwise, at step 514, it is determined whether the load coefficient is less than a "low" threshold. The low threshold is predefined and may be exactly 0.5 or a somewhat lower value (e.g., 0.45 or 0.4). If the load coe~cient is below the low threshold, then the loads are adjusted at step 516 by moving the boundary line P in Fig. 2 up by a preset amount (e.g., one line, five lines, ten lines). At step 518, if the load coefficient is neither above the high threshold nor below the low threshold, the load is considered balanced, and the boundary line P is left unchanged.
[0056] After the new boundary line P is determined, a new clip rectangle command is issued. for each GPU (step 522) and the process returns to step. 504 to wait until it is time to balance the load again. In an alternative embodiment, a new clip rectangle command is issued at step 522 only if the boundary line changes. In canjunction with the new clip rectangle command, a message may be sent to the scanout control logic so that the appropriate display buffer is selected to provide each line of pixel data (e.g., by modifying one or more scanout parameters related to selection of display buffers).
Changes in the parameters of the scanout control logic axe advantageously synchronized with rendering of the frame in which the new clip rectangle takes effect; accordingly, in some embodiments, the clip rectangle command may also update the scanout parameters in order to display the next rendered frame correctly.

[0057] In some embodirrients, when the boundary line is shifted to balance the load, it may be useful to transfer data from one display buffer to another. For example, in Fig. 2, suppose that just after GPUs 114a, 114b have finished rendering a current frame, the value of P is changed to a larger value P', increasing the number of lines that GPU 114a will render for the next frame. GPU 114a may need access to data for some or all of lines P+1 through P' of the current frame in order to correctly process the next frame. In one embodiment, GPU 114a can obtain the data by a DMA transfer from the portion of display buffer 122b that has the data for lines P+1 through P'. Examples of processes that can advantageously be used for this purpose are described in the above-referenced application No. (Attorney Docket No.
019680-006000US), although numerous other processes for transferring data may also be used. It is to be understood that transferring data between display buffers is not required but may be useful in embodiments where any overhead associated with the data transfer is outweighed by the overhead of having one GPU repeat computations previously performed by another GPU. Transferring data that is not displayed (e.g., texture data) between graphics memories 116a,116b may also be desirable in some instances and can be implemented using any of the techniques mentioned above.
[4058] It will be appreciated that the processes described herein are illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified or combined.
Optimal selection of the number of frames to average (Q) and/or the frequency of balancing generally depends on various tradeoffs. For instance, a small value of Q provides faster reactions to changes in the scene being rendered, while a larger value of Q will tend to produce more stable results (by minimizing the effect of fluctuations) as well as reducing any effect of an entry in the feedback array for a frame that only one GPU has finished (such an entry would not accurately reflect the last GPU to finish that frame). More frequent balancing may reduce GPU idle time, while less frequent balancing tends to reduce any overhead (such as data transfers between the memories of different GPUs) associated with changing clip rectangles.
In one embodiment, checking the balance every 20 frames with Q = B = 20 is effective, but in general, optimal values depend on various implementation details. It should be noted that checking the balance can occur quite frequently; e.g., if 30 frames are rendered per second and checking occurs every 20 frames, then the balance may change about every 0.67 seconds.
(0059] The identifiers fox different GPUs may have any value. Correspondingly, the high threshold and low threshold may have any values, and the two threshold values may be equal (e.g., both equal to 0.5), so long as the high threshold is not less than the low threshold. Both thresholds are advantageously set to values near or equal to the arithmetic mean of the two identifiers; an optimal selection of thresholds in a particular system may be affected by considerations such as the frequency of load rebalancing and any overhead associated with changing the clip rectangles assigned to each GPU. The threshold comparison is advantageously defined such that there is some condition for which the load is considered balanced (e.g., if the average is exactly equal to the arithmetic mean).
[0060] Prior to rendering images or writing any feedback data, the feedback array may be initialized, e.g., by randomly selecting either of the GPU identifiers for each entry or by filling alternating entries with different identifiers. Such initialization reduces the likelihood of a spurious imbalance being detected in the event that checking the load balance occurs before the GPUs have written values to all of the entries that are being used to determine the load coefficient.
[0061] In one alternative embodiment, the amount by which the partition changes (e.g., the number of lines by which the boundary line P is shifted) may depend on the magnitude of the difference between the load coefficient and the arithmetic mean. For example, if the load coefficient is greater than 0.5 but less than 0.6, a downward shift of four lines might be used, while for a load coefficient greater than 0.6, a shift of eight lines might be used; similar shifts in the opposite direction can be implemented for load coefficients below the arithmetic mean.
In some embodiments, the difference in size of the two clip rectangles is limited to ensure that each GPU is always rendering at least a minimum portion (e.g., 10% or 25%) of the display axea.
[0062] Instead of averaging, a load coefficient may be defined in other ways.
For instance, the sum of the recorded identifier values may be used as the load coefficient.
In the embodiment described above, with Q=20, the stored identifier values (0 or 1) would sum to 10 if the load is balanced; high and low thresholds may be set accordingly.
Other arithmetic operations that may be substituted for those described herein will also be apparent to those of ordinary skill in the art and are within the scope of the present invention.
[0063] In another alternative embodiment, different feedback data may be used instead of or in addition to the GPU identifiers described above. For example, instead of providing one feedback array in system memory, with both GPUs writing feedback data to the same location for a given frame, each GPU may write to a corresponding entry of a different feedback array, and the feedback data may include timing information, e.g., a timestamp indicating when each GPU finished a particular frame. In this embodiment, the graphics driver is configured to use the timing information to determine whether one GPU is consistently using more time per frame than another and adjust the clip rectangles accordingly to balance the load. It should be noted that, in some system implementations, timestamps might not accurately reflect the performance of the GPUs; in addition, deterniining relative loads from sequences of timestamps for each GPU
generally requires more computational steps than simply computing a load coefficient as described above.
Nevertheless, it is, to be understood that embodiments of the invention may include timing information in the feedback data instead of or in addition to GPU identifiers.
[0064] Multi-processor graphics processing systems may include more than two GPUs, and processes 400 and 500 may be adapted for use in such systems. For example, one embodiment of the present invention provides three GPUs, with each GPU being assigned a different horizontal band of the display area, as shown in Fig. 6. An M-line display area 600 is partitioned into a top portion 602 that includes lines 1 through K, a middle portion 604 that includes lines K+1 through L, and a bottom portion 606 that includes lines L+1 through M.
Data for top portion 602 is generated by a GPU 614a having an identifier value of "0"
(referred to, herein as GPU-0); data for middle portion 604 is generated by a GPU 614b having an identifier value of "1" (referred to herein as GPU-1); and data for bottom portion 606 is generated by a GPU 614c having an identifier value of "2" (referred to herein as GPU-2). Load balancing is achieved by adjusting the values of K and L.
[0065] More specifically, in one embodiment, the command stream for each GPU
is similar to that of Fig. 3, but two feedback arrays of dimension B (referred to herein as feedback0l [0:B-1] and feedbackl2[O:B-1]) are provided, as shown in Fig. 7. In response to the write notifier command 306, GPU-0 writes its identifier value to a location in the feedback0l array 702 (writing is indicated by arrows in Fig. 7), GPU-1 writes its identifier value to respective locations in both the feedback0l and feedbackl2 arrays 702, 704, and GPU-2 writes its identifier value to a location in the feedbackl2 array 704.
As a result, an average value of the feedback0l array reflects the relative loads on GPU-0 and GPU-1, while an average value of the feedbackl2 array reflects the relative loads on GPU-1 and GPU-2.
[0066] To balance the loads, the graphics driver adjusts the value of K based on a load coefficient determined from the feedback0l array, e.g., in accordance with process 500 of Fig. 5 described above (with balance occurring when the load coefFicient is 0.5), and adjusts the value of L based on a load coefficient determined from the feedbackl2 array, e.g., in accordance with process 500 (with balance occurring when the load coefficient is 1.5). While the relative loads of GPU-0 and GPU-2 are not directly compared, over time all three loads ~ will tend to become approximately equal. For example, if the load on GPU-1 exceeds the load on GPU-0, the average value of entries in the feedback0l array will exceed 0.5; as a result the value of K will be increased, thereby reducing the load on GPU-1 If the reduced load on GPU-1 becomes less than the load on GPU-2, this disparity will be reflected in the average value of entries in the feedback02 array, which will exceed 1.5; in response, the value of L will be increased, thereby increasing the load on GPU-1 again. This change may lead to a fiurther adjustment in the value of K, and so on. Those of skill in the art will appreciate that over time, this load-balancing process will tend to equalize all three loads.
Some instability may persist, but this is acceptable as long as any overhead associated with modifying the clip rectangles in response to new values of K andlor L is sufficiently small.
(0067] It will be appreciated that this load-balancing technique may be rurrher extended to systems with any number of GPUs. For instance, the display area can be divided into any number of horizontal bands, with each band being assigned to a different GPU.
Tn such embodiments, the number of feedback arrays is generally one less than the number of GPUs.
Alternatively, vertical bands may be used.
[0068] It should also be noted that the identifier of a particular GPU need not be unique across all GPUs, as long as the two GPUs that write to each feedback array have identifiers that are difFerent from each other. For example, in the embodiment shown in Fig. 6, GPUs 614a and 614c might both be assigned identifier "0." This would not create ambiguity because, as Fig. 7 shows, these GPUs do not write their identifiers to the same feedback array.
[0069] In another alternative embodiment, a combination of horizontal and vertical partitions of the display area may be used to assign portions of the display area to GPUs. For example, Fig. 8 shows a display area 800 consisting of M lines, each containing N pixels, that is divided into four sections 801-804. Sections 801-804 are rendered, respectively, by four GPUs 814a-8144 as indicated by arrows. Each GPU 814a-814d is assigned a different identifier value (0, l, 2, 3). In this embodiment, it may be assumed that complexity of an image is generally about equal between the left and right sides, in which case the vertical boundary line J may remain fixed (e.g., at J = Nl2). Two feedback arrays are provided;
GPU-0 (814a) and GPU-1 (814b) write their identifiers to a first feedback array feedback0l while GPU-2 (814c) and GPU-3 (814d) write their identifiers to a second feedback array feedback23. The boundary line K that divides sections 801 and 802 is adjusted based on the average value of entries in the feedback0l array, while the boundary line L
that divides sections 803 and 804 is adjusted based on the average value of entries in the feedback23 array.
[0070] In yet another alternative embodiment, the vertical boundary line J
might also be adjustable. For instance, GPU-0 and GPU-1 could each be assigned a secondary (column) identifier value of "0" while GPU-2 and GPU-3 are each assigned a secondary identifier with a value of "1." A third~feedback array feedbackC may be provided, with each GPU writing its secondary identifier to the feedbackC array in addition to writing its primary identifier to the appropriate one of the feedback0l and feedback23 arrays. The vertical boundary line J
can then be adjusted based on the average value of entries in the feedbackC
array.
Alternatively, the primary identifier (which has values 0-3) can be associated with the vertical division while the secondary identifier (which has values 0 and 1) is associated with the horizontal division.
[0071] The techniques described herein may also be employed in a "mufti-card"
graphics processing subsystem in which different GPUs reside on different expansion cards connected by a high-speed bus, such as a PCIX (64-bit PCI Express) bus or a 3GI4 (third-generation input/output) bus presently being developed. An example of a mufti-card system 900 is shown in Fig. 9. Two graphics cards 912x, 912b are interconnected by a high speed bus 908;
it is to be understood that any number of cards may be included and that high-speed bus 908 generally also connects to other elements of a computer system (e.g., various components of system 100 as shown in Fig. 1). Each graphics card has a respective GPU 914a, 914b and a respective graphics memory 916a, 916b that includes a display buffer 922a, 922b. Card 912a has scanout control logic 920 that provides pixel data from display buffer 922a to a display device 910. Card 912b may also include scanout control logic circuitry, but in this example, card 9I2b is not connected to a display device and any scanout control logic present in card 912b may be disabled.
[0072] In this arrangement, spatial parallelism can be implemented, with each GPU 914a, 914b rendering a portion of each frame to its display buffer 922a, 922b. In order to display the frame, pixel data from display buffer 922b is transferred (e.g., using a conventional block transfer, or Blit, operation) via bus 908 to display buffer 922a, from which it is read by scanout control logic 920.
[0073] Load balancing as described above can be implemented in this system and S advantageously takes into consideration time consumed by the data transfers.
For example, Fig. 10 shows respective command streams 1000a, 1000b for GPUs 914a, 914b, which are generally similar to command stream 300 of Fig. 3. Each command stream begins with a clip rectangle command {CR) 1002a, 1002b, followed by rendering commands 1004a, 1004b for a frame F0. As in the single-card embodiments described above, different clip rectangle boundaries are provided for each GPU 914a, 914b so that each renders a different portion of the frame; the rendering commands to each GPU may be identical or different as appropriate for a particular embodiment.
[0074] In this embodiment, pixel data from display buffer 922b is transferred to display buffer 922a prior to scanout. Accordingly, for GPU 914b, the rendering commands 1004b are followed by a Blit command 1006 that instructs GPU 914b to transfer pixel data from local display buffer 922b to display buffer 922a on card 912a so that it can be scanned out.
Since GPU 914a writes pixel data directly to display buffer 922a, a Blit command is not xequired in command stream 1000a, so the rendering commands 1004a for GPU 9I4a are followed by a "no-op" 1005. The no-op may be, e.g., a command that simply delays execution of a following command (such commands are known in the art), no command, or a command instructing GPU 914a to ignore a Blit command that appears in its command stream.
[0075] A write notifier command 1008a for frame FO follows the no-op command 1005 in command stream 1000a, and a corresponding write notifier. command 1008b follows Blit command 1006. The write notifier commands 1008a, 1008b may be implemented similarly to the write notifiex commands described above with reference to process 400 of Fig. 4. A
load balancing process such as process 500 of Fig. 5 may be used to balance the load.
[0076] It should be noted that the time required for the Blit operations is accounted for in the Ioad balancing process because the write notifier command 1008b for a frame FO is not executed by GPU 914b until after the Blit operation for the frame FO is executed. Thus, the rendering time for GPU 914a is balanced against the rendering time plus the Blit time for GPU 914b.
[0077] In some mufti-card embodiments used to render scenes in which foreground regions (most often but not always at the bottom of the display area) are consistently more complex than background regions, a performance advantage can be gained by assigning GPU 914a to process the background region of the scene and assigning GPU 914b to process the foreground region. For example, in Fig. 2, suppose that the foreground appears toward the bottom of display area 200. In that case, GPU 914a would be assigned to~render top region 202 while GPU 914b would be assigned to render bottom region 204. The higher complexity of the foreground (bottom) region tends to increase the rendering time of GPU
914b. In response, the load-balancing processes described herein will tend to move the boundary line P toward the bottom of the display area. This decreases the number of lines of data included in bottom region 204, which reduces the amount of data that needs to be transferred to J display buffer 922a.by the Blit command 1006. As a result, more of the processing capacity of GPU 914b may be used for computations rather than data transfers, resulting in a net eff ciency gain.
[0078] Those of ordinary skill in the art will recognize that a similar implementation might also be used in embodiments of a single-card mufti-processor system in which pixel data from all GPUs is transferred to a single display buffer prior to scanout. For example, in system 112 of Fig. 1, data from display buffer 122b might be transferred to display buffer 122a to be scanned out, so that scanout control logic 120 can simply access display buffer 122a to obtain all of the pixel data for a frame. In this embodiment, GPU 114b can be instructed to perform a Blit operation before the write notifier instruction, while GPU 114a is given a no-op.
(0079] While the invention has been described with respect to specific embodiments, one skilled in the art will recognize that numerous modifications are possible.
For instance, in a mufti-processor graphics processing system, any number of GPUs may be included on a graphics card, and any number of cards may be provided; e.g., a four-GPU
subsystem might be implemented using two cards with two GPUs each, or a three-GPU subsystem might include a first card with one GPU and a second card with two GPUs. One or more of the GPUs may be a motherboard-mounted graphics co-processor.
[0080] Rendering of a display frame may be divided among the GPUs in horizontal bands and/or vertical bands. Those of skill in the art will recognize that use of vertical bands may result in more uniform sizes of the regions rendered by different GPUs (since image complexity usually varies less from left to right than from top to bottom), while use of horizontal bands may simplify the scanout operation in a horizontal row-oriented display device (since only one GPU's display buffer would be accessed to read a particular row of pixels). In addition, a frame may be partitioned among the GPUs along both horizontal and vertical boundaries, and load balancing may be performed along either or both boundaries as described above.
[0081) Embodiments of the invention may be implemented using special-purpose hardware, software executing on general-purpose or special-purpose processors, or any combination thereof. The embodiments have been described in terms of functional blocks that might or might not correspond to separate integrated circuit devices in a particular implementation. Although the present disclosure may refer to a general-purpose computing system, those of ordinary skill in the art with access to the present disclosure will recognize that the invention may be employed in a variety of other embodiments, including special-purpose computing systems such as video game consoles or any other computing system that provides graphics processing capability with multiple graphics processors.
[0082] Computer programs embodying various features of the present invention may be encoded on computer-readable media for storage and/or transmission; suitable media include magnetic disk or tape, optical storage media such as compact disk (CD) or DVD
(digital video disk), flash memory, and carrier signals for transmission via wired, optical, and/or wireless networks conforming to a variety of protocols, including the Internet.
Computer-readable media encoded with the program code may be packaged with a compatible device such as a mufti-processor graphics card or provided separately from other devices (e.g., via Internet download).
[0083] Thus, although the invention has been described with respect to specific embodiments, it will be appreciated that the invention is intended to cover all modifications and equivalents within the scope of the following claims.

Claims (28)

1. A method for load balancing for a plurality of graphics processors configured to operate in parallel, the method comprising:
partitioning a display area into at least a first portion to be rendered by a first one of the plurality of graphics processors and a second portion to be rendered by a second one of the plurality of graphics processors;
instructing the plurality of graphics processors to render a frame, wherein the first and second graphics processors perform rendering for the first and second portions of the display area, respectively;
receiving feedback data for the frame from the first and second graphics processors, the feedback data. reflecting respective rendering times for the first and second graphics processors;
determining, based on the feedback data, whether an imbalance exists between respective loads of the first and second graphics processors; and in the event that an imbalance exists:
identifying, based on the feedback data, which of the firsthand second graphics processors is more heavily loaded; and re-partitioning the display area to increase a size of the one of the first and second portions of the display area that is rendered by the more heavily loaded one of the first and second graphics processors and to decrease a size of the other of the first and second portions of the display area.
2. The method of claim 1, wherein the first portion of the display area comprises a first number of contiguous lines of pixels and the second portion of the display area comprises a second number of contiguous lines of pixels.
3. The method of claim 2, wherein the act of re-partitioning the display area includes shifting a third number of contiguous lines of pixels from the first portion of the display area to the second portion of the display area, the third number being smaller than the first number.
4. The method of claim 2, wherein the lines of pixels are oriented horizontally.
5. The method of claim 2, wherein the lines of pixels are oriented vertically.
6. The method of claim 1, further comprising:
assigning a different processor identifier to each of the first and second graphics processors, wherein the feedback data received from each of the first and second graphics processors includes the respective processor identifier.
7. The method of claim 6, wherein each of the processor identifiers has a numerical value.
8. The method of claim 1, wherein the feedback data includes a timestamp.
9. The method of claim 1, wherein the feedback data includes data indicating which of the first and second graphics processors is last to finish rendering the frame.
10. The method of claim 9, wherein the feedback data from the one of the first and second graphics processors that is last to finish overwrites feedback data from the other of the first and second graphics processors.
11. The method of claim 9, wherein the act of receiving includes receiving the feedback data for each of a plurality of frames.
12. The method of claim 11, further comprising:
providing a plurality of storage locations, each storage location associated with a different one of the plurality of frames, wherein the act of receiving the feedback data for each of the plurality of frames includes:
instructing the first graphics processor to store a first processor identifier in the associated one of the storage locations for each of the plurality of frames after rendering the first portion of the display area for the frame; and instructing the second graphics processor to store a second processor identifier different from the first processor identifier in the associated one of the storage locations for each of the plurality of frames after rendering the second portion of the display area for the frame.
13. The method of claim 12, wherein the processor identifier of the one of the of the first and second graphics processors that was last to finish rendering the frame overwrites the processor identifier of the other of the first and second graphics processors in the storage location.
14. The method of claim 11, wherein the act of determining includes computing a load coefficient from the feedback data for the plurality of frames, the load coefficient indicating a frequency of one of the first and second graphics processors being last to finish.
15. The method of claim 14, wherein a numeric identifier is associated with each of the first and second graphics processors and the load coefficient is an average over the plurality of frames of the numeric identifier of the processor that was last to finish each frame.
16. The method of claim 15, wherein the act of determining further includes comparing the load coefficient to an arithmetic mean of the numeric identifiers.
17. The method of claim 15, wherein during the act of re-partitioning, an amount by which the size of the first portion of the display area is reduced depends at least in part on a magnitude of the difference between the load coefficient and the arithmetic mean.
18. The method of claim 1, further comprising:
generating a command stream for each of the first and second graphics processors, the command stream including a set of rendering commands for the frame; and inserting a write notifier command into a command stream for each of the first and second graphics processors following the set of rendering commands, wherein each of the first and second graphics processors responds to the write notifier command by transmitting the feedback'data to a storage location.
19. A graphics processing system comprising:
a graphics driver module; and a plurality of graphics processors configured to operate in parallel to render respective portions of a display area and to provide feedback data to the graphics driver module, the graphics drivel module being further configured to detect, based on the feedback data, an imbalance between respective loads of two of the plurality of graphics processors and, in response to detecting an imbalance, to decrease a size of a first portion of the display area that is rendered by a more heavily loaded one of the two graphics processors and to increase a size of a second portion of the display area that is rendered by the other one of the two graphics processors.
20. The graphics processing system of claim 19, further comprising a plurality of graphics memories, each graphics memory coupled to a respective one of the graphics processors and storing pixel data for the portion of the display area rendered by the graphics processor coupled thereto.
21. The graphics processing system of claim 20, further comprising scanout control logic coupled to the plurality of graphics memories and configured to read pixel data for the display area from the graphics memories.
22. The graphics processing system of claim 19, wherein the graphics driver module is further configured to generate a command stream for the plurality of graphics processors, the command stream including a set of rendering commands for a frame and an instruction to each of the two graphics processors to transmit feedback data indicating that the transmitting processor has executed the set of rendering commands.
23. The graphics processing system of claim 19, wherein the feedback data includes an indication of which of the two graphics processors was last to finish rendering a frame.
24. The graphics processing system of claim 23, wherein the feedback data includes a numeric identifier of the one of the two graphics processors that was last to finish and the graphics driver module is further configured to compute a load coefficient from the numeric identifiers over a plurality of frames.
25. The graphics processing system of claim 24, wherein the graphics driver module is further configured to detect an imbalance in the event that the load coefficient is greater than a high threshold or less than a low threshold.
26. The graphics processing system of claim 19, wherein each portion of the display area comprises a number of contiguous lines of pixels and wherein the two graphics processors are configured to render adjacent portions.
27. The graphics processing system of claim 26, wherein the graphics driver is further configured to decrease the size of the first portion and increase the size of the second portion by shifting a number of lines of pixels from the first portion to the second portion.
28
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Publication number Priority date Publication date Assignee Title
US9849372B2 (en) * 2012-09-28 2017-12-26 Sony Interactive Entertainment Inc. Method and apparatus for improving efficiency without increasing latency in emulation of a legacy application title
US7119808B2 (en) * 2003-07-15 2006-10-10 Alienware Labs Corp. Multiple parallel processor computer graphics system
US20080211816A1 (en) * 2003-07-15 2008-09-04 Alienware Labs. Corp. Multiple parallel processor computer graphics system
US7075541B2 (en) * 2003-08-18 2006-07-11 Nvidia Corporation Adaptive load balancing in a multi-processor graphics processing system
US8775997B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for testing and configuring semiconductor functional circuits
US8788996B2 (en) 2003-09-15 2014-07-22 Nvidia Corporation System and method for configuring semiconductor functional circuits
US8732644B1 (en) 2003-09-15 2014-05-20 Nvidia Corporation Micro electro mechanical switch system and method for testing and configuring semiconductor functional circuits
US7739479B2 (en) * 2003-10-02 2010-06-15 Nvidia Corporation Method for providing physics simulation data
US7895411B2 (en) * 2003-10-02 2011-02-22 Nvidia Corporation Physics processing unit
US20050086040A1 (en) * 2003-10-02 2005-04-21 Curtis Davis System incorporating physics processing unit
US7782325B2 (en) * 2003-10-22 2010-08-24 Alienware Labs Corporation Motherboard for supporting multiple graphics cards
US20090027383A1 (en) * 2003-11-19 2009-01-29 Lucid Information Technology, Ltd. Computing system parallelizing the operation of multiple graphics processing pipelines (GPPLs) and supporting depth-less based image recomposition
US7961194B2 (en) 2003-11-19 2011-06-14 Lucid Information Technology, Ltd. Method of controlling in real time the switching of modes of parallel operation of a multi-mode parallel graphics processing subsystem embodied within a host computing system
US20080074429A1 (en) * 2003-11-19 2008-03-27 Reuven Bakalash Multi-mode parallel graphics rendering system (MMPGRS) supporting real-time transition between multiple states of parallel rendering operation in response to the automatic detection of predetermined operating conditions
US20070291040A1 (en) * 2005-01-25 2007-12-20 Reuven Bakalash Multi-mode parallel graphics rendering system supporting dynamic profiling of graphics-based applications and automatic control of parallel modes of operation
US8085273B2 (en) 2003-11-19 2011-12-27 Lucid Information Technology, Ltd Multi-mode parallel graphics rendering system employing real-time automatic scene profiling and mode control
US8497865B2 (en) * 2006-12-31 2013-07-30 Lucid Information Technology, Ltd. Parallel graphics system employing multiple graphics processing pipelines with multiple graphics processing units (GPUS) and supporting an object division mode of parallel graphics processing using programmable pixel or vertex processing resources provided with the GPUS
US20080094403A1 (en) * 2003-11-19 2008-04-24 Reuven Bakalash Computing system capable of parallelizing the operation graphics processing units (GPUs) supported on a CPU/GPU fusion-architecture chip and one or more external graphics cards, employing a software-implemented multi-mode parallel graphics rendering subsystem
EP1687732A4 (en) * 2003-11-19 2008-11-19 Lucid Information Technology Ltd Method and system for multiple 3-d graphic pipeline over a pc bus
US20050134595A1 (en) * 2003-12-18 2005-06-23 Hung-Ming Lin Computer graphics display system
US8711161B1 (en) 2003-12-18 2014-04-29 Nvidia Corporation Functional component compensation reconfiguration system and method
US7421303B2 (en) * 2004-01-22 2008-09-02 Nvidia Corporation Parallel LCP solver and system incorporating same
US7526456B2 (en) 2004-01-22 2009-04-28 Nvidia Corporation Method of operation for parallel LCP solver
US8704837B2 (en) * 2004-04-16 2014-04-22 Apple Inc. High-level program interface for graphics operations
US8134561B2 (en) 2004-04-16 2012-03-13 Apple Inc. System for optimizing graphics operations
US8707317B2 (en) * 2004-04-30 2014-04-22 Microsoft Corporation Reserving a fixed amount of hardware resources of a multimedia console for system application and controlling the unreserved resources by the multimedia application
US20050251644A1 (en) * 2004-05-06 2005-11-10 Monier Maher Physics processing unit instruction set architecture
US20050270298A1 (en) * 2004-05-14 2005-12-08 Mercury Computer Systems, Inc. Daughter card approach to employing multiple graphics cards within a system
EP1601218A1 (en) * 2004-05-28 2005-11-30 Orange S.A. Method and system for improving mobile radio communications
CN100519275C (en) * 2004-08-24 2009-07-29 夏普株式会社 Display system
WO2006022228A1 (en) * 2004-08-24 2006-03-02 Sharp Kabushiki Kaisha Simulation apparatus, simulation program, and simulation method
US8723231B1 (en) 2004-09-15 2014-05-13 Nvidia Corporation Semiconductor die micro electro-mechanical switch management system and method
JP4405884B2 (en) * 2004-09-22 2010-01-27 キヤノン株式会社 Drawing processing circuit and image output control device
US8711156B1 (en) 2004-09-30 2014-04-29 Nvidia Corporation Method and system for remapping processing elements in a pipeline of a graphics processing unit
US7475001B2 (en) * 2004-11-08 2009-01-06 Nvidia Corporation Software package definition for PPU enabled system
US7620530B2 (en) * 2004-11-16 2009-11-17 Nvidia Corporation System with PPU/GPU architecture
US7598958B1 (en) * 2004-11-17 2009-10-06 Nvidia Corporation Multi-chip graphics processing unit apparatus, system, and method
US7633505B1 (en) 2004-11-17 2009-12-15 Nvidia Corporation Apparatus, system, and method for joint processing in graphics processing units
US7522167B1 (en) 2004-12-16 2009-04-21 Nvidia Corporation Coherence of displayed images for split-frame rendering in multi-processor graphics system
US20090096798A1 (en) * 2005-01-25 2009-04-16 Reuven Bakalash Graphics Processing and Display System Employing Multiple Graphics Cores on a Silicon Chip of Monolithic Construction
CN101849227A (en) * 2005-01-25 2010-09-29 透明信息技术有限公司 Graphics processing and display system employing multiple graphics cores on a silicon chip of monolithic construction
US8436851B2 (en) * 2005-02-04 2013-05-07 Hewlett-Packard Development Company, L.P. Systems and methods for rendering three-dimensional graphics in a multi-node rendering system
US7565279B2 (en) * 2005-03-07 2009-07-21 Nvidia Corporation Callbacks in asynchronous or parallel execution of a physics simulation
US20060227145A1 (en) * 2005-04-06 2006-10-12 Raymond Chow Graphics controller having a single display interface for two or more displays
US7305649B2 (en) * 2005-04-20 2007-12-04 Motorola, Inc. Automatic generation of a streaming processor circuit
US8021193B1 (en) 2005-04-25 2011-09-20 Nvidia Corporation Controlled impedance display adapter
US7616207B1 (en) * 2005-04-25 2009-11-10 Nvidia Corporation Graphics processing system including at least three bus devices
US20070070067A1 (en) * 2005-04-29 2007-03-29 Modviz, Inc. Scene splitting for perspective presentations
US7650266B2 (en) * 2005-05-09 2010-01-19 Nvidia Corporation Method of simulating deformable object using geometrically motivated model
JP4070778B2 (en) * 2005-05-13 2008-04-02 株式会社ソニー・コンピュータエンタテインメント Image processing system
US7793029B1 (en) 2005-05-17 2010-09-07 Nvidia Corporation Translation device apparatus for configuring printed circuit board connectors
US20060265485A1 (en) * 2005-05-17 2006-11-23 Chai Sek M Method and apparatus for controlling data transfer in a processing system
US8287451B2 (en) * 2005-05-19 2012-10-16 Industrial Technology Research Institute Flexible biomonitor with EMI shielding and module expansion
US8054314B2 (en) * 2005-05-27 2011-11-08 Ati Technologies, Inc. Applying non-homogeneous properties to multiple video processing units (VPUs)
US8681160B2 (en) * 2005-05-27 2014-03-25 Ati Technologies, Inc. Synchronizing multiple cards in multiple video processing unit (VPU) systems
US8212838B2 (en) 2005-05-27 2012-07-03 Ati Technologies, Inc. Antialiasing system and method
US7649537B2 (en) * 2005-05-27 2010-01-19 Ati Technologies, Inc. Dynamic load balancing in multiple video processing unit (VPU) systems
US7663635B2 (en) * 2005-05-27 2010-02-16 Ati Technologies, Inc. Multiple video processor unit (VPU) memory mapping
US20060271717A1 (en) * 2005-05-27 2006-11-30 Raja Koduri Frame synchronization in multiple video processing unit (VPU) systems
US7613346B2 (en) 2005-05-27 2009-11-03 Ati Technologies, Inc. Compositing in multiple video processing unit (VPU) systems
US7456833B1 (en) 2005-06-15 2008-11-25 Nvidia Corporation Graphical representation of load balancing and overlap
US20070038939A1 (en) * 2005-07-11 2007-02-15 Challen Richard F Display servers and systems and methods of graphical display
JP4327175B2 (en) * 2005-07-12 2009-09-09 株式会社ソニー・コンピュータエンタテインメント Multi-graphics processor system, graphic processor and drawing processing method
US20070059669A1 (en) * 2005-08-23 2007-03-15 Lockheed Martin Corporation Systems and methods for processing video images
US7603492B2 (en) * 2005-09-20 2009-10-13 Motorola, Inc. Automatic generation of streaming data interface circuit
TWI366151B (en) * 2005-10-14 2012-06-11 Via Tech Inc Multiple graphics processor system and methods
US20070085903A1 (en) * 2005-10-17 2007-04-19 Via Technologies, Inc. 3-d stereoscopic image display system
TWI348652B (en) * 2005-10-17 2011-09-11 Via Tech Inc Driver assisted asynchronous command processing
US7629978B1 (en) * 2005-10-31 2009-12-08 Nvidia Corporation Multichip rendering with state control
TWI322354B (en) * 2005-10-18 2010-03-21 Via Tech Inc Method and system for deferred command issuing in a computer system
US7817151B2 (en) * 2005-10-18 2010-10-19 Via Technologies, Inc. Hardware corrected software vertex shader
US8327388B2 (en) * 2005-12-07 2012-12-04 Nvidia Corporation Cloth application programmer interface
US8412872B1 (en) * 2005-12-12 2013-04-02 Nvidia Corporation Configurable GPU and method for graphics processing using a configurable GPU
US8417838B2 (en) 2005-12-12 2013-04-09 Nvidia Corporation System and method for configurable digital communication
US7656409B2 (en) * 2005-12-23 2010-02-02 Intel Corporation Graphics processing on a processor core
TWI309395B (en) * 2006-02-24 2009-05-01 Via Tech Inc Graphics system and graphics control method
JP4779756B2 (en) * 2006-03-29 2011-09-28 カシオ計算機株式会社 Server apparatus and server control program in computer system
US7535433B2 (en) * 2006-05-18 2009-05-19 Nvidia Corporation Dynamic multiple display configuration
US8035648B1 (en) * 2006-05-19 2011-10-11 Nvidia Corporation Runahead execution for graphics processing units
JP2008028852A (en) * 2006-07-24 2008-02-07 Felica Networks Inc Information processing terminal, data selection processing method, and program
US20080030510A1 (en) * 2006-08-02 2008-02-07 Xgi Technology Inc. Multi-GPU rendering system
ATE527610T1 (en) * 2006-08-23 2011-10-15 Hewlett Packard Development Co MULTIPLE SCREEN SIZE DISPLAY MACHINE
US9099050B1 (en) 2006-08-24 2015-08-04 Nvidia Corporation Method and apparatus for dynamically modifying the graphics capabilities of a mobile device
US8089481B2 (en) * 2006-09-28 2012-01-03 International Business Machines Corporation Updating frame divisions based on ray tracing image processing system performance
US7768516B1 (en) * 2006-10-16 2010-08-03 Adobe Systems Incorporated Image splitting to use multiple execution channels of a graphics processor to perform an operation on single-channel input
US9058792B1 (en) * 2006-11-01 2015-06-16 Nvidia Corporation Coalescing to avoid read-modify-write during compressed data operations
US20080120497A1 (en) * 2006-11-20 2008-05-22 Motorola, Inc. Automated configuration of a processing system using decoupled memory access and computation
KR100803220B1 (en) * 2006-11-20 2008-02-14 삼성전자주식회사 Method and apparatus for rendering of 3d graphics of multi-pipeline
JP4942179B2 (en) * 2006-12-11 2012-05-30 キヤノン株式会社 Print control apparatus, control method therefor, and device driver
US7969444B1 (en) * 2006-12-12 2011-06-28 Nvidia Corporation Distributed rendering of texture data
US8207972B2 (en) 2006-12-22 2012-06-26 Qualcomm Incorporated Quick pixel rendering processing
US7940261B2 (en) * 2007-01-10 2011-05-10 Qualcomm Incorporated Automatic load balancing of a 3D graphics pipeline
US20100020088A1 (en) * 2007-02-28 2010-01-28 Panasonic Corporation Graphics rendering device and graphics rendering method
US8205205B2 (en) * 2007-03-16 2012-06-19 Sap Ag Multi-objective allocation of computational jobs in client-server or hosting environments
JP5200396B2 (en) 2007-03-16 2013-06-05 株式会社リコー Image forming apparatus, image processing apparatus, control apparatus, and connection apparatus
JP4325697B2 (en) * 2007-04-17 2009-09-02 ソニー株式会社 Image processing system, image processing apparatus, image processing method, and program
US7627744B2 (en) * 2007-05-10 2009-12-01 Nvidia Corporation External memory accessing DMA request scheduling in IC of parallel processing engines according to completion notification queue occupancy level
US8306367B2 (en) * 2007-06-08 2012-11-06 Apple Inc. Method and apparatus for managing image-processing operations
US7969445B2 (en) * 2007-06-20 2011-06-28 Nvidia Corporation System, method, and computer program product for broadcasting write operations
KR101201026B1 (en) * 2007-06-27 2012-11-14 인터내셔널 비지네스 머신즈 코포레이션 System and method for providing a composite display
US8127300B2 (en) * 2007-08-28 2012-02-28 International Business Machines Corporation Hardware based dynamic load balancing of message passing interface tasks
US20090064166A1 (en) * 2007-08-28 2009-03-05 Arimilli Lakshminarayana B System and Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks
US8234652B2 (en) * 2007-08-28 2012-07-31 International Business Machines Corporation Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks
US8312464B2 (en) * 2007-08-28 2012-11-13 International Business Machines Corporation Hardware based dynamic load balancing of message passing interface tasks by modifying tasks
US8108876B2 (en) * 2007-08-28 2012-01-31 International Business Machines Corporation Modifying an operation of one or more processors executing message passing interface tasks
US8724483B2 (en) 2007-10-22 2014-05-13 Nvidia Corporation Loopback configuration for bi-directional interfaces
US8149247B1 (en) * 2007-11-06 2012-04-03 Nvidia Corporation Method and system for blending rendered images from multiple applications
US8922565B2 (en) * 2007-11-30 2014-12-30 Qualcomm Incorporated System and method for using a secondary processor in a graphics system
US8537166B1 (en) * 2007-12-06 2013-09-17 Nvidia Corporation System and method for rendering and displaying high-resolution images
US7995003B1 (en) * 2007-12-06 2011-08-09 Nvidia Corporation System and method for rendering and displaying high-resolution images
KR100980449B1 (en) 2007-12-17 2010-09-07 한국전자통신연구원 Method and system for rendering of parallel global illumination
US8711153B2 (en) * 2007-12-28 2014-04-29 Intel Corporation Methods and apparatuses for configuring and operating graphics processing units
KR100969322B1 (en) 2008-01-10 2010-07-09 엘지전자 주식회사 Data processing unit with multi-graphic controller and Method for processing data using the same
US9418171B2 (en) 2008-03-04 2016-08-16 Apple Inc. Acceleration of rendering of web-based content
US8477143B2 (en) 2008-03-04 2013-07-02 Apple Inc. Buffers for display acceleration
US8811499B2 (en) * 2008-04-10 2014-08-19 Imagine Communications Corp. Video multiviewer system permitting scrolling of multiple video windows and related methods
KR101473215B1 (en) 2008-04-18 2014-12-17 삼성전자주식회사 Apparatus for generating panorama image and method therof
US8933943B2 (en) * 2008-04-30 2015-01-13 Intel Corporation Technique for performing load balancing for parallel rendering
TWI363969B (en) * 2008-04-30 2012-05-11 Asustek Comp Inc A computer system with data accessing bridge circuit
JP5397782B2 (en) * 2008-05-08 2014-01-22 日本電気株式会社 Business process management apparatus, business process management method, and business process management program
US8056086B2 (en) * 2008-05-19 2011-11-08 International Business Machines Corporation Load balancing for image processing using multiple processors
US8711154B2 (en) * 2008-06-09 2014-04-29 Freescale Semiconductor, Inc. System and method for parallel video processing in multicore devices
US8199158B2 (en) 2008-06-11 2012-06-12 Intel Corporation Performance allocation method and apparatus
JP5067282B2 (en) * 2008-06-27 2012-11-07 ソニー株式会社 Object detection control device, object detection system, object detection control method, and program
GB2461900B (en) 2008-07-16 2012-11-07 Advanced Risc Mach Ltd Monitoring graphics processing
JP5280135B2 (en) * 2008-09-01 2013-09-04 株式会社日立製作所 Data transfer device
US10157492B1 (en) 2008-10-02 2018-12-18 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUS
US8395619B1 (en) * 2008-10-02 2013-03-12 Nvidia Corporation System and method for transferring pre-computed Z-values between GPUs
US8427474B1 (en) 2008-10-03 2013-04-23 Nvidia Corporation System and method for temporal load balancing across GPUs
US8228337B1 (en) * 2008-10-03 2012-07-24 Nvidia Corporation System and method for temporal load balancing across GPUs
TWI382348B (en) * 2008-10-24 2013-01-11 Univ Nat Taiwan Multi-core system and scheduling method thereof
US8456478B2 (en) * 2008-10-30 2013-06-04 Microchip Technology Incorporated Microcontroller with integrated graphical processing unit
US8531471B2 (en) * 2008-11-13 2013-09-10 Intel Corporation Shared virtual memory
US8751654B2 (en) * 2008-11-30 2014-06-10 Red Hat Israel, Ltd. Determining the graphic load of a virtual desktop
US9270783B2 (en) * 2008-12-06 2016-02-23 International Business Machines Corporation System and method for photorealistic imaging workload distribution
AU2008258132B2 (en) * 2008-12-15 2011-11-10 Canon Kabushiki Kaisha Load balancing in multiple processor rendering systems
KR101511273B1 (en) * 2008-12-29 2015-04-10 삼성전자주식회사 System and method for 3d graphic rendering based on multi-core processor
US8737475B2 (en) * 2009-02-02 2014-05-27 Freescale Semiconductor, Inc. Video scene change detection and encoding complexity reduction in a video encoder system having multiple processing devices
US8854379B2 (en) * 2009-02-25 2014-10-07 Empire Technology Development Llc Routing across multicore networks using real world or modeled data
US8843927B2 (en) * 2009-04-23 2014-09-23 Microsoft Corporation Monitoring and updating tasks arrival and completion statistics without data locking synchronization
US9479358B2 (en) * 2009-05-13 2016-10-25 International Business Machines Corporation Managing graphics load balancing strategies
US20100289804A1 (en) * 2009-05-13 2010-11-18 International Business Machines Corporation System, mechanism, and apparatus for a customizable and extensible distributed rendering api
US8122117B2 (en) * 2009-05-28 2012-02-21 Microsoft Corporation Determining an imbalance among computer-component usage
US9378062B2 (en) * 2009-06-18 2016-06-28 Microsoft Technology Licensing, Llc Interface between a resource manager and a scheduler in a process
US8719831B2 (en) * 2009-06-18 2014-05-06 Microsoft Corporation Dynamically change allocation of resources to schedulers based on feedback and policies from the schedulers and availability of the resources
US8484647B2 (en) 2009-07-24 2013-07-09 Apple Inc. Selectively adjusting CPU wait mode based on estimation of remaining work before task completion on GPU
US8963931B2 (en) * 2009-09-10 2015-02-24 Advanced Micro Devices, Inc. Tiling compaction in multi-processor systems
US9015440B2 (en) 2009-09-11 2015-04-21 Micron Technology, Inc. Autonomous memory subsystem architecture
US8698814B1 (en) * 2009-10-13 2014-04-15 Nvidia Corporation Programmable compute engine screen mapping
US9041719B2 (en) * 2009-12-03 2015-05-26 Nvidia Corporation Method and system for transparently directing graphics processing to a graphical processing unit (GPU) of a multi-GPU system
EP2513860B1 (en) * 2009-12-16 2018-08-01 Intel Corporation A graphics pipeline scheduling architecture utilizing performance counters
JP2011126210A (en) * 2009-12-18 2011-06-30 Canon Inc Printing data processor, print data processing method, and program
US9524138B2 (en) * 2009-12-29 2016-12-20 Nvidia Corporation Load balancing in a system with multi-graphics processors and multi-display systems
US20110212761A1 (en) * 2010-02-26 2011-09-01 Igt Gaming machine processor
US9331869B2 (en) 2010-03-04 2016-05-03 Nvidia Corporation Input/output request packet handling techniques by a device specific kernel mode driver
KR101641541B1 (en) * 2010-03-31 2016-07-22 삼성전자주식회사 Apparatus and method of dynamically distributing load in multi-core
US20110292057A1 (en) * 2010-05-26 2011-12-01 Advanced Micro Devices, Inc. Dynamic Bandwidth Determination and Processing Task Assignment for Video Data Processing
US9183560B2 (en) 2010-05-28 2015-11-10 Daniel H. Abelow Reality alternate
US8675002B1 (en) * 2010-06-09 2014-03-18 Ati Technologies, Ulc Efficient approach for a unified command buffer
JP5539051B2 (en) * 2010-06-14 2014-07-02 キヤノン株式会社 Rendering processor
JP2012003619A (en) * 2010-06-18 2012-01-05 Sony Corp Information processor, control method thereof and program
US8587596B2 (en) * 2010-06-28 2013-11-19 International Business Machines Corporation Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads
EP2596491B1 (en) 2010-07-19 2017-08-30 ATI Technologies ULC Displaying compressed supertile images
US9069622B2 (en) * 2010-09-30 2015-06-30 Microsoft Technology Licensing, Llc Techniques for load balancing GPU enabled virtual machines
US8970603B2 (en) 2010-09-30 2015-03-03 Microsoft Technology Licensing, Llc Dynamic virtual device failure recovery
US8736695B2 (en) 2010-11-12 2014-05-27 Qualcomm Incorporated Parallel image processing using multiple processors
US9524572B2 (en) * 2010-11-23 2016-12-20 Microsoft Technology Licensing, Llc Parallel processing of pixel data
US8830245B2 (en) * 2010-12-14 2014-09-09 Amazon Technologies, Inc. Load balancing between general purpose processors and graphics processors
JP5275402B2 (en) * 2011-04-20 2013-08-28 株式会社東芝 Information processing apparatus, video playback method, and video playback program
JP2012256223A (en) 2011-06-09 2012-12-27 Sony Corp Information processing device and information processing method
CN102270095A (en) * 2011-06-30 2011-12-07 威盛电子股份有限公司 Multiple display control method and system
DE102011108754A1 (en) * 2011-07-28 2013-01-31 Khs Gmbh inspection unit
KR20130019674A (en) * 2011-08-17 2013-02-27 삼성전자주식회사 Terminal and method for performing application thereof
CN102521209B (en) * 2011-12-12 2015-03-11 浪潮电子信息产业股份有限公司 Parallel multiprocessor computer design method
CN102546946B (en) * 2012-01-05 2014-04-23 中国联合网络通信集团有限公司 Method and device for processing task on mobile terminal
CN104011700B (en) 2012-02-14 2016-10-26 英派尔科技开发有限公司 Load balance in games system based on cloud
KR101947726B1 (en) * 2012-03-08 2019-02-13 삼성전자주식회사 Image processing apparatus and Method for processing image thereof
KR101834195B1 (en) * 2012-03-15 2018-04-13 삼성전자주식회사 System and Method for Balancing Load on Multi-core Architecture
US9875105B2 (en) 2012-05-03 2018-01-23 Nvidia Corporation Checkpointed buffer for re-entry from runahead
KR101399472B1 (en) * 2012-08-13 2014-06-27 (주)투비소프트 Method and apparatus for rendering processing by using multiple processings
KR101399473B1 (en) * 2012-08-13 2014-05-28 (주)투비소프트 Method and apparatus for rendering processing by using multiple processings
US10001996B2 (en) 2012-10-26 2018-06-19 Nvidia Corporation Selective poisoning of data during runahead
US9269120B2 (en) * 2012-11-06 2016-02-23 Intel Corporation Dynamically rebalancing graphics processor resources
GB2522355B (en) * 2012-11-06 2019-12-25 Intel Corp Dynamically rebalancing graphics processor resources
US9740553B2 (en) 2012-11-14 2017-08-22 Nvidia Corporation Managing potentially invalid results during runahead
US9632976B2 (en) 2012-12-07 2017-04-25 Nvidia Corporation Lazy runahead operation for a microprocessor
US9275601B2 (en) 2012-12-12 2016-03-01 Intel Corporation Techniques to control frame display rate
US9823931B2 (en) 2012-12-28 2017-11-21 Nvidia Corporation Queued instruction re-dispatch after runahead
EP2941726A1 (en) * 2013-01-07 2015-11-11 MAGMA Giessereitechnologie GmbH Method for simulating thermal radiation between surfaces
CN103077088B (en) * 2013-01-17 2016-01-13 浙江大学 Based on the dynamic feedback of load equalization methods of PKDT tree in Cluster Rendering environment
CN103984669A (en) * 2013-02-07 2014-08-13 辉达公司 System and method for image processing
US20140298246A1 (en) * 2013-03-29 2014-10-02 Lenovo (Singapore) Pte, Ltd. Automatic display partitioning based on user number and orientation
US9582280B2 (en) 2013-07-18 2017-02-28 Nvidia Corporation Branching to alternate code based on runahead determination
US9358467B2 (en) 2013-07-22 2016-06-07 Empire Technology Development Llc Game load management
JP6249692B2 (en) * 2013-09-06 2017-12-20 キヤノン株式会社 Image processing apparatus, control method thereof, and program
US8924596B1 (en) * 2013-12-06 2014-12-30 Concurrent Ventures, LLC System and method for dividing and synchronizing a processing task across multiple processing elements/processors in hardware
IN2013MU03836A (en) * 2013-12-06 2015-07-31 Tata Consultancy Services Ltd
AU2013273716A1 (en) 2013-12-19 2015-07-09 Canon Kabushiki Kaisha Method, apparatus and system for rendering an image
KR20150095144A (en) * 2014-02-12 2015-08-20 삼성전자주식회사 Method and apparatus for rendering graphics data and medium record of
US9275429B2 (en) * 2014-02-17 2016-03-01 Qualcomm Incorporated Device hang detection and recovery
US9417911B2 (en) * 2014-03-12 2016-08-16 Live Planet Llc Systems and methods for scalable asynchronous computing framework
EP3136719A4 (en) * 2014-04-24 2017-09-13 Sony Corporation Image processing apparatus and method and surgical operation system
US10346941B2 (en) * 2014-05-30 2019-07-09 Apple Inc. System and method for unified application programming interface and model
DK178380B1 (en) * 2014-07-01 2016-01-25 Magma Giessereitechnologie Gmbh Method of beam tracking for use in a simulation or calculation process
CN104133647A (en) * 2014-07-16 2014-11-05 三星半导体(中国)研究开发有限公司 Display driving equipment and display driving method for generating display interface of electronic terminal
US9898804B2 (en) * 2014-07-16 2018-02-20 Samsung Electronics Co., Ltd. Display driver apparatus and method of driving display
CN104123452B (en) * 2014-07-18 2017-10-10 西北工业大学 GPU load comprehensive evaluation methods based on fuzzy decision
KR102314110B1 (en) * 2014-09-16 2021-10-18 삼성디스플레이 주식회사 Touch display device comprising visual accelerator
GB2533284B (en) * 2014-12-11 2017-04-12 Imagination Tech Ltd Performing object detection
JP6513984B2 (en) * 2015-03-16 2019-05-15 株式会社スクウェア・エニックス PROGRAM, RECORDING MEDIUM, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD
US10445850B2 (en) * 2015-08-26 2019-10-15 Intel Corporation Technologies for offloading network packet processing to a GPU
GB2559042B (en) 2015-12-21 2019-06-05 Imagination Tech Ltd Allocation of tiles to processing engines in a graphics processing system
US9767770B2 (en) * 2015-12-28 2017-09-19 American Megatrends Inc. Computer system and method thereof for scalable data processing
US9817431B2 (en) * 2016-02-03 2017-11-14 Qualcomm Incorporated Frame based clock rate adjustment for processing unit
GB2547252B (en) * 2016-02-12 2019-12-11 Advanced Risc Mach Ltd Graphics processing systems
KR101797845B1 (en) * 2016-02-16 2017-11-14 가천대학교 산학협력단 Parallel video processing apparatus using multicore system and method thereof
US10261847B2 (en) * 2016-04-08 2019-04-16 Bitfusion.io, Inc. System and method for coordinating use of multiple coprocessors
EP3465605B1 (en) * 2016-05-27 2021-01-20 Analog Way S.A.S. A computer-implemented method for reducing video latency of a computer video processing system and computer program product thereto
US9990714B2 (en) 2016-09-07 2018-06-05 Simula Innovation As Apparatus and method for global optimization
US10084855B2 (en) 2017-01-23 2018-09-25 Akamai Technologies, Inc. Pixel-based load balancing
US10115223B2 (en) * 2017-04-01 2018-10-30 Intel Corporation Graphics apparatus including a parallelized macro-pipeline
US10147159B2 (en) * 2017-04-07 2018-12-04 Microsoft Technology Licensing, Llc Ink render using high priority queues
JP7013677B2 (en) * 2017-05-01 2022-02-01 ソニーグループ株式会社 Medical image processing device, operation method of medical image processing device, and endoscopic system
CN107423135B (en) * 2017-08-07 2020-05-12 上海兆芯集成电路有限公司 Equalizing device and equalizing method
GB2565770B (en) 2017-08-15 2019-09-18 Advanced Risc Mach Ltd Data processing systems
US10354356B2 (en) * 2017-11-02 2019-07-16 Dell Products L.P. Systems and methods for interconnecting and cooling multiple graphics processing unit (GPU) cards
JP2019128658A (en) * 2018-01-22 2019-08-01 ファナック株式会社 Numerical control device and numerical control system
TWI683253B (en) * 2018-04-02 2020-01-21 宏碁股份有限公司 Display system and display method
CN109395384A (en) * 2018-09-12 2019-03-01 Oppo广东移动通信有限公司 Game rendering method and Related product
WO2020105069A1 (en) * 2018-11-21 2020-05-28 Datalogic Ip Tech S.R.L. Image multiprocessing method for vision systems
TWI734072B (en) * 2019-01-25 2021-07-21 鴻齡科技股份有限公司 Gpu accelerated optimization method, device and computer storage medium
US11074666B2 (en) * 2019-01-30 2021-07-27 Sony Interactive Entertainment LLC Scalable game console CPU/GPU design for home console and cloud gaming
US11890538B2 (en) 2019-01-30 2024-02-06 Sony Interactive Entertainment LLC Scalable game console CPU / GPU design for home console and cloud gaming
CN109920040B (en) * 2019-03-01 2023-10-27 京东方科技集团股份有限公司 Display scene processing method and device and storage medium
JP7317630B2 (en) * 2019-08-14 2023-07-31 キヤノン株式会社 Image processing device, image processing method, and program
CN110532100B (en) * 2019-09-02 2022-04-15 Oppo广东移动通信有限公司 Method, device, terminal and storage medium for scheduling resources
US11321800B2 (en) * 2020-02-03 2022-05-03 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by region testing while rendering
CN115210748B (en) * 2020-02-03 2023-11-24 索尼互动娱乐股份有限公司 System and method for performing geometric figure high-efficiency multi-GPU rendering through region test during rendering
US11170461B2 (en) 2020-02-03 2021-11-09 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis while rendering
US11120522B2 (en) * 2020-02-03 2021-09-14 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by subdividing geometry
US11263718B2 (en) 2020-02-03 2022-03-01 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against in interleaved screen regions before rendering
US11508110B2 (en) 2020-02-03 2022-11-22 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
US11080814B1 (en) * 2020-02-03 2021-08-03 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using prior frame information
US11514549B2 (en) 2020-02-03 2022-11-29 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by generating information in one rendering phase for use in another rendering phase
CN115335866A (en) * 2020-02-03 2022-11-11 索尼互动娱乐股份有限公司 System and method for efficient multi-GPU rendering of geometry through geometry analysis at rendering
US20220035684A1 (en) * 2020-08-03 2022-02-03 Nvidia Corporation Dynamic load balancing of operations for real-time deep learning analytics
CN111988598B (en) * 2020-09-09 2022-06-21 江苏普旭科技股份有限公司 Visual image generation method based on far and near view layered rendering
US11604752B2 (en) 2021-01-29 2023-03-14 Arm Limited System for cross-routed communication between functional units of multiple processing units
CN114095655A (en) * 2021-11-17 2022-02-25 海信视像科技股份有限公司 Method and device for displaying streaming data
US20230289211A1 (en) 2022-03-10 2023-09-14 Nvidia Corporation Techniques for Scalable Load Balancing of Thread Groups in a Processor
US20230377242A1 (en) * 2022-05-23 2023-11-23 Rockwell Collins, Inc. A-buffer dynamic allocation
CN116954541B (en) * 2023-09-18 2024-02-09 广东保伦电子股份有限公司 Video cutting method and system for spliced screen

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717440A (en) * 1986-10-06 1998-02-10 Hitachi, Ltd. Graphic processing having apparatus for outputting FIFO vacant information
US5031089A (en) * 1988-12-30 1991-07-09 United States Of America As Represented By The Administrator, National Aeronautics And Space Administration Dynamic resource allocation scheme for distributed heterogeneous computer systems
JPH05324583A (en) 1992-05-26 1993-12-07 Dainippon Screen Mfg Co Ltd Image data processor
JP2780575B2 (en) * 1992-07-27 1998-07-30 松下電器産業株式会社 Parallel image generation device
US6469746B1 (en) * 1992-12-28 2002-10-22 Sanyo Electric Co., Ltd. Multi-vision screen adapter
US5719598A (en) * 1993-08-23 1998-02-17 Loral Aerospace Corporation Graphics processor for parallel processing a plurality of fields of view for multiple video displays
EP0693737A3 (en) * 1994-07-21 1997-01-08 Ibm Method and apparatus for managing multiprocessor graphical workload distribution
US6266072B1 (en) * 1995-04-05 2001-07-24 Hitachi, Ltd Graphics system
US5790130A (en) * 1995-06-08 1998-08-04 Hewlett-Packard Company Texel cache interrupt daemon for virtual memory management of texture maps
EP0789882B1 (en) * 1995-07-21 2000-10-04 Koninklijke Philips Electronics N.V. Multi-media processor architecture with high performance-density
JPH09153150A (en) * 1995-12-01 1997-06-10 Hitachi Ltd Parallel processing method
KR100269106B1 (en) * 1996-03-21 2000-11-01 윤종용 Multiprocessor graphics system
US6362818B1 (en) * 1998-01-07 2002-03-26 Evans & Sutherland Computer Corporation System and method for reducing the rendering load for high depth complexity scenes on a computer graphics display
DE19804470C1 (en) * 1998-02-05 1999-08-26 Leica Microsystems Microscope objective with correction mounting
US6078339A (en) * 1998-02-10 2000-06-20 Intel Corporation Mutual exclusion of drawing engine execution on a graphics device
US6300965B1 (en) * 1998-02-17 2001-10-09 Sun Microsystems, Inc. Visible-object determination for interactive visualization
US6023281A (en) 1998-03-02 2000-02-08 Ati Technologies, Inc. Method and apparatus for memory allocation
JP3224782B2 (en) * 1998-08-03 2001-11-05 インターナショナル・ビジネス・マシーンズ・コーポレーション Process sharing dynamic change method and computer
US6191800B1 (en) 1998-08-11 2001-02-20 International Business Machines Corporation Dynamic balancing of graphics workloads using a tiling strategy
US6317133B1 (en) * 1998-09-18 2001-11-13 Ati Technologies, Inc. Graphics processor with variable performance characteristics
US6259461B1 (en) * 1998-10-14 2001-07-10 Hewlett Packard Company System and method for accelerating the rendering of graphics in a multi-pass rendering environment
JP2000132349A (en) * 1998-10-21 2000-05-12 Fuji Xerox Co Ltd Plotting processor
JP2000222590A (en) * 1999-01-27 2000-08-11 Nec Corp Method and device for processing image
US6853381B1 (en) * 1999-09-16 2005-02-08 Ati International Srl Method and apparatus for a write behind raster
US6473086B1 (en) * 1999-12-09 2002-10-29 Ati International Srl Method and apparatus for graphics processing using parallel graphics processors
US6724390B1 (en) * 1999-12-29 2004-04-20 Intel Corporation Allocating memory
US6747654B1 (en) * 2000-04-20 2004-06-08 Ati International Srl Multiple device frame synchronization method and apparatus
US7047309B2 (en) * 2000-08-23 2006-05-16 International Business Machines Corporation Load balancing and dynamic control of multiple data streams in a network
JP2003115047A (en) * 2001-03-23 2003-04-18 Keisoku Giken Co Ltd Device for generating and displaying highly accurate image
US6683614B2 (en) 2001-12-21 2004-01-27 Hewlett-Packard Development Company, L.P. System and method for automatically configuring graphics pipelines by tracking a region of interest in a computer graphical display system
US6919896B2 (en) * 2002-03-11 2005-07-19 Sony Computer Entertainment Inc. System and method of optimizing graphics processing
US7594233B2 (en) * 2002-06-28 2009-09-22 Hewlett-Packard Development Company, L.P. Processing thread launching using volunteer information
US20040075623A1 (en) * 2002-10-17 2004-04-22 Microsoft Corporation Method and system for displaying images on multiple monitors
US6885376B2 (en) * 2002-12-30 2005-04-26 Silicon Graphics, Inc. System, method, and computer program product for near-real time load balancing across multiple rendering pipelines
US6985150B2 (en) * 2003-03-31 2006-01-10 Sun Microsystems, Inc. Accelerator control unit configured to manage multiple hardware contexts
US7119808B2 (en) * 2003-07-15 2006-10-10 Alienware Labs Corp. Multiple parallel processor computer graphics system
US7075541B2 (en) 2003-08-18 2006-07-11 Nvidia Corporation Adaptive load balancing in a multi-processor graphics processing system
US7782325B2 (en) * 2003-10-22 2010-08-24 Alienware Labs Corporation Motherboard for supporting multiple graphics cards

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