CA2649002A1 - A program verify method for otp memories - Google Patents
A program verify method for otp memories Download PDFInfo
- Publication number
- CA2649002A1 CA2649002A1 CA002649002A CA2649002A CA2649002A1 CA 2649002 A1 CA2649002 A1 CA 2649002A1 CA 002649002 A CA002649002 A CA 002649002A CA 2649002 A CA2649002 A CA 2649002A CA 2649002 A1 CA2649002 A1 CA 2649002A1
- Authority
- CA
- Canada
- Prior art keywords
- latch
- data
- logic level
- clock signal
- turning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract 22
- 230000015654 memory Effects 0.000 title claims abstract 8
- 230000000977 initiatory effect Effects 0.000 claims 3
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
Abstract
A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data. In a program operation, the master latch stores program data which is used for programming selected memory cells. In a program verify operation, the data programmed to the memory cells are read out and stored in the slave latches. In each data register stage, the logic states of both latches are compared to each other, and a status signal corresponding to a program pass condition is generated if opposite logic states are stored in both latches. The master latch in each stage is inverted if programming was successful, in order to prevent re-programming of that bit of data.
Claims (20)
1. A method for executing a program verify operation, comprising:
a) loading program data into a first latch of a register stage coupled to at least one bitline of a memory array;
b) programming a memory cell coupled to the at least one bitline;
c) reading the programmed data of the memory cell coupled to the at least one bitline into a second latch of the register stage;
d) comparing logic states stored in the first latch and the second latch; and e) providing a local status signal corresponding to a program pass condition if opposite data states are stored in the first latch and the second latch.
a) loading program data into a first latch of a register stage coupled to at least one bitline of a memory array;
b) programming a memory cell coupled to the at least one bitline;
c) reading the programmed data of the memory cell coupled to the at least one bitline into a second latch of the register stage;
d) comparing logic states stored in the first latch and the second latch; and e) providing a local status signal corresponding to a program pass condition if opposite data states are stored in the first latch and the second latch.
2. The method of claim 1, wherein the step of loading includes shifting the program data serially into the first latch, the first latch and the second latch being arranged in a master-slave flip-flop configuration.
3. The method of claim 1, wherein the step of loading includes providing the program data in parallel into the first latch, the first latch and the second latch being arranged in a master-slave flip-flop configuration.
4. The method of claim 2, wherein the first latch is coupled to one of the bitlines prior to the step of programming.
5. The method of claim 3, wherein the step of reading includes sensing the programmed data with a sense amplifier and providing sensed data to the second latch.
6. The method of claim 1, wherein the step of comparing includes providing a single bit output corresponding to the result of comparing.
7. The method of claim 6, wherein the step of comparing further includes combining the single output with a previous local status signal to provide the local status signal, the previous local status signal corresponding to a comparison result from a previous register stage.
8. The method of claim 7, further including inverting the program data stored in the first latch if the second latch stores a data state corresponding to a programmed memory cell.
9. The method of claim 8, wherein the step of comparing further includes comparing the data states of the first latch and another first latch in the previous register stage.
10. The method of claim 9, wherein the step of comparing the data states of the first latch and another first latch in the previous register stage includes providing another local status signal if the first latch and the another first latch have the same predetermined data state, the predetermined data state corresponding to the inverted program data.
11. A method for operating a register stage having a first latch and a second latch arranged in a master-slave flip-flop configuration for storing a first bit of data and a second bit of data respectively, comprising:
a. decoupling the first latch from a serial input terminal and decoupling the second latch from the first latch at substantially the same time while a source clock signal oscillates; and, b. initiating a shifting operation on either a high logic level of the source clock or a low logic level of the source clock for shifting one of the first bit of data and the second bit of data.
a. decoupling the first latch from a serial input terminal and decoupling the second latch from the first latch at substantially the same time while a source clock signal oscillates; and, b. initiating a shifting operation on either a high logic level of the source clock or a low logic level of the source clock for shifting one of the first bit of data and the second bit of data.
12. The method of claim 11, wherein the step of decoupling includes turning off a first gating device between the first latch and a serial input terminal and turning off a second gating device between the first latch and the second latch.
13. The method of claim 12, wherein turning off includes driving a first clock signal to an inactive logic level for turning off the first gating device, and driving a second clock signal to the inactive logic level for turning off the second gating device.
14. The method of claim 13, wherein the first clock signal and the second clock signal are driven to the inactive logic level by maintaining a shift enable signal at the inactive logic level while the source clock signal oscillates.
15. The method of claim 12, wherein the step of initiating includes turning on the first gating device while the second gating device is turned off for shifting the second bit of data.
16. The method of claim 15, wherein turning on the first gating device includes driving a first clock signal to an active logic level.
17. The method of claim 16, wherein the first clock signal is driven to the active logic level when a shift enable signal is enabled while the source clock signal is at a first logic level, the second clock signal being driven to an inactive logic level when the shift enable signal is enabled while an inverted source clock signal is at a second logic level.
18. The method of claim 17, wherein the step of initiating includes turning on the second gating device while the first gating device is turned off for shifting the first bit of data.
19. The method of claim 18, wherein turning on the second gating device includes driving the second clock signal to the active logic level.
20. The method of claim 19, wherein the second clock signal is driven to the active logic level when the shift enable signal is enabled while the source clock signal is at the second logic level, the first clock signal being driven to the inactive logic level when the shift enable signal is enabled while an inverted source clock signal is at the first logic level.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US87151906P | 2006-12-22 | 2006-12-22 | |
| US87157106P | 2006-12-22 | 2006-12-22 | |
| US60/871,519 | 2006-12-22 | ||
| US60/871,571 | 2006-12-22 | ||
| PCT/CA2007/002284 WO2008077237A1 (en) | 2006-12-22 | 2007-12-20 | A program verify method for otp memories |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2649002A1 true CA2649002A1 (en) | 2008-07-03 |
| CA2649002C CA2649002C (en) | 2010-04-20 |
Family
ID=39562051
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002645774A Active CA2645774C (en) | 2006-12-22 | 2007-12-20 | A power up detection system for a memory device |
| CA2649002A Active CA2649002C (en) | 2006-12-22 | 2007-12-20 | A program verify method for otp memories |
| CA2645781A Active CA2645781C (en) | 2006-12-22 | 2007-12-20 | Dual function data register |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002645774A Active CA2645774C (en) | 2006-12-22 | 2007-12-20 | A power up detection system for a memory device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2645781A Active CA2645781C (en) | 2006-12-22 | 2007-12-20 | Dual function data register |
Country Status (7)
| Country | Link |
|---|---|
| US (4) | US8082476B2 (en) |
| EP (2) | EP2122632B1 (en) |
| JP (3) | JP5457195B2 (en) |
| CA (3) | CA2645774C (en) |
| HK (1) | HK1205344A1 (en) |
| TW (1) | TWI509611B (en) |
| WO (3) | WO2008077237A1 (en) |
Families Citing this family (229)
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Also Published As
| Publication number | Publication date |
|---|---|
| EP2814037A1 (en) | 2014-12-17 |
| JP2010514082A (en) | 2010-04-30 |
| US8266483B2 (en) | 2012-09-11 |
| JP2014099239A (en) | 2014-05-29 |
| TW200836198A (en) | 2008-09-01 |
| EP2814037B1 (en) | 2016-10-26 |
| US8082476B2 (en) | 2011-12-20 |
| US20090290434A1 (en) | 2009-11-26 |
| US20110317804A1 (en) | 2011-12-29 |
| US8023338B2 (en) | 2011-09-20 |
| US7940595B2 (en) | 2011-05-10 |
| EP2122632B1 (en) | 2014-06-25 |
| JP5457195B2 (en) | 2014-04-02 |
| US20100002527A1 (en) | 2010-01-07 |
| WO2008077237A1 (en) | 2008-07-03 |
| CA2645774C (en) | 2010-01-12 |
| CA2645774A1 (en) | 2008-07-03 |
| CA2649002C (en) | 2010-04-20 |
| JP5671161B2 (en) | 2015-02-18 |
| JP5671162B2 (en) | 2015-02-18 |
| CA2645781C (en) | 2011-04-12 |
| EP2122632A4 (en) | 2010-01-27 |
| TWI509611B (en) | 2015-11-21 |
| WO2008077238A1 (en) | 2008-07-03 |
| US20100011266A1 (en) | 2010-01-14 |
| JP2014089796A (en) | 2014-05-15 |
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