CN100361095C - 具有内部高速缓存和/或内存访问预测的内存集线器 - Google Patents

具有内部高速缓存和/或内存访问预测的内存集线器 Download PDF

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CN100361095C
CN100361095C CNB038187590A CN03818759A CN100361095C CN 100361095 C CN100361095 C CN 100361095C CN B038187590 A CNB038187590 A CN B038187590A CN 03818759 A CN03818759 A CN 03818759A CN 100361095 C CN100361095 C CN 100361095C
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约瑟夫·杰德洛
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Micron Technology Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Abstract

一种计算机系统，包括用于将处理器(104)耦合到多个同步动态随机访问内存(“SDRAM”)设备的内存集线器(130)。内存集线器(130)包括耦合到处理器(104)的处理器接口(150)以及耦合到相应的SDRAM设备(140a-c)的多个内存接口(170a-c)。处理器接口(150)通过开关(160)耦合到内存接口(170a-c)。内存接口(170a-c)的每一个包括一个内存控制器(180)、一个高速缓存(184)和一个预测单元(190)。高速缓存(184)存储最近从相应的SDRAM设备(140a-c)读取的或者写入到相应的SDRAM设备(140a-c)的数据，使得其随后可以由处理器(104)以相当小的延迟读取。预测单元(190)基于以前被访问的地址，从可能的读取访问的地址预取数据。

Description

具有内部高速缓存和/或内存访问预测的内存集线器
技术领域
本发明涉及计算机系统，更特别地，涉及具有将多个内存设备连接到处理器或者其他内存访问设备的内存集线器的计算机系统。
背景技术
计算机系统使用内存设备，诸如动态随机访问存储器(“SDRAM”)设备，以存储由处理器访问的指令以及数据。在典型的计算机系统中，处理器通过处理器总线以及内存控制器与系统内存通信。处理器发出命令，例如读取命令，以及指定数据或者指令即将被读取的位置的地址。内存控制器使用该命令以及地址以生成应用到系统内存的适当的命令信号以及行和列地址。响应该命令以及地址，数据在系统内存以及处理器之间传递。内存控制器常常是系统控制器的一部分，其还包括用于连接处理器总线到诸如PCI总线这样的扩展总线的总线桥电路。
虽然内存设备的运算速度不断地增加，但是这个运算速度的增加没有跟上处理器运算速度的增加。而连接处理器到内存设备的内存控制器的运算速度增加得更慢。内存控制器和内存设备的相对低的速度限制了在处理器与内存设备之间的通信带宽。
除了在处理器与内存设备之间被限制的带宽外，计算机系统的性能还受到延迟问题的限制，该延迟问题增加从系统内存设备读取数据所需的时间。更具体地，当内存设备读取命令传递到诸如异步DRAM(“SDRAM”)这样的系统内存设备时，所读取的数据在几个时钟周期的延迟之后才从SDRAM中输出。因此，虽然SDRAM可以以高数据速率同步输出突发数据，但是最初提供数据的延时可以显著地降低使用这样的SDRAM设备的计算机系统的运算速度。
缓解内存延迟问题的一个途径是使用多个通过内存集线器连接到处理器的内存设备。由于当另一内存设备响应先前的内存访问时处理器可以访问一个内存设备，所以使用该结构的计算机系统可以具有更高的带宽。例如，处理器可以输出写数据到系统中的内存设备之一，同时系统中的另一内存设备准备提供读数据到处理器。但是，虽然使用内存集线器的计算机系统可以提供较高的性能，但是它们仍常常未能以最优速度进行工作。这样的计算机系统的未能以最优速度进行工作的原因之一是常规的内存集线器本质上是单通道系统，因为所有控制、地址以及数据信号必须通过共同的内存集线器电路。结果，当内存集线器电路忙于与一个内存设备通信时，它不能与另一内存设备通信。此外，虽然使用内存集线器的计算机系统可以提供更大的内存带宽，但是它们仍然遭受上述类型的延迟问题。更具体地，虽然当另一内存设备正在准备传输数据时处理器可以与一内存设备通信，但是在可以使用来自该另一内存设备的数据之前有时必须接收来自该一内存设备的数据。如果在可以使用来自该另一内存设备的数据之前必须从该一内存设备接收数据，则延迟问题继续降低这样的计算机系统的运算速度。
因此，需要一种计算机结构，其可以提供内存集线器结构的优点，而且最小化在这样的系统中共有的延迟问题，从而提供具有高带宽和低延迟的内存设备。
发明内容
一种可以在计算机系统中使用的内存集线器，包括与处理器或者其他内存访问设备相耦合的内存访问设备接口，以及多个内存接口，其每个内存接口耦合到相应的内存设备。每个内存接口包括一个内存控制器以及，根据本发明的一个方面，一个高速缓存。每个内存接口通过开关耦合到内存访问设备。在运算中，将从耦合到内存接口之一的内存设备读取的或写入到其上的数据存储在该内存接口的高速缓存中。响应随后的内存读取的请求，检查该高速缓存以确定对应于该内存读取请求的数据是否存储在该高速缓存中。若高速缓存命中，则所请求的数据从该高速缓存中提供。否则，所请求的数据由内存设备提供。根据本发明的另一方面，每个内存接口包括一个内存控制器以及一个预测单元。该预测单元基于先前的内存访问的地址，预测数据可能被读取的地址。该预测单元然后使在相应的内存接口中的内存控制器从该预测的地址读取数据。可以将内存集线器物理地包括在系统控制器、内存模块、或者计算机系统或其他使用内存设备的电子系统的一些其他部件中。
附图说明
图1为根据本发明的一个实施例的计算机系统的模块图，其中内存集线器包括在系统控制器中。
图2为根据本发明的另一个实施例的计算机系统的模块图，其中内存集线器包括在内存模块中。
图3为在图1和2的计算机系统中使用的内存集线器的模块图。
具体实施方式
在图1中示出了根据本发明的一个实施例的计算机系统100。该计算机系统100包括处理器104，用于实现例如执行特定的程序以实现特定的计算或者任务的各种处理功能。该处理器104包括处理器总线108，其通常包括地址总线、控制总线以及数据总线。此外，计算机系统100包括一个或多个诸如键盘或鼠标这样的输入装置108，该输入装置通过系统控制器110耦合到处理器104，以允许操作者与计算机系统100进行交互。典型地，计算机系统100还包括一个或多个输出装置114，该输出装置通过系统控制器110连接到处理器104，这样的输出装置典型地为打印机或者视频终端。一个或多个数据存储设备120典型地也通过系统控制器110与处理器104相耦合，以允许处理器104存储数据或者从内部或外部存储媒介(未示出)中检索数据。典型的存储设备120的例子包括硬盘与软盘、盒式磁带以及光盘只读存储器(CD-ROMs)。处理器104典型地也与高速缓存124相耦合，其通常为静态随机访问存储器(“SRAM”)。
系统控制器110还包括内存集线器130，用于控制对多个系统内存设备140a-d的访问，每个系统内存设备可以是同步动态随机访问存储器(“SDRAM”)。内存集线器130允许处理器104写入数据到每个系统内存设备140a-d以及从每个系统内存设备140a-d中读取数据。内存集线器130通过总线系统142耦合到每个系统内存设备140a-d，该总线系统通常包括控制总线、地址总线以及数据总线。
虽然内存集线器130在图1中显示为与处理器104相耦合，但是应当理解，如本领域所公知的，该内存集线器130还可以与在计算机系统芯片(未示出)中的其他部件相耦合，并且也可以允许其他设备(未示出)以直接内存操作方式写入数据到系统内存设备140a-d或者从系统内存设备140a-d中读取数据。同样，内存集线器130可以物理地被包括作为不同于系统控制器110的电子系统的部件的一部分。例如，如图2所示的计算机系统144使用在图1的计算机系统100中使用的大部分相同的部件。为简单起见，这样共同的部件设置相同的参考数字，并且不再重复它们的操作说明。计算机系统144与在图1中显示的计算机系统100的不同之处在于内存集线器130没有包括在系统控制器110中。作为替代，系统控制器110与多个内存模块146连接，例如双面引脚内存模块(“DIMMs”)。每个内存模块146包括内存集线器130以及多个内存设备148，该内存设备可以是SDRAM或者一些其他类型的内存设备。内存集线器130本质上以与上面参考图1解释的相同方式工作，以高速缓存存储在内存模块146中的数据。
虽然图1和图2分别显示包括在系统控制器110和内存模块146中的内存集线器130，但是应当理解，内存集线器130可以为独立单元，或者可以包括在计算机系统的其他部件或者使用内存设备的其他系统中。
内存集线器130的一个实施例如图3所示，其中内存集线器与处理器104以及三个内存设备140a-c相耦合，在图3中所举例说明的例子中，该三个内存设备是SDRAM设备。内存集线器130显示为以点对点排列的方式与处理器104相耦合，其中没有其他设备与在处理器104与内存集线器130之间的连接相耦合。这种类型的互连由于多个原因提供了在处理器104与内存集线器130之间的更好的信号耦合，包括相对低的电容、相对少的用于反射信号的线路中断以及相对短的信号路径。但是，也可以使用多点互连，在其中其他设备(未示出)与处理器104与内存集线器130之间的互连相耦合。
如本领域所公知的，内存集线器130包括处理器接口150，其通过多个总线和信号线与处理器104相耦合。处理器接口150通过包括写数据总线154和读数据总线156的多个总线以及信号线依次与开关160相耦合，虽然也可以设置单个双向数据总线用于在处理器端口150与开关160之间双向传递数据。处理器端口150还通过请求线164以及检测线(snoop line)168与开关160相耦合。如下面所非常详细描述的，通过检测线168从开关160传递到处理器端口150的检测信号用于保持高速缓存的一致性。通过请求线164从处理器接口150传递到开关160的请求信号，给开关160提供与通过开关160发送数据的请求相对应的信息。但是应当理解，处理器接口150可以是用更多或更少数量的总线和信号线或者不同于图3举例说明的总线和信号线与开关160相耦合。
开关160还与三个内存接口170a-c相耦合，该三个内存接口依次分别与系统内存设备140a-c相耦合。通过分别为每个系统内存设备140a-c提供分开并且独立的内存接口170a-c，内存集线器130避免典型地发生在单通道内存结构中的总线或内存组冲突。开关160通过包括写数据总线174、读数据总线176和请求线178的多个总线以及信号线与每个内存接口相耦合。但是，单个双向数据总线也可以用来替代分开的写数据总线174以及读数据总线176。值得注意的是，每个内存接口170a-c专门地适配其要连接的系统内存设备140a-c。更具体地，每个内存接口170a-c专门地适配以提供和接收特定的信号，该信号分别由其要连接的系统内存设备140a-c接收和产生。同样，内存接口170a-c能够与工作在不同时钟频率的系统内存设备140a-c一起工作。结果，内存接口170a-c把处理器104与变化隔离开来，并且提供更加受控制的内存设备140a-c可以交互的环境，所述变化发生于在内存集线器130与耦合到内存集线器130的内存设备140a-c之间的接口上。
将处理器接口150耦合到内存接口170a-c的开关160可以为任何各种常规的或在下文中描述的开关。例如，开关160可以是交叉(cross-bar)开关，其可以在处理器接口150和内存接口170a-c之间同时相互耦合。开关160也可以为一组多路复用器，其不提供与交叉开关相同级别的连通性，但是仍然可以将处理器接口150耦合到每个内存接口170a-c。开关160也可以包括仲裁逻辑(未示出)以确定哪个内存访问应该优于其他内存访问。实现该功能的总线仲裁对本领域技术人员是公知的。
进一步参考图3，每个内存接口170a-c包括各自的内存控制器180以及各自的高速缓存单元184。内存控制器180通过提供控制、地址以及数据信号给其耦合的系统内存设备140a-c以及从其耦合的系统内存设备140a-c接收数据信号，实现与传统内存控制器相同的功能。如本领域所公知的，高速缓存单元184包括包含有标签内存、数据内存和比较器的高速缓存的常规部分。在高速缓存184中使用的内存设备可以为DRAM设备、静态随机访问存储器(“SRAM”)、其他类型的内存设备，或者这三者的组合。此外，在高速缓存单元184中使用的任何或所有这些内存设备以及其他部件可以是嵌入的或独立的设备。
在每个内存接口170a-c中使用高速缓存单元184，允许处理器104在数据最近被从内存设备140a-c读取或者被写入到内存设备140a-c的情况下，不用等待内存设备140a-c提供该数据就能接收响应发送给相应系统内存设备140a-c的读取命令的该数据。高速缓存单元因此减少系统内存设备140a-c的读取延迟，以最大化计算机系统的内存带宽。类似地，处理器104可以在高速缓存单元184中存储写入数据，然后当在相同的内存接口170a-c中的内存控制器180从高速缓存单元184传递该写入数据到其耦合的系统内存设备140a-c时，执行其他功能。
为了进一步减少由内存集线器130导致的内存访问延迟，每个内存接口170a-c可以设置有预取单元190。该预取单元190能够使用常规算法预测后续内存读请求的可能地址。然后，在处理器104正在访问不同的系统内存设备140或者执行其他功能的同时，在相同内存接口170a-c中的内存控制器180可以在后台执行内存访问。当处理器104随后提供命令给内存集线器130以从预测的地址读取数据时，该读取数据已经存在高速缓存单元180中，因而可以快速地提供给处理器104。
由前述可知，虽然在此为了举例说明的目的已经描述了本发明的特定的实施例，但是在不背离本发明的精神和范围的情况下可以有不同的变型。因此，本发明由权利要求书来限定。

Claims (38)

1、一种内存集线器，包括：
一个内存访问设备接口，配置成与内存访问设备连接；
多个内存接口，配置成与相应的内存设备连接，该多个内存接口的每一个包括一个内存控制器和一个高速缓存；以及
一个开关，使该内存访问设备接口与该多个内存接口的每一个相耦合。
2、根据权利要求1所述的内存集线器，其中，所述内存访问设备接口包括一个处理器接口，配置成与处理器相连接。
3、根据权利要求1所述的内存集线器，其中，所述多个内存接口的每一个进一步包括一个预测单元，配置成基于先前的内存访问的地址预测数据可能被读取的地址，并使在相应的内存接口中的所述内存控制器输出指示从该预测的地址进行内存读取操作的信号。
4、根据权利要求3所述的内存集线器，其中，所述预测单元进一步配置成使所述内存接口在所述高速缓存中存储响应所述指示内存读取操作的信号而接收的读取数据。
5、根据权利要求1所述的内存集线器，其中，所述多个内存接口的每一个以相同的时钟速度工作。
6、根据权利要求1所述的内存集线器，其中，所述开关包括交叉开关。
7、根据权利要求1所述的内存集线器，其中，所述开关包括多路复用器开关。
8、根据权利要求1所述的内存集线器，其中，所述高速缓存包括动态随机存取存储器。
9、一种内存集线器，包括：
一个内存访问设备接口，配置成与内存访问设备相连接；
多个内存接口，配置成与相应的内存设备相连接，该多个内存接口的每一个包括一个内存控制器以及一个预测单元，该预测单元配置成基于先前的内存访问的地址预测数据可能被读取的地址，并且使在相应的内存接口中的该内存控制器输出指示从该预测的地址进行内存读取操作的信号；以及
一个开关，使该内存访问设备接口与该多个内存接口相耦合。
10、根据权利要求9所述的内存集线器，其中，所述内存访问设备接口包括处理器接口。
11、根据权利要求9所述的内存集线器，其中，所述多个内存接口的每一个以相同时钟速度工作。
12、根据权利要求9所述的内存集线器，其中，所述开关包括交叉开关。
13、根据权利要求9所述的内存集线器，其中，所述开关包括多路复用器开关。
14、一种计算机系统，包括：
一个处理单元，可用于执行计算功能；
一个系统控制器，与该处理单元相耦合；
至少一个输入装置，通过该系统控制器与该处理单元相耦合；
至少一个输出装置，通过该系统控制器与该处理单元相耦合；
至少一个数据存储设备，通过该系统控制器与该处理单元相耦合；
多个内存设备；以及
一个内存集线器，包括：
一个处理器接口，与该处理器相耦合；
多个内存接口，与该多个内存设备中的相应内存设备相耦合，该多个内存接口的每一个包括一个内存控制器以及一个高速缓存；以及
一个开关，使该处理器接口与该多个内存接口的每一个相耦合。
15、根据权利要求14所述的计算机系统，其中，所述内存集线器物理地包括在所述系统控制器中。
16、根据权利要求14所述的计算机系统，其中，所述多个内存设备物理地封装在一个内存模块中，并且其中所述内存集线器物理地包括在该内存模块中。
17、根据权利要求14所述的计算机系统，其中，所述多个内存接口的每一个进一步包括一个预测单元，配置成基于先前的内存访问的地址预测数据可能被读取的地址，并且使在相应的内存接口中的所述内存控制器将指示从该预测地址进行内存读取操作的输出信号应用到该内存接口所连接的内存设备。
18、根据权利要求17所述的计算机系统，其中，所述预测单元进一步配置成使所述内存接口在所述高速缓存中存储响应所述指示内存读取操作的信号从相应的内存设备中接收的读取数据。
19、根据权利要求14所述的计算机系统，其中，所述多个内存接口的每一个以相同的时钟速度工作。
20、根据权利要求14所述的计算机系统，其中，所述开关包括交叉开关。
21、根据权利要求14所述的计算机系统，其中，所述开关包括多路复用器开关。
22、根据权利要求14所述的计算机系统，其中，所述高速缓存包括动态随机存取存储器。
23、根据权利要求14所述的计算机系统，其中，所述多个内存设备的每一个包括动态随机存取存储设备。
24、根据权利要求23所述的计算机系统，其中，所述动态随机存取存储设备的每一个包括同步动态随机存取存储设备。
25、一种计算机系统，包括：
一个处理单元，可用于执行计算功能；
一个系统控制器，与该处理单元相耦合；
至少一个输入装置，通过该系统控制器与该处理单元相耦合；
至少一个输出装置，通过该系统控制器与该处理单元相耦合；
至少一个数据存储设备，通过该系统控制器与该处理单元相耦合；
多个内存设备；以及
一个内存集线器，包括：
一个处理器接口，与该处理器相耦合；
多个内存接口，与该多个内存设备的相应内存设备相耦合，该多个内存接口的每一个包括一个内存控制器以及一个预测单元，该预测单元配置成基于先前的内存访问的地址预测数据可能被读取的地址，并且使在相应的内存接口中的该内存控制器输出指示从该预测的地址进行内存读取操作的信号到该内存接口所耦合的内存设备；以及
一个开关，使该处理器接口与该多个内存接口的每一个相耦合。
26、根据权利要求25所述的计算机系统，其中，所述内存集线器物理地包括在所述系统控制器中。
27、根据权利要求25所述的计算机系统，其中，所述多个内存设备物理地封装在一个内存模块中，并且其中所述内存集线器物理地包括在该内存模块中。
28、根据权利要求25所述的计算机系统，其中，所述多个内存接口的每一个以相同的时钟速度工作。
29、根据权利要求25所述的计算机系统，其中，所述开关包括交叉开关。
30、根据权利要求25所述的计算机系统，其中，所述开关包括多路复用器开关。
31、根据权利要求25所述的计算机系统，其中，所述多个内存设备的每一个包括动态随机存取存储设备。
32、一种访问多个内存设备的方法，包括：
将一个内存访问请求送到与内存集线器相耦合的多个内存设备中的第一内存设备，所述多个内存设备中的每个内存设备具有其专用的高速缓存；
将从该第一内存设备读取的或者写入到该第一内存设备的数据存储在该第一内存设备专用的所述高速缓存中；
随后将一个内存读取请求送到该第一内存设备；
响应该内存读取请求，检测对应于该内存读取请求的数据是否存储在所述第一内存设备专用的该高速缓存中；
如果确定对应于该内存读取请求的数据存储在所述第一内存设备专用的该高速缓存中，则从该高速缓存提供该读取数据；以及
如果确定对应于该内存读取请求的数据不存储在所述第一内存设备专用的该高速缓存中，则从该第一内存设备提供读取数据。
33、根据权利要求32所述的方法，进一步包括：
基于对所述第一内存设备的先前的内存访问的地址，预测可能从所述第一内存设备读取的数据的地址；
从在所述第一内存设备中的该预测地址提供读取数据；以及
将来自该预测地址的读取数据存储在所述第一内存设备专用的所述高速缓存中。
34、根据权利要求33所述的方法，其中，预测基于的所述内存访问请求包括读内存访问。
35、根据权利要求33所述的方法，其中，预测基于的所述内存访问请求包括写内存访问。
36、一种访问多个内存设备的方法，包括：
将若干内存访问请求送到在与内存集线器相耦合的多个内存设备中的若于个相应地址，所述多个内存设备中的每个内存设备具有与之关联的高速缓存；
在该内存集线器中，基于该内存访问请求被送到的地址，预测可能将要从第一内存设备读取的数据的至少一个地址；在接收被送到所述预测地址的内存读取请求之前，从所述至少一个地址读取数据字并且将该数据字存储在与对应于所述至少一个地址的所述内存设备相关联的所述高速缓存中。
37、根据权利要求36所述的方法，其中，所述预测所基于的所述内存访问请求包括读内存请求。
38、根据权利要求36所述的方法，其中，所述预测所基于的所述内存访问请求包括写内存请求。
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