CN100365760C - 半导体器件的制作方法，半导体器件以及电子产品 - Google Patents

半导体器件的制作方法，半导体器件以及电子产品 Download PDF

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CN100365760C
CN100365760C CNB2003101206855A CN200310120685A CN100365760C CN 100365760 C CN100365760 C CN 100365760C CN B2003101206855 A CNB2003101206855 A CN B2003101206855A CN 200310120685 A CN200310120685 A CN 200310120685A CN 100365760 C CN100365760 C CN 100365760C
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substrate
semiconductor
laser
film
semiconductor film
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CN1508844A (zh
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山崎舜平
高山彻
丸山纯矢
大野由美子
田中幸一郎
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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Abstract

本发明的目的是在不实施造成裂缝以及研磨痕迹的背面研磨处理的情况下，提供一种封装以及其制作方法，该封装可以使芯片飞跃性地变薄，而且可以制作出低成本并且高产量的芯片，还可以抑制芯片厚度的不均匀。本发明用连续振荡的激光晶化形成在作为支撑物发挥作用的衬底上的膜的厚度等于或少于500nm的半导体薄膜，然后用该晶化过的半导体膜形成芯片，该芯片具有总膜厚为5μm，优选等于或少于2μm的薄膜的半导体元件。并且，在最后衬底被剥离的状态下，该芯片被安装到内插板。

Description

半导体器件的制作方法，半导体器件以及电子产品
技术领域
本发明涉及安装有由集成电路(IC)构成的芯片的CSP(芯片级封装，Chip Size Package)或MCP(多芯片封装，Multi Chip Package)等的半导体器件(封装)以及其制作方法，并且涉及装载有该封装的电子产品。
背景技术
以移动电话和电子笔记本为典型的便携用电子产品一方面被要求具有各种各样的包括电子邮件的收发，声频识别，由小型照相机收录图像等功能，另一方面，用户对电子产品体积的小型化，轻巧化的需求依然强烈。所以，就产生了在便携用电子产品的有限容积中装载更大规模的电路或更大存储量的芯片的必要性。
由此，封装技术之一的芯片级封装CSP作为将内含IC的芯片装载到印刷线路板的技术受到注目。CSP能够做到几乎和裸芯片相同程度的体积小型化，轻巧化。而且，CSP不同于裸芯片，当封装厂家提供的芯片在电子产品厂家被装载时，CSP不需要无尘室(clean room)以及特殊焊接机(bonder)等设备和技术，适应于标准化。另外，CSP具有裸芯片所不具有的封装的优势功能，包括从外部环境保护芯片的保护功能；能够使印刷线路板的引脚标准化普及的功能；以及能够将亚微标度的芯片的布线扩大到和印刷线路板相同程度的毫米标度的标度转换功能，所以CSP对电子产品厂家来说，是实现体积小型化，轻巧化不可缺少的必要技术。
为了实现CSP的进一步的体积小型化，轻巧化，装载在CSP的芯片的超薄化被认为是一大课题。比如，下面的非专利文件1中提到厚度为50μm或更薄的芯片是现在的目标值。
非专利文件1
SEMICON Japan 2002年12月5日由SEMI Japan主办的半导体装置以及材料工业的技术规划(Technical Programs for theSemiconductor Equipment and Material Industries)，薄芯片(晶片，die)装载的现状~50μm或更薄的展望，富士通公司 早坂 升(Noboru Hayasaka)[标准化事例以及今后标准化应做的事项]P1-P8
一般来说，在以CSP为典型的封装中安装芯片的制作工艺过程中，对其上形成有后来成为芯片的半导体元件的硅片的反面实施被称为背面研磨(back grind)的研磨工艺。通过这个研磨工艺，芯片可以变薄，从而实现了封装的体积小型化，轻巧化。
但是，由于这个背面研磨的研磨工艺会在硅片的背面留下深几十nm左右的研磨痕迹，成为导致芯片的机械强度降低的一个原因。有时，除了研磨痕迹，还会出现形成裂缝的情况。并且，裂缝的深度为几μm，有时甚至可以达到20μm。该研磨痕迹以及裂缝都会成为在后面工艺中芯片破损的原因，而且，随着芯片薄膜化的进展，这个问题将会变得越来越深刻。
为了解决上述问题，在实施背面研磨后，可以追加被称为应力消除(stress relief)的工艺。应力消除是使硅片背面平坦化的处理，具体实施的处理是等离子蚀刻，湿式蚀刻，干式研磨(polishing)等。但是，虽然上述应力消除对消除几十nm左右深的研磨痕迹有效，但对达到几μm-20μm深的裂缝的效果不理想，另外，如果要完全消除裂缝，应力消除工艺需要相当长的时间，这样，制作芯片的处理能力就会变低，所以不是理想的解决办法。
此外，当在背面实施背面研磨时，有必要在形成有元件的硅片的表面粘贴胶带和衬底以便保护元件。所以，在背面研磨中对硅片厚度的控制实际上是对硅片，以及为保护元件而粘贴的胶带和衬底合计的总厚度的控制，因此，当保护用的胶带和衬底具有弯曲性，或其厚度不均匀时，研磨后的硅片的厚度就会产生几μm-几十μm的不均匀。由于硅片的厚度影响制作的芯片的特性，所以如果厚度不均匀，就有芯片特性不均匀的问题。
而且，跟玻璃衬底相比，硅片的单价昂贵，并且，在市场上大多流通的是至多直径大约12英寸大小的硅片。虽然市场上也有比12英寸大的硅片，随着尺寸的增大，每单位面积的价格就会增多，所以不适合作为提供廉价芯片的材料。但是，从一个硅片能够制作出的芯片的数量有限，所以很难在直径12英寸的硅片上提高产量，因此不适合大量生产。
发明内容
针对上述问题，本发明的目的是提供满足以下条件的封装以及其制作方法，该条件为，一，不实施造成裂缝以及研磨痕迹的背面研磨处理，这样可以使芯片飞跃性地变薄；二，可以制作出低成本并且高产量的芯片；三，可以抑制芯片厚度的不均匀。并且，本发明的另一目的是提供装载有该封装的电子产品。
本发明用连续振荡的激光晶化作为支撑物发挥作用的衬底上的膜的厚度为500nm或更薄的半导体薄膜，然后用该晶化过的半导体膜形成芯片，该芯片具有总膜厚为5μm，优选等于或少于2μm的薄膜的半导体元件。并且，在最后衬底被剥离的状态下，该芯片被装载到内插板。
具体来说，在第一衬底上形成金属膜，将该金属膜的表面氧化形成厚几nm的薄金属氧化膜。然后，在该金属氧化膜上依次形成并层叠绝缘膜，半导体膜。随后，用连续振荡的激光将半导体膜晶化，然后用晶化过的半导体膜制作半导体元件。接下来在形成半导体元件后，粘贴第二衬底以便覆盖该元件，使半导体元件处于夹在第一衬底和第二衬底之间的状态。
然后，在与形成有半导体元件的第一衬底相反的一侧粘接第三衬底从而加固第一衬底的刚度。第一衬底的刚度如比第二衬底强，当剥离第一衬底时，就不容易对半导体元件造成损伤，能够顺利地执行剥离工艺。然而，在后面的从第一衬底剥离半导体元件的工艺中，如果第一衬底的刚度足够，就不一定必须在第一衬底上粘接第三衬底。
随后，执行加热处理晶化金属氧化膜，加强脆性使衬底容易从半导体元件上被剥离下来。第一衬底和第三衬底一起从半导体元件上被剥离下来。另外，为晶化金属氧化膜的加热处理可以在粘贴第三衬底之前实施，也可以在粘贴第二衬底之前实施。或者，在形成半导体元件的工艺中实施的加热处理可以兼用于该金属氧化膜的晶化工艺。
由于该剥离的工艺，产生了金属膜和金属氧化膜之间分离的部分；绝缘膜和金属氧化膜之间分离的部分；以及金属氧化膜自身双方分离的部分。不管怎样，从第一衬底剥离半导体元件并将其粘附在第二衬底上。
剥离第一衬底后，将半导体元件安装到内插板(interposer)并剥离第二衬底。注意，第二衬底不一定必须被剥离，比如，如果跟芯片的厚度比，更重视机械强度的情况下，可以在第二衬底被粘贴在芯片的状态下完成封装。
另外，可以用倒装芯片法(Flip Chip)或布线接合法(WireBonding)来实现内插板和芯片的电连接(接合)。当用倒装芯片法时，在安装半导体元件到内插板的同时进行接合。当用布线接合法时，接合的工艺在安装芯片并剥离第二衬底后被实施。
注意，在一个衬底上形成多个芯片的情形中，在中途实施切割(dicing)，使芯片们互相分开。实施切割的工艺，可以在形成半导体元件后的任一工艺之间被插加执行，优选在以下时间实施切割的工艺：一，在剥离第一衬底后，安装之前；二，在安装后，剥离第二衬底之前；三，在剥离第二衬底后的任一时间。
另外，本发明可以在同一内插板上装载多个芯片形成多芯片封装的MCP。这种情况下，可以用芯片间的电布线接合法，也可以用倒装芯片法。
另外，内插板可以是通过引线架(lead frame)实现和印刷线路板电连接的形式，也可以是通过凸块(bump)实现和印刷线路板电连接的形式，还可以是其他众所周知的形式。
本发明使用两个激光，在单方向上扫描该两个激光，在通过该方法而被晶化的区域内，形成一个芯片。这两个激光分别为第一激光和第二激光。具体地，第一激光的波长在相同于或少于可见光线(830nm或更少左右)的范围。
只用脉冲振荡的激光晶化的半导体膜由多个晶粒集成而形成，该晶粒的位置以及大小均无规则。跟晶粒内部相比，晶粒的界面(即晶界，grain boundary)存在着无数导致非晶结构以及晶体缺陷等的复合中心和俘获中心。载流子如被该俘获中心俘获，晶界的电位就会升高，成为载流子的势垒，这样就产生了使载流子的电流运输特性降低的问题。另一方面，使用连续振荡激光的情形中，通过一边单方向地扫描激光的辐照区域(聚束光，beam spot)一边辐照半导体膜，可以使结晶在扫描方向上连续成长，从而形成沿该扫描方向伸长的由单结晶构成的晶粒的聚集体。然而连续振荡激光跟脉冲振荡激光相比，每单位时间的激光输出能源低，所以很难扩大聚束光的面积，这样也就很难提高产量。而且，在用YAG激光或YVO4激光晶化一般用于半导体器件的厚几十nm-几百nm的硅膜时，比基波还短的二次谐波的吸收系数高，能够高效率地执行晶化。然而，由于将激光转换成高次谐波的非线形光学元件对激光的耐性相当低，例如，连续振荡的YAG激光能够输出10kW的基波，但二次谐波的输出能源只有10W左右。例如Nd：YAG激光的情形中，从基波(波长：1064nm)到二次谐波(波长：532nm)的转换效率为50％左右。所以，为了获得半导体膜晶化所需的能源密度，必须将聚束光的面积缩小到10-3mm2大小，所以，从生产量的角度看，连续振荡的激光比不上脉冲振荡的激光。
本发明在被高次谐波的脉冲振荡的第一激光熔化的区域中，辐照连续振荡的第二激光。也就是，通过用第一激光熔化半导体膜，半导体膜对第二激光的吸收系数得到飞跃性的提高，这样就使第二激光容易被半导体膜吸收。图2A示出非晶硅膜(amorphous silicon)对激光的波长(nm)的吸收系数(cm-1)的值。图2B示出多晶硅膜(Dolycrystalline silicon)对激光的波长(nm)的吸收系数(cm-1)的值。另外，测定是从用分光椭圆测定仪(Spectro Ellipsometry)测出的衰减系数而求得。从图2A，2B可以认为，如果吸收系数是在1×104cm-1或更多的范围内，用第一激光就足够熔化半导体膜。为了获得这个范围内的吸收系数，非晶硅膜的情形中，可以认为第一激光的波长最好是780nm或更少。另外，第一激光的波长和吸收系数的关系因半导体膜的材料以及结晶性等而异。所以第一激光的波长不限于780nm或更少的范围，可以适当地设定第一激光的波长使吸收系数在1×104cm-1或更多的范围内。被第一激光熔化的部分，通过连续振荡的第二激光的辐照，在半导体膜中移动被维持的熔化状态，从而可以形成在扫描方向上连续成长的晶粒的聚集体。
熔化状态能够被维持的时间由脉冲振荡激光和连续振荡激光的输出能源的平衡来决定。在熔化状态能够被维持的时间内对半导体膜辐照下一个脉冲振荡激光，在上述熔化状态被维持的情况下能够继续半导体膜的退火。在极端的情形中，先暂时用脉冲激光熔化半导体膜，之后只用基波辐照便能维持熔化状态的情况也是可能的。这种情形中，只单次辐照脉冲激光，之后用连续振荡激光来维持熔化状态。
越高层次的谐波能源就越低，第一激光在其基波的波长为1μm左右时，最好是二次谐波。但是，本发明并不局限于此，第一激光只要具有可见光或更短的波长即可。另外，从对第一激光的能源补助的目的出发，与对半导体膜的吸收系数相比，第二激光更重视输出功率。所以，第二激光最好用基波。但是，本发明并不局限于此，第二激光可以是基波，也可以是高次谐波。
当第二激光用基波时，没有必要转换波长，所以不用考虑非线形光学元件的退化而抑制能源。例如，第二激光可以输出连续振荡的少于可见光线的激光的100倍或更多的能源(比如输出能源1000W或更多)。因此，可以省略维护非线形光学元件的复杂程序，提高被半导体膜吸收的激光的总能源，所以可以获得直径大的晶粒。
另外，脉冲振荡跟连续振荡相比，被振荡的激光的每单位时间的能源高于连续振荡。另外，高次谐波和基波相比，高次谐波的能源低，基本波的能源高。本发明将高次谐波或具有等于或短于可见光线波长的激光作为脉冲振荡，基波的激光作为连续振荡，这个结构跟将高次谐波和基波都作为连续振荡的结构，或将高次谐波作为连续振荡，基波作为脉冲振荡的结构相比，可确保高次谐波的聚束光和基波的聚束光互相重叠区域的空间，因此，可以飞跃性地减少在制作芯片中设计上的制约。
可以采用脉冲振荡的Ar激光，Kr激光，准分子激光，CO2激光，YAG激光，Y2O3激光，YVO4激光，YLF激光，YA1O3激光，玻璃激光，红宝石激光，翠绿宝石激光，Ti：蓝宝石激光，铜蒸汽激光或金蒸汽激光作为第一激光。
可以采用连续振荡的Ar激光，Kr激光，CO2激光，YAG激光，Y2O3激光，YVO4激光，YLF激光，YA1O3激光，翠绿宝石激光，Ti：蓝宝石激光，或氦镉激光作为第二激光。
例如，以连续振荡的YAG激光和脉冲振荡的准分子激光为例，说明重叠用两个激光形成的两个聚束光的情况。
图3A表示具有基波的连续振荡的YAG激光的聚束光10和具有二次谐波的连续振荡的YAG激光的聚束光11重叠的状态。具有基波的YAG激光可以获得10kW左右的输出能源，而具有二次谐波的YAG激光可以获得10W左右的输出能源。
假设激光的能源百分之百能被半导体膜所吸收，通过将各个激光的能源密度设定为0.01-100MW/cm2，可以提高半导体膜的结晶性。所以，在此的能源密度设定为1MW/cm2。
假设具有基波的连续振荡的YAG激光的聚束光10的形状为矩形，其短轴方向的长度为LX1，长轴方向的长度为LY1，为了满足上述能源密度，使LX1＝20μm-100μm，比如当LX1＝20μm时，LY1＝50mm左右，当LX1＝30μm时，LY1＝30mm左右，当LX1＝100μm时，LY1＝10mm左右是妥当的。也就是说，在这种情况下，LY1的值在10mm至50mm的范围内是获得更好的结晶性的适当的值。
假设具有高次谐波的连续振荡的YAG激光的聚束光11的形状为矩形，其短轴方向的长度为LX2，长轴方向的长度为LY2，为了满足上述能源密度，使LX2＝20μm-100μm，比如当LX2＝10μm时，LY2＝100mm左右是妥当的。
具有基波的连续振荡的YAG激光的聚束光10和具有二次谐波的连续振荡的YAG激光的聚束光11重叠区域的面积，当假设聚束光11完全重叠于聚束光10时，上述重叠面积相当于聚束光11的面积。
图3B表示具有基波的连续振荡的YAG激光的聚束光10和脉冲振荡的准分子激光的聚束光12重叠的状态。脉冲振荡的准分子激光每脉冲可以获得1J左右的输出能源。另外，将脉冲幅度设定为30ns时，每单位时间的输出能源为30MW。所以，假设脉冲振荡的准分子激光的聚束光12的形状为矩形，其短轴方向的长度为LX3，长轴方向的长度为LY3，为了满足上述能源密度，使LX3＝20μm-500μm，比如当LX3＝400μm时，LY3＝300mm左右是妥当的。
具有基波的连续振荡的YAG激光的聚束光10和脉冲振荡的准分子激光的聚束光12重叠区域的面积，当假设聚束光10完全重叠于聚束光12时，这个重叠面积相当于聚束光10的面积。
因此，跟如图3A所示，第一激光和第二激光都采用连续振荡激光相比，如本发明所示，第一激光采用连续振荡激光，第二激光采用脉冲振荡激光可以将两个激光重叠的面积飞跃性地扩大，因此，可以飞跃性地减少在制作芯片中设计上的制约，从而进一步提高了生产量。
另外，激光不局限于两个，也可以是两个以上。可以使用多个具有高次谐波的第一激光，也可以使用多个第二激光。
采用线形的聚束光，可以将在扫描方向上晶化的晶粒聚集的区域的，上述聚束光的长轴方向的幅宽尽量地扩大。也就是，可以减少在整个聚束光中形成在长轴两端的结晶性欠佳的区域所占面积的比例。但是，本发明中聚束光的形状不限制于线形，只要能对被辐照体执行足够的退火，采用矩形，平面形的聚束光也没有问题。
将聚束光加工成在单方向上为长惰圆形或矩形，在该聚束光的短轴方向扫描晶化半导体膜，可以提高生产量。加工后的激光变成惰圆形，这是因为，激光的原来形状是圆形或近于圆形。激光的原来形状如果是长方形，用柱面透镜在单方向上扩大该长方形，使长轴变得更长，如此加工后再使用。另外，分别加工多个激光使其在单方向上成为长惰圆形或矩形，然后连接多个激光，在单方向上制作更长的激光，从而进一步提高生产量。
注意，这里所述的“线形”从严格的意义上讲不是“线”的意思，而是具有大的长宽比的长方形(或长惰圆形)的意思。例如，虽然长宽比是2或更多(优选10-10000)的长方形被称作线形，但这不影响线形包含于矩形的情况。
图1A表示用第一以及第二激光晶化半导体膜的状态。101表示第一衬底，半导体膜102形成在第一衬底101之上。103相当于用第一激光在半导体膜102上形成的聚束光(第一聚束光)，104相当于用第二激光在半导体膜102上形成的聚束光(第二聚束光)。
虚线的箭头表示聚束光103，104相对于半导体膜102相对移动的方向。聚束光103，104在半导体膜102上单方向地扫描后，在垂直于该扫描方向的方向上横向滑动。随后，在相反于该扫描方向的方向上，再次扫描半导体膜102。按顺序重复这样的扫描，可以使半导体膜102整体被聚束光103，104辐照。另外，聚束光103，104横向滑动的距离最好和聚束光103的扫描方向的垂直方向中的幅宽基本相同。
另外，105-107相当于后面作为芯片使用的区域，通过单方向地扫描第一以及第二聚束光103，104，使105-107的各个领域各自落在晶化过的区域的范围中，换句话说，芯片的位置不会被安排到横穿形成在第二聚束光104的长轴两端的结晶性欠佳的区域(边缘)。通过这样的布置，至少可以将几乎不存在结晶晶界的半导体膜用作芯片内的半导体元件。
图1B是一个斜透视图，表示在各个领域105-107中各自形成的芯片105a-107a被安装到内插板108而形成的封装。可以象芯片105a和芯片106a那样，以层叠的形式被安装到内插板108，也可以象芯片107a那样，以单层的形式被安装到内插板108。另外，提供在内插板108上的终端可以是提供有焊锡球的球状矩阵排列(Ball GridArray)类型，也可以是终端被布置在周边的引线架类型，或者具有其他众所周知形式的类型。
本发明用激光晶化半导体膜，这样不但可以减少对玻璃衬底的热的损伤，而且可以实现晶化。依此，可以在廉价玻璃衬底上用多晶半导体膜制作芯片。
本发明可以利用比硅片廉价并且大面积的玻璃衬底，因此可以高产量地大量生产低成本芯片，并且可以飞跃性地减少每张芯片的生产成本。此外，衬底可以被反复使用，这样，可以减少每张芯片的生产成本。
另外，可以形成总膜厚度在5μm，优选等于或少于2μm的芯片，通过不实施造成裂缝以及研磨痕迹原因的背面研磨，芯片可以被制作得极薄。并且，芯片厚度的不均匀是在形成膜时，由于构成芯片的各个膜的不均匀而导致，这个不均匀多也不过几百nm左右，跟背面研磨处理导致的几-几十μm的不均匀相比，不均匀性可以被飞跃性地减少。
通过将本发明的封装用于电子产品，可以使电路规模或存储容量更大的芯片被更多地装载到电子产品有限的容积中，这样不但可以实现电子产品的多功能化，而且可以实现电子产品的小体积化，轻巧化。特别是便携用电子产品，由于其小体积化，轻巧化被重视，所以利用本发明的封装是有效的。
本发明的封装可以被利用于控制驱动液晶显示器件，在其各个像素中提供有以有机发光元件为典型的发光元件的发光器件，DMD(数字微镜器件，Digital Micromirror Device)，PDP(等离子体显示屏板，Plasma Display Panel)，FED(场致发光显示器，Field EmissionDisplay)等的显示器件的各种电路。例如，在有源矩阵型液晶显示器，发光器件的情形中，选择各个像素的扫描线驱动电路，控制馈送视频信号到被选择的像素的时间的信号线驱动电路，生成馈送到扫描线驱动电路以及信号线驱动电路的信号的控制器等都可以用本发明的封装来形成。另外，不仅仅是控制显示器件驱动的电路，本发明还适用于微处理机(CPU)，存储器，电源电路，或其他的数字电路，或模拟电路。此外，以TFT为典型的半导体元件的特性有了飞跃性进步时，一般被称为高频电路的各种电路也可以用本发明的封装来实现。
本发明的电子产品不仅包括上述显示器件，还包括摄像机，数码相机，护目镜式显示器(头戴式显示器)，导航系统，声频重播装置(汽车音响，音响组合等)，个人计算机，游戏机，便携式信息终端(便携式计算机，移动电话，便携式游戏机，或电子书等)，搭载有记录介质的图像重播装置(具体地说是DVD(数字通用盘，DigitalVersatile Disc)等重播记录介质并可以显示其图像的装配有显示器的装置)。特别是，本发明在被用于以笔记本计算机，便携式摄像机，便携式数码相机，护目镜式显示器(头戴式显示器)，便携式信息终端(便携式计算机，移动电话，便携式游戏机，或电子书等)为典型的便携式电子产品时有效。
此外，本发明的封装不仅适用于CSP，MCP，而且可以适用于DIP(双列直插式封装，Dual In-line Package)，QFP(塑料方型扁平式封装，Quad Flat Package)，SOP(小尺寸封装，Small OutlinePackage)等所有众所周知形式的封装。
附图说明
图1A和1B分别是表示本发明中在晶化半导体时聚束光的扫描路线的视图，以及安装有芯片的封装的斜透视图；
图2A和2B是表示激光的波长和吸收系数关系的视图；
图3A和3B是表示聚束光大小关系的视图；
图4是表示实施晶化时使用的激光辐照设备的结构的视图；
图5A-5E是表示封装的制作方法的视图；
图6A-6C是表示封装的制作方法的视图；
图7A-7C是表示封装的制作方法的视图；
图8是表示封装制作工艺的流程图；
图9A-9C是表示封装制作工艺中切割时间的视图；
图10A-10D是表示封装横截面结构的斜透视图，横截面图；
图11是表示封装横截面结构的斜透视图；
图12A和12B是表示封装横截面结构的横截面图；
图13A和13B是表示层叠型封装的制作方法的视图；
图14A和14B是表示层叠型封装的制作方法的视图；
图15A和15B分别是表示本发明的电子产品之一的移动电话的模块的俯视图和方框图。
本发明的选择图为图1
具体实施方案模式
实施方案模式1
本实施方案模式将描述用经第一以及第二激光晶化过的半导体薄膜形成封装的方法。本实施方案模式中虽然以两个TFT作为半导体元件进行举例，但在本发明中包含于芯片中的半导体元件并不局限于此，它包含所有的电路元件。例如，除了TFT以外，典型的还包括以存储元件，二极管，光电转换元件，电阻元件，线圈(coil)，电容元件，电感器等。
首先，如图5A所示，在第一衬底500上用溅射法形成金属膜501。在此，用钨作为金属膜501的材料，其膜的厚度为10nm-200nm，优选50nm-75nm。注意在本实施方案模式中在第一衬底500上直接形成金属膜501，但是也可以用氧化硅，氮化硅，氮氧化硅等的绝缘膜覆盖第一衬底500后，然后在其上形成金属膜501。
形成金属膜501后，在不暴露于大气的情况下，在金属膜上层叠氧化物膜502。在此，形成厚150nm-300nm的氧化硅膜作为氧化物膜502。注意如果使用溅射法形成该膜，在第一衬底500的边缘也会形成膜。这样在实施后面的剥离工艺时，为了防止氧化物膜502残留在第一衬底500上，最好用氧灰化(O2 ashing)等方法选择性地清除形成在衬底边缘的金属膜501以及氧化物膜502。
另外，在形成氧化物膜502时，作为溅射的前阶段在靶和衬底之间用闸门屏蔽，产生等离子体从而实施预溅射(pre-sputtering)。预溅射在以下条件下实施，即设定流量Ar为10sccm，O2为30sccm，第一衬底500的温度为270℃，成膜功率为3kW，衬底在被保持平行的状态下被实施预溅射。通过该预溅射，在金属膜501和氧化物膜502之间形成了厚几nm左右(在此为3nm)的极薄的金属氧化膜503。金属氧化膜503是由于金属膜501表面的氧化而形成的。所以，本实施方案模式中的金属氧化膜503是由氧化钨而形成。
另外，虽然本实施方案模式通过预溅射形成了金属氧化膜503，但本发明并不局限于此，例如也可以添加氧，或添加了Ar等惰性气体的氧，通过等离子体意向性地将金属膜501的表面氧化后形成金属氧化膜503。
形成氧化物膜502后，用PCVD法形成底膜504。在此，形成厚100nm的氧氮化硅膜作为底膜504。然后，在形成底膜504后，在不暴露于大气的情况下，形成厚25-100nm(优选30-60nm)的半导体膜505。顺便提一下，半导体膜505可以是非晶半导体，也可以是多晶半导体。另外，半导体不仅可以采用硅作为其材料，还可以采用锗硅。当采用锗硅时，锗的密度最好在0.01-4.5atomic％左右。
随后，如图5B所示，用第一以及第二激光辐照半导体膜505，执行晶化。
本实施方案模式使用能源为6W，1脉冲的能源为6mJ/p，TEM00的振荡模式，二次谐波(527nm)，振荡频率为1kHz，脉冲幅宽为60ns的YLF激光作为第一激光。注意，第一激光通过光学加工在半导体膜505表面形成的第一聚束光是短轴为200μm，长轴为3mm的矩形，其能源密度为1000mJ/cm2。
本实施方案模式使用能源为2kW，基波(1.064μm)的YAG激光作为第二激光。注意，第二激光通过光学加工在半导体膜505表面形成的第二聚束光是短轴为100μm，长轴为3mm的矩形，其能源密度为0.7MW/cm2。
然后，在半导体膜505的表面辐照第一聚束光和第二聚束光并使两个聚束光重叠。上述两个激光按图5B所示的箭头的方向扫描。通过第一激光的熔化，基波的吸收系数被提高了，这样第二激光的能源就容易被半导体膜吸收。随后，通过辐照连续振荡的第二激光，在半导体膜中移动被维持的熔化状态的区域，从而可以形成在扫描方向上连续成长的晶粒的聚集体。通过在沿扫描的方向上形成延伸的单结晶的颗粒，可以形成至少在TFT的沟道方向上几乎不存在结晶晶界的半导体膜。
另外，也可以在稀有气体或氮等惰性气体的气氛中辐照激光。通过该程序，可以减少由于辐照激光而引起的半导体表面的粗糙，而且可以减少由界面态密度(interface state density)的不均匀导致的门栏值的不均匀。
为了提高能源密度均匀区域在全体中所占比例，激光的聚束光最好具有线形，矩形，或长轴对短轴的长度比大于5的惰圆形。
通过以上的对半导体膜505辐照激光的程序，形成了结晶性被提高的半导体膜506。随后，如图5C所示，对半导体膜506实施形成图案，从而形成岛形状的半导体膜507，508，用该岛形状的半导体膜507，508形成以TFT为典型的各种半导体元件。另外，在本实施方案模式中，底膜504和岛形状的半导体膜507，508连接在一起，但是可以根据半导体元件的情况，在底膜504和岛形状的半导体膜507，508之间形成电极以及绝缘膜等。例如，在半导体元件之一的底栅型TFT的情形中，在底膜504和岛形状的半导体膜507，508之间形成栅电极以及栅绝缘膜。
在本实施方案模式中，用岛形状的半导体膜507，508形成顶栅型的TFT509，510(图5D)。具体地说，形成栅绝缘膜511使其覆盖岛形状的半导体膜507，508。然后，在栅绝缘膜511上形成导电膜，通过形成图案的程序形成栅电极512，513。接着将栅电极512，513，或形成抗蚀剂膜并形成图案用作掩膜，给岛形状的半导体膜507，508掺杂赋予n型导电性的杂质从而形成源区，漏区，以及LDD(轻掺杂漏，Light Doped Drain)区。顺便提一下，虽然在此TFT509，510被制作为n型，如制作为p型TFT，可以掺杂赋予p型导电性的杂质。
通过上述工序，可以形成TFT 509，510。注意，制作TFT的方法不限于在形成岛形状的半导体膜后制作TFT的上述工序，。本发明的一个特征是用激光晶化半导体膜，这样可以减少元件之间的移动度，门栏值和开电流的不均匀。
然后，形成第一层间绝缘膜514使其覆盖TFT509，510。随后，在栅绝缘膜511以及第一层间绝缘膜514形成接触孔(contact hole)后，形成通过接触孔和TFT509，510连接的布线515-518，并使这些布线和第一层间绝缘膜514连接。然后在第一层间绝缘膜514上形成第二层间绝缘膜519，并使其覆盖布线515-518。
随后，在第二层间绝缘膜519形成接触孔，并在第二层间绝缘膜519上形成通过该接触孔和布线518连接的焊垫(pad)520。虽然在本实施方案模式，焊垫520通过布线518和TFT510电连接在一起，然而半导体元件和焊垫520的电连接形式不局限于此。
接下来，在第二层间绝缘膜519和焊垫520上形成保护层521。保护层521在后面程序的粘接以及剥离第二衬底时，可以保护在第二层间绝缘膜519和焊垫520的表面，并且，该保护层采用在剥离第二衬底后能够被清除的材料。比如，在整个表面涂敷可溶于水或醇的环氧基，丙乙烯基，硅基的树脂，然后烘烤后就可以形成保护层521。
在本实施方案模式中，用旋涂涂敷由水溶性树脂(东亚合成制：VL-WSHL10)制成的膜并使该膜的厚度为30μm，随后进行2分钟的曝光以实现初步硬化，然后用UV光辐照内面2.5分钟，表面10分钟，共计12.5分钟以执行正式硬化，这样就形成了保护层521(图5E)。
另外，层叠多个有机树脂膜的情形中，在涂敷或焙烧时，有这些有机树脂使用的溶剂的一部分溶解，或粘合性变得过高的危险。因此，在第二层间绝缘膜519和保护层521都用可溶于相同介质的有机树脂时，为使在后面的工艺中顺利地清除掉保护层521，最好形成无机绝缘膜(SiNx膜，SiNxOY膜，AlNx膜，或AlNxOY膜)以备用，该无机绝缘膜被夹在第二层间绝缘膜519和焊垫520之间并且覆盖第二层间绝缘膜519。
随后，晶化金属氧化膜503使后面的剥离程序容易被执行。通过该晶化处理，可以使金属氧化膜503在晶界变得易碎，加强了其脆性。本实施方案模式具体执行420℃-550℃，0.5-5小时左右的加热处理来执行晶化工艺。
然后，形成引发剥离机制的部分，这个程序可以部分地降低金属氧化膜503和氧化物膜502之间的紧贴性，或部分地降低金属氧化膜503和金属膜501之间的紧贴性。具体地说，用激光沿着要剥离区域的周边部分辐照金属氧化膜503，或沿着要剥离区域的周边部分从外部施加局部压力，以损坏金属氧化膜503的层内的一部分或界面附近的一部分。在本实施方案模式中，在金属氧化膜503的边缘附近垂直压下金刚石笔等硬针，并且在施加负荷的状态下，沿着金属氧化膜503移动。最好使用划线器装置并且将下压量设在0.1mm到2mm，边移动边施加压力。以这种方式在剥离之前形成引发剥离机制的紧贴性被降低的部分，可以减少后面剥离工艺的次品率，从而提高了成品率。
接下来，使用双面胶带522粘贴第二衬底523到保护层521。并且，使用双面胶带524粘贴第三衬底525到第一衬底500(图6A)。另外，可以使用粘合剂来代替双面胶带。例如，通过使用用紫外线执行剥离的粘合剂，在剥离第二衬底时，可以减轻落在半导体元件的负担。第三衬底525保护第一衬底500在后面的工艺中不受损伤。第二衬底523和第三衬底525最好采用强度比第一衬底500更高的衬底，比如，石英衬底，半导体衬底。
然后，用物理手段撕剥金属膜501和氧化物膜502。撕剥从金属氧化膜503，金属膜501或氧化物膜502之间的紧贴性在上面的步骤中被部分地降低了的区域开始。
通过上述剥离工艺，金属膜501和金属氧化膜503之间分离的部分以及氧化物膜502和金属氧化膜503之间分离的部分，金属氧化膜503自身双方产生分离的部分。并且，在第二衬底523一侧粘附有半导体元件(在此为TFT509，510)，在第三衬底525一侧粘附有第一衬底500以及金属膜501的状态下，执行分离。利用较小的力就可执行剥离(例如，利用人的手，利用喷嘴吹出气体的吹压，利用超声，等等)。图6B表示剥离后的状态。
接着，用粘合剂526粘接内插板527和附着有部分金属氧化膜503的氧化物层502(图6C)。这时，选择粘合剂526的材料使通过粘合剂粘接在一起的氧化物层502和内插板527之间的粘接力比用双面胶带522粘接在一起的第二衬底523和保护层521之间的粘接力要高是重要的。
另外，金属氧化膜503如残留在氧化物膜502的表面，氧化物膜502和内插板527之间的粘接力有可能因此而变小，所以，用蚀刻等方法完全清除残留物，然后粘接内插板，从而使粘接力得到提高。
可以采用陶瓷衬底，玻璃环氧衬底，聚酰亚胺衬底等众所周知的材料作为内插板527。另外，为了扩散在芯片内产生的热，该内插板最好具有2-30W/mK左右的高导热率。
内插板527上提供有封装用的终端530，终端530和内插板527上提供的焊锡球531电连接在一起。焊锡球531提供在和安置有封装用的终端530相反的面上。在此只表示出一个焊锡球531，但是实际上在内插板527上提供有多个焊锡球。各个焊锡球之间的间距一般被标准化为0.8mm，0.65mm，0.5mm或0.4mm。但是本发明不限于这些间距。另外，各个焊锡球的大小一般被标准化为间距的60％。但是本发明不限于这个尺寸。
另外，终端530，通过比如在铜上渡焊锡，金或锡而形成。另外，虽然本实施方案模式采用其上提供有焊锡球的球状矩阵排列类型的内插板，但是本发明不限于此。终端被布置在周边的引线架类型的内插板也无妨。
作为粘合剂526的材料，可以采用诸如反应固化粘合剂，热固化粘合剂，UV固化粘合剂等的光固化粘合剂，厌氧粘合剂等各种固化粘合剂。理想的是在粘合剂526中添加银，镍，铝，氮化铝等制成的粉末，或填充物使其具有高导热性。
然后，如图7A所示，从保护层521按双面胶带522，第二衬底523的顺序剥离，或者同时两者一起剥离。
然后，如图7B所示，清除保护层521。在此，因保护层521使用水溶性树脂，所以用水熔化后清除。当残留下的保护层521成为次品的原因时，最好在清除完毕后，对表面实施清洗处理或氧等离子体处理，除去残留的保护层521的那一部分。
接下来，通过布线接合法，用布线532连接焊垫520和终端530，然后通过真空密封方式或树脂密封方式进行密封，这样就完成了封装。当使用真空密封方式时，一般使用陶瓷，金属或玻璃等的盒子进行密封。当使用树脂密封方式时，具体使用成形树脂(mold resin)。另外，不一定必须要密封芯片，但通过密封，可以增加封装的机械强度，扩散在芯片中产生的热，并且阻挡来自邻接电路的电磁噪音。
在实施方案模式中，金属膜501采用钨作材料，但本发明的金属膜的材料并不限于该材料。只要能够在其表面形成金属氧化膜503，通过晶化该金属氧化膜503可以将衬底剥离的材料，任何含有金属的材料都可以被利用。例如，可以使用W，TiN，WN，Mo等。另外，利用这些金属的合金作为金属膜时，在晶化时的最佳加热温度根据其成分比例而不同。所以，调节该合金的成分比例，可以使加热处理在不妨碍半导体元件的制作程序的温度范围内被执行，所以半导体元件工艺的选择范围不容易被限制。
另外，在本实施方案模式中，以一个封装搭载一个芯片的CSP为例进行了描述，但是本发明并不局限于此。也可以是搭载多个并列或层叠的芯片的MCP。
另外，第一激光以及第二激光不限定于本实施方案模式所示的辐照条件。
例如可以使用能源为4W，1脉冲的能源为2mJ/p，TEM00的振荡模式，二次谐波(532nm)，振荡频率为1kHz，脉冲幅宽为30ns的YAG激光作为第一激光。又例如可以使用能源为5W，1脉冲的能源为0.25mJ/p，TEM00的振荡模式，三次谐波(355nm)，振荡频率为20kHz，脉冲幅宽为30ns的YVO4激光作为第一激光。又例如可以使用能源为3.5W，1脉冲的能源为0.233mJ/p，TEM00的振荡模式，四次谐波(266nm)，振荡频率为15kHz，脉冲幅宽为30ns的YVO4激光作为第一激光。
另一方面，可以使用能源为500W，基波(1.064μm)的Nd：YAG激光作为第二激光。并且，例如可以使用能源为2000W，基波(1.064μm)的Nd:YAG激光作为第二激光。
另外，垂直于扫描方向上的聚束光的幅宽只要能够充分确保形成芯片，第一激光也可以是连续振荡。第一激光如果不是脉冲振荡而是连续振荡时，在第一激光的聚束光的垂直于扫描方向的方向中的幅宽范围内形成各个芯片。所以为了确保扫描方向的垂直方向上聚束光的幅宽具有足够形成芯片的尺寸，可以重叠通过多个第一激光而获得的多个聚束光使其作为一个聚束光来使用。
另外，用激光进行晶化前，也可以实施利用催化剂元素的晶化程序。采用镍作为催化剂元素，除此以外，还可以采用锗(Ge)，铁(Fe)，钯(Pd)，锡(Sn)，铅(Pb)，钴(Co)，白金(Pt)，铜(Cu)，金(Au)等元素。完成利用催化剂元素的晶化程序后，如果实施利用激光的晶化程序，当利用催化剂元素晶化时形成的结晶在离衬底近的一侧不因激光的辐照而熔化，因而会残存下来，该结晶作为结晶核推进晶化。所以，利用激光辐照的晶化在从衬底那一侧朝半导体表面的方向上均匀的被实施，跟只实施利用激光的晶化程序相比，在利用激光进行晶化前实施利用催化剂元素的晶化程序可以提高半导体膜的结晶性，减少在利用激光晶化后的半导体膜表面的粗糙。所以，这样形成的半导体元件，典型的是TFT的特性的不均匀，可以进一步得到减少，并可以减少闭电流。
另外，可以在添加催化剂元素后实施加热处理来促进晶化，然后辐照激光提高结晶性。也可以省略掉该加热处理。具体地说，在添加催化剂元素后可以辐照激光提高结晶性，从而代替加热处理。
注意，本发明的芯片的厚度，不仅包括半导体元件自身的厚度，还包括金属氧化膜和半导体元件之间提供的绝缘膜的厚度，形成半导体元件后覆盖的层间绝缘膜的厚度，以及焊垫。但是不包括凸块(bump)。
实施方案模式2
本实施方案模式将用图4说明在制作本发明的封装中使用的激光辐照设备的结构。
图中的数字201表示脉冲振荡的激光振荡器，在本实施方案模式中使用6W的Nd:YLF激光。并且使用的激光振荡器201是TEM00的振荡模式，通过非线形光学元件转换为二次谐波。虽然没有必要特别限定于二次谐波，但从能源效率的角度，二次谐波比更高层次的谐波优越。频率是1kHz，脉冲幅宽为60ns左右。在本实施方案模式中使用输出能源为6W的固体激光，但是也可以使用输出能源达到300W的激光，比如XeCl准分子激光。
非线形光学元件使用非线形光学常数比较大的KTP(KTiOPO4)，BBO(B-BaB2O4)，LBO(LiB3O5)，CLBO(CsLiB6O10)，GdYCOB(YCa4O(BO3)3)，KDP(KD2PO4)，KB5，LiNbO3，Ba2NaNb5O15等的结晶。其中尤其LBO，BBO，KDP，KTP，KB5，CLBO等如被使用可以提高从基波到谐波的转换效率。
因激光通常是从水平方向被射出，从激光振荡器201振荡出的第一激光的前进方向在反射镜202被转换为和垂直方向的角度(入射角)为θ1的方向。本实施方案模式中，θ＝21°。前进方向被改变的第一激光的聚束光的形状在镜头203被加工，然后辐照到被处理物204上。图4中反射镜202和镜头203相当于控制第一激光的聚束光的形状以及位置的光学系统。
图4中，镜头203使用平凹柱面透镜203a和平凸柱面透镜203b。平凹柱面透镜203a的曲率半径是10mm，其厚度为2mm，当第一激光的前进方向作为光轴时，平凹柱面透镜203a被安排在从被处理物204的表面沿光轴29mm的位置。并且，平凹柱面透镜203a的母线垂直于第一激光入射到被处理物204的入射面。
平凸柱面透镜203b的曲率半径是15mm，其厚度为2mm，平凸柱面透镜203b被安排在从被处理物204的表面沿光轴24mm的位置。并且，平凸柱面透镜203b的母线平行于第一激光入射到被处理物204的入射面。
于是，在被处理物204上形成了3mm×0.2mm大小的第一聚束光206。
图中的数字210表示连续振荡的激光振荡器，本实施方案模式中使用2kW基波的Nd:YAG激光。从激光振荡器210振荡出的第二激光通过φ300μm的光导纤维211被传送出来。光导纤维211被安排在射出口方向和垂直方向的角度呈θ2的位置。本实施方案模式中，θ2＝45°。另外，光导纤维211的射出口被安排在沿从激光振荡器210射出的第二激光的光轴从被处理物204的表面105mm的位置，并且该光轴被包含在入射面中。
从光导纤维211射出的第二激光在镜头212处其聚束光的形状被加工，然后辐照到被处理物204上。图4中光导纤维211和镜头212相当于控制第二激光的聚束光的形状以及位置的光学系统。图4中，镜头213使用平凸柱面透镜212a和平凸柱面透镜212b。
平凸柱面透镜212a的曲率半径是15mm，其厚度为4mm，平凸柱面透镜212a被安排在从被处理物204的表面沿第二激光的光轴85mm的位置。并且，平凸柱面透镜212a的母线垂直于入射面。平凸柱面透镜212b的曲率半径是10mm，其厚度为2mm，平凸柱面透镜212b被安排在从被处理物204的表面沿第二激光的光轴25mm的位置。
于是，在被处理物204上形成了3mm×0.1mm大小的第二聚束光205。
本实施方案模式中，其上形成有半导体膜的衬底作为被处理物204被安置为平行于水平面。半导体膜比如，可以在玻璃衬底的表面形成。形成有半导体膜的衬底是厚0.7mm的玻璃衬底，将衬底固定在吸台207上，这样当辐照激光时，衬底就不会掉下来。吸台207通过X轴用的单轴自动装置208和Y轴用的单轴自动装置209，使被处理物204可以在平行面内向X轴Y轴移动。
在对激光有透光性的衬底上形成的半导体膜被实施退火时，为了实现激光的均一照射，假设激光的形状是矩形，当将入射平面定义为与被照表面垂直的平面，且入射平面是包括激光的长边或短边的平面时，理想的是激光的入射角“φ”满足不等式φ≥arctan(W/2d)。在不等式中，“W”是包括在入射平面中的长边或短边的长度，“d”是对激光具有透光性的放在被照表面上的衬底的厚度。在使用多个激光的情况下，该不等式相对于多个激光中的每个激光都需要得以满足。注意，激光的轨迹投射到入射平面上，在该轨迹不在入射平面上时确定入射角“φ”。当激光以入射角“φ”入射时，用来自衬底后表面的反射光，能执行激光的均一照射而不受到来自衬底表面的反射光的影响。上述原理假设衬底的折射率为1。实际上，大部分衬底的折射率在1.5左右，在考虑到该值在1.5左右时，获得比根据不等式算得的角更大的计算值。然而，由于被照表面上的激光使能量在其纵向上在两侧减弱，所以，干扰对两侧影响小，根据上述不等式算得的值足以获得减弱干扰的效果。上述理论对第一激光也好对第二激光也好同样行得通，虽然最好双方都满足上述不等式，但对于象准分子激光那样相干长度短的激光来说，不满足上述不等式也没有问题。上述的φ的不等式只适合当衬底对激光有透光性的情况。
一般来说，玻璃衬底对波长为1μm左右的基波以及绿色的二次谐波具有透光性。该镜头为了满足不等式，将平凸柱面透镜203b和平凸柱面透镜212b的位置朝垂直于入射面的方向上移动，使在包括聚束光短轴的被处理物204表面的垂直面内的入射角度为φ1，φ2，这样就满足了不等式。这种情况下，如第一聚束光206中有，φ1＝10°，第二聚束光205中有，φ2＝5°左右的倾斜，就不会产生干涉。
另外，最好以从稳定型共振器获得的TEM00振荡模式(单模)来发射第一激光和第二激光。TEM00振荡模式的情形中，激光具有高斯强度分布，集光性优越，所以使聚束光的加工变得容易。
然后，用Y轴自动装置209在第二聚束光205的短轴方向上扫描被处理物204(其上形成有半导体膜的衬底)。这时，各个激光振荡器201，202的输出能源为上述规格的值，通过该对被处理物204的扫描，第一聚束光206以及第二聚束光205对被处理物204的表面进行了相对性的扫描。
被第一聚束光206辐照的区域中半导体膜熔化，使半导体膜对连续振荡的第二激光的吸收系数有飞跃性的增高。据此，在扫描方向上延伸的相当于第二聚束光205的长轴幅宽的1-2mm的区域中，在该扫描方向上成长了的单结晶的结晶粒以被铺的状态而形成。
另外，在半导体膜中，第一聚束光206和第二聚束光重叠辐照的区域通过基波的第二激光维持吸收系数被二次谐波的第一激光提高的状态。所以，即使二次谐波的第一激光的辐照中途停止，通过其后的基波的第二激光，维持半导体膜被熔化，吸收系数被提高的状态。因此，即使二次谐波的第一激光的辐照中途停止，通过扫描，可以使溶化了的吸收系数被提高了的区域在一定程度上向一个方向移动，所以，形成了在扫描方向上成长的结晶粒。而且，吸收系数被提高了的区域，在扫描的过程中，为了连续维持其状态，最好再次辐照二次谐波的第一激光，以补充能源。
另外，第一聚束光206以及第二聚束光205的扫描速度适合在几cm/s-几百cm/s左右，在此为50cm/s。
辐照第二激光，在扫描方向上成长的结晶粒形成的区域在结晶性上具有优越性。因此，如将该区域用于TFT的沟道形成区，有望获得极高的电迁移率和开电流。但是，在半导体膜中如存在不需要如此高的结晶性的部分时，可以不对该部分辐照激光。或者，也可以通过增大扫描的速度等，在不能获得高结晶性的条件下辐照激光。例如，以2m/s的速度进行扫描，虽然可以晶化a-Si膜，但是很难形成上述在扫描方向上连续晶化的区域。所以，部分提高扫描的速度，可以进一步提高产量。
另外，本发明的激光辐照设备中的光学系统并不局限于本实施方案模式中所示的结构。
实施方案模式3
在第一衬底上同时制作多个芯片的情形中，在完成封装前，在中途有必要实施切割来切离这些芯片。本实施方案模式中，将就切割的时间进行说明。
图8是封装制作过程中流程图的一个例子。另外，布线接合法和芯片倒装法的作为执行电连接集成电路的终端发挥作用的焊垫的位置不同。在此，用实线的箭头表示在形成元件后形成焊垫时的流程图的流程，用虚线的箭头表示在形成元件前形成焊垫时的流程图的流程。
先说明在形成元件后形成焊垫的情形。首先，在第一衬底上形成金属膜，将该金属膜的表面氧化形成金属氧化膜。随后在该金属氧化膜上形成绝缘膜，然后进入形成元件(半导体元件)的程序。本发明在形成元件的程序中，执行半导体膜的激光晶化。关于激光晶化的详细说明已经描述过，所以在此省略相关说明。在形成元件，完成集成电路后，形成焊垫。然后，形成保护层覆盖元件和焊垫，在保护层那一侧粘贴第二衬底，在第一衬底那一侧粘贴第三衬底。随后，从元件剥离第一以及第三衬底，然后，将粘贴在第二衬底上的元件安装到内插板上，除去第二衬底和保护层后接合布线，并实施密封，这样就完成了封装。
这种情形中，焊垫中间夹元件位于内插板的背侧，内插板和芯片之间的接合可以使用布线接合法。在用布线接合法的情形中，接合的程序，在装载芯片，除去第二衬底后被实施。在这种情况下，切割的时间如图9A所示，最好是在剥离第一以及第三衬底后，执行安装前。
其次说明在形成元件前形成焊垫的情形。首先，在第一衬底上形成金属膜，将该金属膜的表面氧化形成金属氧化膜。随后在该金属氧化膜上形成绝缘膜后，形成焊垫，然后进入形成元件(半导体元件)的程序。在元件和焊垫之间提供另一层绝缘膜，可以形成接触孔来电连接元件和焊垫，也可以在相同的绝缘膜上形成元件和焊垫双方，不通过接触孔而实现电连接。在形成元件，完成集成电路后，形成保护层覆盖元件，在保护层那一侧粘贴第二衬底，在第一衬底那一侧粘贴第三衬底。随后，从元件上剥离第一以及第三衬底，另外，因焊垫夹在元件和内插板中间，所以内插板和芯片的接合可以采用倒装芯片法。所以，对绝缘膜进行部分的蚀刻从而使焊垫暴露出来，然后在焊垫上形成凸块。在蚀刻时使用的定位用的标记最好在形成元件时用半导体膜形成以备用。然后，将粘贴在第二衬底上的元件安装到内插板上，用凸块进行接合后，除去第二衬底和保护层，然后实施密封，这样就完成了封装。
这种情形中，切割的时间如图9A所示，最好是在剥离第一以及第三衬底后，执行安装前。另外，图9A所示的切割也可以在形成凸块之前或之后。另外，切割也可以如图9B所示，在实施安装后，但在剥离第二衬底之前进行。另外，切割也可以如图9C所示，在剥离第二衬底之后进行。
上述说明是以在一个内插板上装载一个芯片为前提，但是本发明并不局限于此。层叠形成在相同的第一衬底上的芯片们时，如图9A所示，也可以在装载前实施切割。然后，各个芯片在剥离第二衬底后，按从下层芯片的顺序被安装到内插板。
此外，在互相层叠另行形成于不同的第一衬底上的芯片时，最先安装到内插板的芯片的切割，不限于如图9A所示的时间，也可以按图9B，图9C所示的时间进行切割。但是，在这种情况下，各个芯片在剥离第二衬底后，按从下层芯片的顺序被安装到内插板。
另外，不一定可以明确分开形成焊垫的程序和形成半导体元件的程序。例如，利用顶栅型TFT作为半导体元件，在制作该TFT的栅电极的程序中制作焊垫时，制作焊垫的程序被包括在制作半导体元件的程序中。这种情形中，芯片在被安装到内插板时，判断焊垫(或者凸块)是向内插板一侧暴露，还是向和内插板相反的方向暴露。也就是说，前者的情形中，可以在相同于在形成元件前形成凸块时的时间进行切割。后者的情形中，可以在相同于在形成元件后形成凸块时的时间进行切割。
实施方案模式4
在本实施方案模式中，将就内插板和芯片的电连接的方法进行说明。
图10A是一个斜透视图，其表示用布线接合法将芯片和内插板连接在一起的封装横截面结构。其中数字301表示内插板，302表示芯片，303表示成形树脂层。芯片302用安装用的粘合剂304安装在内插板301上。
表示在图10A的内插板301是提供有焊锡球305的球状矩阵排列型。焊锡球305提供在相反于安装有芯片302的内插板301的一侧。并且，提供在内插板301的布线306通过提供在内插板301上的接触孔，和焊锡球305电连接在一起。
另外，在本实施方案模式中，电连接芯片302和焊锡球305的布线306提供在内插板301的安装有芯片的那一面，但是，本发明使用的内插板并不限于此。例如，可以在内插板的内部提供多层化的布线。
并且，图10A中，芯片302和布线306通过导线(wire)307电连接在一起。图10B是图10A所示封装的横截面图。半导体元件309提供在芯片302中。焊垫308提供在相反于提供有芯片302的内插板301的一侧，焊垫308和该半导体元件309电连接在一起。并且，焊垫308通过导线307和提供在内插板301上的布线306电连接在一起。
数字310相当于印刷线路板的一部分，311相当于提供在印刷线路板310上的布线或电极。布线306通过焊锡球305和提供在印刷线路板310上的布线或电极311电连接在一起。另外，焊锡球305和布线或电极311的连接，可以采用各种各样的方法，比如热压，或由超声波引起振动的热压等。另外，也可以利用封胶(underfill)法，即填充施压后的焊锡球之间的空隙从而加强连接部分的机械强度，并且提高封装中产生的热的散热效率。封胶法不一定必须使用，但封胶法可以防止由于内插板和芯片的热膨胀系数的不匹配(mismatch)产生的应力而导致的连接短路。当用超声波施压时，比仅用热压时更能抑制连接短路的产生。特别是，当凸块多于300左右时更有效。
图10C是一个封装的横截面图，该封装用倒装芯片法连接芯片和内插板。图10C表示在芯片322上提供焊锡球327的封装。焊锡球327提供在芯片322的内插板321那一侧，并与同样提供在芯片322中的焊垫连接在一起。提供在芯片322中的半导体元件329和焊垫328连接在一起。当用TFT作为半导体元件时，焊垫328可以用形成该TFT的栅电极的导电膜来形成。
焊锡球327和提供在内插板321上的布线326连接在一起。图10C中，提供封胶324来填充焊锡球327之间的空隙。另外，内插板321的焊锡球325提供在内插板321的安装有芯片322的相反侧。提供在内插板321的布线326通过提供在内插板321的接触孔和焊锡球325电连接在一起。
在倒装芯片法的情形中，即使增加应该连接的焊垫的数量，跟布线接合法相比，可以确保的焊垫之间的间距比较大，所以适合用于终端数多的芯片的连接。
图10D是一个横截面图，表示用倒装芯片法层叠芯片的封装。图10D表示在内插板333上层叠芯片330，331的封装。提供在内插板333上的布线335和芯片330用焊锡球334电连接在一起。另外，芯片330和芯片331的电连接用焊锡球332来实现。
另外，图10A-10D表示的封装使用球状矩阵排列型的内插板，然而本发明并不局限于该类型。也可以使用终端布置在周边的导线架型的内插板。图11是一个斜透射图，表示使用导线架型内插板的封装的横截面结构。
图11表示的封装中，芯片351根据布线接合法和内插板350上的终端352连接在一起。终端352被安排在内插板350的安装有芯片351的那一面。虽然可以用成形树脂353密封芯片351，但在此在暴露出各个终端352的一部分的状态下进行密封。
图12A表示一个封装的横截面图，其中，层叠的芯片用布线接合法连接在一起。图12A表示在内插板362上层叠两个芯片360，361的封装。芯片360和提供在内插板362上的布线363通过和导线364电连接在一起。另外，芯片361和提供在内插板362上的布线363借助导线365电连接在一起。
另外，图12A中，芯片360和芯片361各自和提供在内插板362上的布线通过导线连接在一起，但是，芯片之间也可以用导线互相连接。
图12B表示一个封装之间层叠的例子。在图12B中，安装有芯片的封装370和封装371用焊锡球372电连接，并且，层叠在一起。
当将芯片和芯片层叠并封装在一个内插板的情形和将封装和封装层叠的情形作比较时，前者比后者在可以抑制封装整体的尺寸上具有优势。另一方面，后者跟前者不同，因其可以对整个封装进行电检查，在区分选出合格品后进行层叠，所以具有可以提高成品率的优势。
另外，本发明的封装可以将布线接合法和芯片倒装法组合起来进行芯片的接合。另外，也可以不层叠芯片，而在内插板上并列排列层叠的芯片或单层的芯片来进行接合。
实施方案模式5
本实施方案模式示出一个具体层叠芯片方法的实例。首先，依据实施方案模式1所示的制作方法，制作出直到如图7B所示的，安装有第一层芯片的状态。
另一方面，第二层的芯片也同样地，依据实施方案模式1所示的制作方法，制作出直到如图5D所示的状态。然后，如图13A所示，在焊垫620上制作凸块621。本实施方案模式举出不仅用热压，而且用超声波振动来连接芯片和芯片的例子，从而进行说明。因此，采用有尖头的凸块，而不是单纯球形的凸块。
接下来如图13B所示，涂敷封胶623来覆盖第一层的芯片的焊垫622，随后，使凸块621面对第一层的芯片的焊垫622，然后施压到如图13A所示的第二层的芯片。这种情况下，一边对第二层的芯片施加超声波的振动，一边对凸块621和芯片焊垫622施压。凸块621的尖头插入封胶623并到达焊垫622，在那里该尖头被挤碎并受压于焊垫622。
然后，对封胶实施硬化处理，具体实施加热，辐照紫外线等从而提高芯片和芯片的紧贴性。随后，如实施方案模式1所述，晶化金属氧化膜624。通过该晶化工艺，可以使金属氧化膜624在晶界变得易碎，加强了其脆性。在本实施方案模式中，具体执行420℃-550℃，0.5-5小时左右的加热处理来执行晶化工艺。
随后，如图14A所示，用双面胶带625将第三衬底627粘贴到第一衬底626。然后如图14B所示，将第一衬底626从第二层的芯片628开始以金属氧化膜624为界限进行剥离。
通过上述结构，可以使第一层的芯片629和第二层的芯片628电连接地层叠在一起。
实施例
本实施例以本发明的电子产品之一的移动电话为例，用图15A说明封装实际被搭载到电子产品的情况。
图15A表示的移动电话的模块在印刷线路板812上搭载有控制器801，CPU802，存储器811，电源电路803，声频处理电路829，收发信电路804，以及其他的，电阻，缓冲器，电容元件等元件。另外，屏板(panel)800通过FPC 808(柔性印刷电路，Flexible PrintedCircuit)和印刷线路板812粘附在一起。屏板800上安装有发光元件提供在各个像素的像素单元805，选择该像素单元805具有的像素的扫描线驱动电路806，馈送声频信号到被选中的像素的信号线驱动电路807。
电源电压以及从键盘输入的各种信号通过配备有多个输入终端的印刷线路板用的程序接口(interface，I/F)809馈送到印刷线路板812。另外，用于和天线之间的信号收发信的天线端口(antennaport)810提供在印刷线路板812上。
另外，本实施例用FPC将屏板800连接到印刷线路板812上，然而不一定必须是该结构。也可以采用玻璃上载芯片的COG(Chip OnGlass)方式，在屏板800上直接搭载控制器801，声频处理电路829，存储器811，CPU802或电源电路803。
而且，在印刷线路板812中，存在着形成在各个线路之间的电容器以及线路本身具有的电阻，由此会引起电源电压和信号的噪声或使信号传递变得迟钝。因此，在印刷线路板812上提供诸如电容器或缓冲器之类的各种元件，以便防止电源电压和信号的噪声或防止信号传递变得迟钝。
图15B是图15A所示的模块的方框图。
本实施例中，存储器811包含VRAM832，DRAM825，快闪存储器(flash memory)826。VRAM832存储显示在屏板上的图像数据，DRAM825存储图像数据或声频数据，快闪存储器826存储各种程序。
电源电路803给屏板800，控制器801，CPU802，声频处理电路829，存储器811，收发信电路804提供电源电压。另外，依据屏板的规格，电源电路803也可以装备有电源。
CPU802具有控制信号生成电路820，译码器821，寄存电路822，演算电路823，RAM824，CPU用的接口(interface)835等。通过接口835输入到CPU802的各种信号暂时存储在寄存电路822后，被输入到演算电路823，译码器821等。演算电路823根据输入来的信号进行演算，然后指定传送各种命令的场所。另一方面，输入到译码器821的信号在译码器821处被破译后，被馈送到控制信号生成电路820中。控制信号生成电路820根据输入来的信号生成包含各种指令的信号，该信号被馈送到由演算电路823指定的场所，具体地说，馈送到存储器811，收发信电路804，声频处理电路829以及控制器801等等。
存储器811，收发信电路804，声频处理电路829以及控制器801各自依据接收到的指令进行运作。下文将就其运作进行简单说明。
从键盘831输入的信号通过程序接口809被馈送到搭载在印刷线路板812上的CPU802。控制信号生成电路820依据从键盘831输入的信号，将存储在VRAM832的图像数据转换为预定格式，并馈送到控制器801。
控制器801配合屏板的格式对从CPU802馈送来的包括图像数据的信号执行数据处理，然后馈送到屏板800。控制器801依据从电源电路803输入的电源电压或从CPU输入的各种信号，生成Hsync信号，Vsync信号，时钟信号CLK，交流电压(AC Cont)，并馈送到屏板800。
收发信电路804处理天线833收发到的作为电波的信号，收发信电路804具体包括隔离器，带通滤波器，VCO(压控振荡器，voltagecontrolled oscillator)，LPF(低通滤光片，low pass filter)，耦合器，平衡-不平衡转换器(balun)等的高频电路。收发信电路804依据CPU802的指令，将收发信号中包含声频信息的信号，馈送到声频处理电路829。
依据CPU802的指令被馈送来的包含声频信息的信号在声频处理电路829中被解调成声频信号，并被馈送到扬声器828。另外，从传声器827传送来的声频信号在声频处理电路829中被调制，并依据CPU802的指令被传送到收发信电路804。
控制器801，CPU802，电源电路803，声频处理电路829，存储器811可以作为本发明的封装搭载。本发明只要不是隔离器，带通滤波器，VCO(压控振荡器，Voltage Controlled Oscillator)，LPF(低通滤光片，Low Pass Filter)，耦合器，平衡-不平衡转换器(balun)等的高频电路，可以应用于任何电路。
本发明可以利用比硅片廉价并且大面积的玻璃衬底，因此可以高产量地大量生产低成本芯片，并且可以飞跃性地减少每张芯片的生产成本。此外，衬底可以被反复使用，这样，可以减少每张芯片的生产成本。
另外，总膜厚度在5μm，优选等于或少于2μm的芯片可以被形成，通过不实施造成裂缝以及研磨痕迹原因的背面研磨，芯片可以被制作得极薄。并且，芯片厚度的不均匀是在形成膜时，由于构成芯片的各个膜的不均匀会导致的，这个不均匀多也不过几百nm左右，跟背面研磨处理导致的几-几十μm的不均匀相比，可以被飞跃性地减少。
通过将本发明的封装用于电子产品，可以使电路规模或存储容量更大的芯片被更多地装载到电子产品有限的容积中，这样不但可以实现电子产品的多功能化，而且可以实现电子产品的小体积化，轻巧化。特别是便携用电子产品，由于其小体积化，轻巧化被重视，所以利用本发明的封装是有效的。
本发明用容易被半导体膜吸收并具有可见光或更短波长的脉冲振荡的第一激光辐照半导体膜，并通过该辐照熔化半导体膜从而提高半导体膜的基波的吸收系数。将脉冲振荡型激光作为第一激光，跟利用连续振荡型激光的情况相比，能够飞跃性地获取大的聚束光的面积。然后在上述熔化的状态下辐照具有基波的第二激光，基波的吸收系数被提高的半导体膜高效地吸收第二激光。所以，由于可以取得长度长的聚束光的长轴，可以提高激光晶化的产量，另外，对芯片的设计规则的缓和也有效。
另外，将基波型激光用作为第二激光，可以采用具有相当大的输出能源的激光，比如能够输出100倍或更大于高次谐波能源的激光用来作为第二激光而不用考虑用于转换高次谐波的非线形光学元件的耐性。并且，省略掉由于非线形光学元件的变质而引起的维护方面的繁杂工序。特别是，可以发挥固态激光所具有的可以长期保持无需维护的状态的优势。

Claims (16)

1.一种半导体器件的制作方法，它包括以下步骤：
在第一衬底上形成半导体膜；
对所述半导体膜辐照脉冲激光以及连续波激光，并使被双方辐照的区域重叠从而晶化所述半导体膜；
用所述晶化过的半导体膜形成半导体元件；
在所述半导体元件上粘合第二衬底；
从所述半导体元件去除所述第一衬底；
在所述半导体元件上粘合内插板；以及
从所述半导体元件去除所述第二衬底。
2.一种半导体器件的制作方法，它包括以下步骤：
在第一衬底上形成半导体膜；
对所述半导体膜辐照脉冲激光以及连续波激光，并使被双方辐照的区域重叠从而晶化所述半导体膜；
用所述晶化过的半导体膜形成半导体元件；
在所述半导体元件上粘合第二衬底；
从所述半导体元件去除所述第一衬底；
在所述半导体元件上粘合内插板；
从所述半导体元件去除所述第二衬底；以及
电连接所述内插板和所述半导体元件。
3.一种半导体器件的制作方法，它包括以下步骤：
在第一衬底上形成半导体膜；
对所述半导体膜辐照脉冲激光以及连续波激光，并使被双方辐照的区域重叠从而晶化所述半导体膜；
用所述晶化过的半导体膜形成半导体元件；
在所述半导体元件上粘合第二衬底；
从所述半导体元件去除所述第一衬底；
电连接内插板到所述半导体元件；以及
从所述半导体元件去除所述第二衬底。
4.一种半导体器件的制作方法，它包括以下步骤：
在第一衬底的表面上形成半导体膜；
对所述半导体膜辐照脉冲激光以及连续波激光，并使被双方辐照的区域重叠从而晶化所述半导体膜；
用所述晶化过的半导体膜形成半导体元件；
在所述半导体元件上粘合第二衬底；
在所述第一衬底的背面粘合第三衬底；
从所述半导体元件去除所述第一衬底和所述第三衬底；
粘合内插板到所述半导体元件；
从所述半导体元件去除所述第二衬底；以及
电连接所述内插板和所述半导体元件。
5.一种半导体器件的制作方法，它包括以下步骤：
在第一衬底上形成半导体膜；
对所述半导体膜辐照脉冲激光以及连续波激光，并使被双方辐照的区域重叠从而晶化所述半导体膜；
用所述晶化过的半导体膜形成多个半导体元件；
在所述多个半导体元件上粘合第二衬底；
从所述多个半导体元件去除所述第一衬底；
借助于切割所述第二衬底从所述多个半导体元件分离出一个半导体元件；
粘合内插板到所述半导体元件；以及
从所述半导体元件去除所述第二衬底。
6.一种半导体器件的制作方法，它包括以下步骤：
在第一衬底上形成半导体膜；
对所述半导体膜辐照脉冲激光以及连续波激光，并使被双方辐照的区域重叠从而晶化所述半导体膜；
用所述晶化过的半导体膜形成多个半导体元件；
在所述多个半导体元件上粘合第二衬底；
从所述多个半导体元件去除所述第一衬底；
粘合内插板到所述多个半导体元件；
借助于切割所述第二衬底和所述内插板从所述多个半导体元件分离出一个半导体元件；以及
从所述半导体元件去除所述第二衬底。
7.一种半导体器件的制作方法，它包括以下步骤：
在第一衬底上形成半导体膜；
对所述半导体膜辐照脉冲激光以及连续波激光，并使被双方辐照的区域重叠从而晶化所述半导体膜；
用所述晶化过的半导体膜形成多个半导体元件；
在所述多个半导体元件上粘合第二衬底；
从所述多个半导体元件去除所述第一衬底；
粘合内插板到所述多个半导体元件；
从所述多个半导体元件去除所述第二衬底；以及
借助于切割所述内插板从所述多个半导体元件分离出一个半导体元件。
8.根据权利要求1至7中任一项的半导体器件的制作方法，其中在所述第一衬底和所述半导体膜之间依次形成金属膜，金属氧化膜和绝缘膜。
9.根据权利要求1至7中任一项的半导体器件的制作方法，其中所述脉冲激光是对所述半导体膜具有吸收系数至少为1×104cm-1的波长。
10.根据权利要求8的半导体器件的制作方法，其中所述制作方法进一步包括借助实施加热处理来晶化所述金属氧化膜的步骤。
11.根据权利要求8的半导体器件的制作方法，其中所述形成半导体元件的方法包括借助实施加热处理来晶化所述金属氧化膜的步骤。
12.根据权利要求8的半导体器件的制作方法，其中所述金属氧化膜是借助氧化所述金属膜的表面而形成。
13.根据权利要求1至7中任一项的半导体器件的制作方法，其中所述脉冲激光是二次谐波激光。
14.根据权利要求1至7中任一项的半导体器件的制作方法，其中所述连续波激光是基波激光。
15.根据权利要求1至7中任一项的半导体器件的制作方法，其中相对于所述半导体膜移动所述脉冲激光辐照区以及所述连续波激光辐照区，所述元件形成在与所述激光的移动方向相垂直的所述连续波激光的辐照区的宽辐的范围内。
16.根据权利要求1 5的半导体器件的制作方法，其中所述连续波激光的辐照区的辐宽在10mm-50mm的范围内。
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US8212364B2 (en) 2012-07-03
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US7056810B2 (en) 2006-06-06
EP1432022A3 (en) 2008-01-23
TWI330399B (en) 2010-09-11
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