CN100389494C - IC package and its preparing process - Google Patents

IC package and its preparing process Download PDF

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Publication number
CN100389494C
CN100389494C CNB021203679A CN02120367A CN100389494C CN 100389494 C CN100389494 C CN 100389494C CN B021203679 A CNB021203679 A CN B021203679A CN 02120367 A CN02120367 A CN 02120367A CN 100389494 C CN100389494 C CN 100389494C
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China
Prior art keywords
chip
layer
substrate
integrated circuit
manufacture craft
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Expired - Lifetime
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CNB021203679A
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Chinese (zh)
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CN1381889A (en
Inventor
陈国祚
宫振越
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Via Technologies Inc
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Via Technologies Inc
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Abstract

The present invention relates to an integrated circuit package and a manufacture technique thereof. The present invention is characterized in that a chip is attached to the surface of a substrate or attached to a concave surface layer of the substrate, and the substrate is provided with at least one patterned circuit layer and a plurality of through holes in which conductive material is filled, so solder pads on the active surface of the chip can be electrically connected with the patterned circuit layer through the through holes. When the integrated circuit package is used for ball grid array type package, a plurality of solder balls can be respectively arranged on a plurality of solder ball pads on the patterned circuit layer, so the chip can orderly penetrate through the circuit layer and the solder balls of an increased circuit layer, and can be electrically connected with the outside.

Description

The manufacture craft of integrated circuit encapsulation
Technical field
The invention relates to a kind of integrated circuit (Integrated Circuit, IC) Feng Zhuan manufacture craft, and particularly relevant for a kind of to increase the manufacture craft that a layer circuit (Build-Up Circuit) replaces the integrated circuit encapsulation of known substrate (Substrate).
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry makes electronic product more humane, with better function constantly weed out the old and bring forth the new.Yet various products towards light, thin, short, little trend design, use to provide more easily invariably.The manufacturing of electronic product is until finish, considerable role is being played the part of in integrated circuit (IC) encapsulation, and the kenel of integrated circuit (IC) encapsulation has multiple, such as being bilateral pin package (DualIn-line Package, DIP) form, ball lattice array (Ball Grid Array, BGA) packing forms, subsides band engage (Tape Automatic Bonding) packing forms etc. automatically, and every kind of packing forms all has its particularity.
(Ball Grid Array BGA) encapsulates the mode of utilizing soldered ball (Solder Ball) to be covered with the floor space of whole base plate (Substrate) to ball lattice array type, replaces the pin of traditional conductive metal frames (Lead frame).It is with routing (Wire Bonding) or cover the mode of crystalline substance (Flip Chip), the contact of chip is connected to contact on the substrate, and utilize the inside coiling of substrate that contact is dispersed to substrate surface, be connected to substrate bottom surface by guide hole (via) again, at last soldered ball planted the contact that connects (Planting) substrate bottom surface respectively.Because the encapsulation of ball lattice array type can utilize the layout of the floor space of whole base plate as contact, so have the advantage of high pin number (High PinCount).In addition, when reflow (Reflow) operation, surface tension after the soldered ball fusion can produce the phenomenon of self-calibrating (Self Alignment), so the aligning accuracy of soldered ball is less demanding, add good, the good electrical characteristic of bond strength, make ball lattice array type be encapsulated into one of main flow of present integrated circuit (IC) encapsulation.
Please refer to Fig. 1, it is the profile of known a kind of ball lattice array type encapsulation.Ball lattice array type encapsulation 100 back sides with chip 200 are attached on the substrate 110, and with the formed lead 120 of routing (WireBonding) mode, make weld pad (the die pad) 202 of chip 200 electrically connect mutually with the contact 112 of substrate 110, then with encapsulating material 130 coating chips 200, lead 120 and contact 112, respectively soldered ball (solder ball) 140 is planted on the solder ball pad 114 that is connected to substrate 110 again, make chip 200 can see through the internal wiring 116 and the soldered ball 140 of lead 120, substrate 110 in regular turn, and electrically connect mutually with external circuitry.
Other please refer to Fig. 2, and it is the profile of known another kind of ball lattice array type encapsulation.Different with Fig. 1 is, ball lattice array type encapsulation 101 utilizes covers crystalline substance (Flip Chip, F/C) mode, on the weld pad 202 of chip 200, form earlier projection (bump) 204 respectively, and directly be engaged in the contact 112 of substrate 110 with projection 204, make chip 200 can see through the internal wiring 116 and the soldered ball 140 of projection 204, substrate 110 in regular turn, and electrically connect mutually with external circuitry.
Yet, in the known ball lattice array type encapsulation, if utilize lead (wire) to connect the contact of the weld pad of chip to substrate, because the electrical resistance (impedance) of lead is higher, will causes the time delay (time delay of signals) of signal and reduce the performance (performance) of chip.In addition,, then must additionally on the weld pad of chip, form projection if connect the contact of the weld pad of chip to substrate to cover brilliant mode, and with the accurate contraposition of the contact of substrate after engage, so will increase manufacturing process steps, and the raising manufacturing cost.
In addition, in the encapsulation of ball lattice array type, because the chip of desire encapsulation all belongs to the chip of high pin number, therefore no matter be the mode of utilizing routing, or to cover the contact of next electrical connection-core sheet weld pad of brilliant mode and substrate, the substrate of (Fine Pitch) contact that has little spacing must be used, just the requirement that high pin is counted chip can be met.Traditional printing circuit board (Printed Circuit Board, PCB) live width (trace width) is about 100 microns, and the spacing of contact and contact (pitch) is about between 800～1200 microns, yet, ball lattice array type encapsulates the substrate of employed little spacing contact, its live width is about 30 microns, and the spacing of weld pad and weld pad is about 150 microns.Therefore with the traditional printing circuit board in comparison, the substrate manufacturing costs of this type of little spacing contact is higher, rough accounting for more than at least two of ball lattice array type encapsulation manufacturing cost becomes is applicable to that to cover brilliant its manufacturing cost of base plate for packaging then expensive more.
Summary of the invention
The object of the present invention is to provide a kind of manufacture craft of integrated circuit encapsulation, its can omit known substrate and with chip between be connected manufacture craft, routing or cover brilliant manufacture craft for example, meet the contact spacing that originally was applied to substrate simultaneously, so can reduce the packaging cost of integrated circuit, and can significantly promote the operational effectiveness of chip, and the rate of heat dispation of quickening encapsulating structure.In addition, do not having under the limitation of chip-covered boss, the operational effectiveness of chip is with easier lifting.
Based on purpose of the present invention, the invention provides the manufacture craft of a kind of integrated circuit encapsulation, a substrate is provided, this substrate has one first and at least one depression, and wherein this depression is depressed in this first of this substrate; At least one chip is provided, and this chip has an active surface and a back side, and wherein this chip is attached at the bottom of this depression with this back side, and this chip has more a plurality of weld pads, and it is positioned at this active surface of this chip; Form one and increase layer circuit layer on this substrate, wherein this increases a layer circuit layer and has at least one insulating barrier, at least one patterned line layer and a plurality of perforation, wherein this insulating barrier is between this active surface and this patterned line layer, and be filled between this chip and this substrate, and corresponding respectively those weld pads of those perforations and run through this insulating barrier, and has a conductive material among those perforations, and this patterned line layer electrically connects with those weld pads mutually with this conductive material, and this patterned line layer of part extends to this zone in addition, active surface top of this chip.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended icon, elaborate.
Description of drawings
Fig. 1 is the profile of known a kind of ball lattice array type encapsulation;
Fig. 2 is the profile of known another kind of ball lattice array type encapsulation;
Fig. 3 A～3I is the flow process profile of the integrated circuit encapsulation of preferred embodiment of the present invention in regular turn;
Fig. 4 A, Fig. 4 B are for forming the flow process profile of conductive material and line layer;
Fig. 5 A, Fig. 5 B are for forming the flow process profile of line layer;
Fig. 6 is a kind of integrated circuit encapsulation of preferred embodiment of the present invention, and it has the profile of the substrate of internal circuit;
Fig. 7 is the another kind of integrated circuit encapsulation of preferred embodiment of the present invention, and it has the profile of plane substrate.
Label declaration:
100,101: ball lattice array type encapsulation 110: substrate
112: contact 114: solder ball pad
116: internal wiring 120: lead
130: encapsulating material 140: soldered ball
200: chip 202: weld pad
204: projection
300,301: integrated circuit encapsulation 310: substrate
312: surface 314: depression
316: internal wiring 320: insulating barrier
322: perforation 330: thin metal layer
340: metal level 342: line layer
344: filling part 346: solder ball pad
348: conductive material 350: protective layer
360: soldered ball 400: chip
402: active surface 404: the back side
406: weld pad 408: viscose glue
501: photoresist layer 503: line layer
505: electric capacity
Embodiment
Please refer to Fig. 3 A～Fig. 3 I, it is the flow chart of the integrated circuit encapsulation of preferred embodiment of the present invention in regular turn.As shown in Figure 3A, at first provide a substrate 310, its surface optionally has a depression 314, and depression 314 is positioned on the substrate 310, and is depressed in the surface 312 of substrate 310, and the position of this depression 314 does not limit the centre that is positioned at substrate 310.In addition, chip 400 has an active surface 402 and a corresponding back side 404, and be attached at the bottom of depression 314 with its back side 404, but the position of chip 400 is not limited to the bottom at depression 314, also can be positioned at the surface 312 of substrate 310, and expose the active surface 402 of chip 400, the active surface of chip 400 (Active Surface) 402 then has a plurality of weld pads 406, in order to export into contact as signal, wherein active surface 402 is the one side with device (device) that refers to chip 400.In addition, the attaching mode of chip 400 can utilize viscose glue (paste) 408 to be pasted on the bottom of depression 314, wherein viscose glue 408 comprises conductive adhering substance, as elargol (silver paste) or conducting resinl, or with dielectric adhering substance, as paste band (adhesive tape) replacement viscose glue 408, and chip 400 is attached at the bottom of depression 314.
Shown in Fig. 3 B, chip 400 is attached at after the substrate 310, then form an insulating barrier 320 on substrate 310 and chip 400, partial insulative layer 320 will be filled between chip 400 and the depression 314 simultaneously, and the method that forms insulating barrier 320 comprises with rotary coating (Spin Coating), screen painting (Screen Printing) and roll extrusion coating modes such as (RollerCoating), and the material of insulating barrier 320 then comprise light-sensitive medium (Photo-Imageable Dielectric, PID), glass (glass), resin (resin) or other curable material.Then, shown in Fig. 3 C, after forming insulating barrier 320, form a plurality of perforations 322 among insulating barrier 320, in order to the weld pad 406 that exposes chip 400, the method that wherein forms perforation (via) 322 then comprises sensitization pore-forming (Photo-Via), radium-shine hole burning (Laser Ablation) and plasma pit modes such as (Plasma Etching).
Shown in Fig. 3 D, on insulating barrier 320 and weld pad 406, comprehensive formation one thin metal layer 330 in order to as the Seed Layer (Seed Layer) of electroplating (Electroplating) usefulness, for example forms a copper foil layer as thin metal layer 330 with chemical copper.Then, shown in Fig. 3 E, for example in the mode of plating, comprehensive formation one metal level 340 is filled perforation 322 simultaneously on thin metal layer 330.Afterwards, shown in Fig. 3 F, metal level 340 is given planarization, this moment, metal level 340 can roughly be divided into line layer 342 and filling part 344, wherein filling part 344 fills up perforation 322, the method that metal level 340 is given planarization then can be utilized cmp (Chemical Mechanical Polishing, mode CMP).Under the less demanding situation of surface smoothness, the flow process of this planarization can be omitted.
Shown in Fig. 3 G, then for example in the mode of lithography, remove part line layer 342, by patterned line layer 342, make the line layer 342 and insulating barrier 320 formations of patterning increase a layer circuit layer (Build-up Circuit) 370, and can repeat above-mentioned steps and form multilayer and increase layer circuit layer 370, to meet required winding placement design.(for example the lead pin of Xing Chenging directly engages with conducting resinl with the film type lead (Tape) with lead) then can omit protective layer, solder ball pad and soldered ball manufacture craft when non-ball lattice array type encapsulates.When integrated circuit encapsulation 300 is applied to the encapsulation of ball lattice array type; then shown in Fig. 3 H; can utilize screen painting, coating back little shadow (Photolithography) or other mode; form a patterned protective layer; a welding cover layer (Solder Mask) for example; material forms solder ball pad 346 such as being anti-welding green lacquer in order to expose part line layer 342.For another example shown in Fig. 3 I, soldered ball 360 is planted meet (Planting) on the solder ball pad 346 of correspondence respectively, and finish the integrated circuit encapsulation 300 of ball lattice array type.
Shown in Fig. 3 G, the back side 404 of chip 400 is when fitting with substrate 310, though make every effort to align with viscose glue 410, must not align, insulating barrier 320 is on the not part of perforation and the surface of metal level 340, though keep smooth comparatively favourable to follow-up manufacture craft, also uninevitable all is smooth.Shown in Fig. 3 I, the spacing of soldered ball 360 must not be a fixed value for another example, can adjust according to actual needs, and line layer 342 can freely extend at the active surface 402 of chip 400 and 312 on the surface of substrate 310.
Shown in Fig. 3 F, on manufacture craft,, also can utilize the twice manufacture craft except forming metal level 340 with as line layer 342 and the filling part 344, line layer 342 and filling part 344 are made at twice.Therefore, we can be after the manufacture craft shown in Fig. 3 D be finished, just after formation thin metal layer 330 is on insulating barrier 320 and weld pad 406, can be shown in Fig. 4 A, one conductive material 348 is inserted among the perforation 322, and its effect is identical with the filling part 344 of the metal level 340 of Fig. 3 F, and the mode of inserting can be used screen painting, can use conducting resinl as for 348 of conductive material, for example elargol, copper glue etc.Then, shown in Fig. 4 B, comprehensive again formation one line layer 342 is on thin metal layer 330 and conductive material 348, and the method for formation line layer 342 can be used plating, and manufacturing process steps after this is then identical with Fig. 3 G～3I, no longer repeats to give unnecessary details in this.
Shown in Fig. 3 G, form the method for line layer 342, can be coated with a last photoresist layer 501 earlier by the step of Fig. 3 D, and can utilize the mode of exposure and development to come this photoresist layer 501 of patterning, shown in Fig. 5 A.Then, the mode to electroplate grows line layer 503 in the part that does not have photoresistance, shown in Fig. 5 B again.Then, remove photoresist layer 501, and of short duration metal etch in addition, the thin conductive layer under the photoresist layer 501 330 is removed, can obtain the line layer 342 of the patterning of Fig. 3 G, and manufacturing process steps after this, equally shown in Fig. 3 H～3I, do not give unnecessary details repeating in this.
Please refer to Fig. 3 I, the material of substrate 310 can comprise metal, glass and high molecular polymer (polymer) or other material.Because chip 400 time can produce high heat in running, therefore, when the material of substrate 310 is the good material of metal or thermal conductivity, can increase the heat conduction and heat radiation speed of chip 400, to promote the operational effectiveness of chip 400.Other please refer to Fig. 6, and it is the profile of integrated circuit encapsulation with substrate of internal wiring.Substrate 310 also can have an internal wiring 316, and can be by increasing the design of filling part 344, make the internal wiring 316 of substrate 310 can pass through filling part 344 ', and electrically connect the weld pad 406 of chip 400 or the line layer 342 of patterning, thereby make the coiling design of integrated circuit encapsulation 301 of ball form array will have bigger elastic space.
In addition, can be after Fig. 3 H, repeat the manufacture craft of Fig. 3 C～Fig. 3 H, then can make the circuit of multilayer line layer 342-1,342-2, and the line layer 342-2 that this has more except can making design freedom change greatly, also can be used as ground connection or power plane, or in interplanar generation electric capacity 505, in order to usefulness as the electrical characteristics of adjusting product.
Please refer to Fig. 7, it has the integrated circuit encapsulation for the another kind of preferred embodiment of the present invention, and it has the profile of plane substrate.With Fig. 6 in comparison, both topmost difference are that insulating barrier 320-1 is inequality with the thickness on the surface 312 of substrate 310 on the surface 402 of chip 400, other part is then similar, no longer describes in detail in this.In addition, if select insulating barrier 320 thickness when identical, then can adjust the thickness of line layer 342-1 equally, or improve the evenness of each layer more than the insulating barrier 320-1 on the surface 312 of the surface 402 of chip 400 and substrate 310.
The feature of integrated circuit encapsulation of the present invention is attached at chip the depression bottom of substrate or the surface of substrate earlier, then on substrate and chip, directly form and increase a layer circuit layer, and soldered ball is disposed at the solder ball pad of the line layer that increases layer circuit layer, make chip be able to see through in regular turn inside coiling and the soldered ball that increases layer circuit layer, and electrically connect mutually with the external world.
From the above, when integrated circuit package application of the present invention when ball lattice array type encapsulates, can omit the required substrate of known ball lattice array type encapsulation with little spacing contact, and can omit the electronic packaging of first level (Level 1), promptly with the routing manufacture craft or cover brilliant manufacture craft, chip is connected to the encapsulation of the level of base plate for packaging, and directly to increase the direct weld pad and the soldered ball that connects chip of inside coiling of layer circuit layer, lead connects or projection connects the higher electrical resistance that is produced so can significantly reduce, and helps to promote the operational effectiveness of chip.
In sum, integrated circuit encapsulation of the present invention has following advantage:
(1) integrated circuit encapsulation of the present invention directly extends to chip zone in addition with line layer with highdensity chip pad, directly to make the welded spot pitch of the weld pad (or soldered ball) that can arrive printed circuit board (PCB) greatly, can directly replace the encapsulation that high pin is counted chip, so can significantly reduce packaging cost.
(2) integrated circuit of the present invention is encapsulated on the chip and directly forms at least one layer circuit layer that increase, under need not the substrate with little spacing contact of application of known, and the integrated circuit encapsulation that can produce the distributing position that meets original solder joint equally.
(3) integrated circuit encapsulation of the present invention increases layer known substrate with little spacing contact of circuit layer replacement with it, thereby omits higher substrate of known cost and assembling manufacture craft thereof, so can reduce the packaging cost of chip.
(4) integrated circuit encapsulation of the present invention directly directly connects the weld pad and the soldered ball of chip with the inside coiling that increases layer circuit layer, for example beat the higher electrical resistance that gold thread connects or the projection connection is produced so can significantly reduce, and help to promote the operational effectiveness of chip.
(5) when integrated circuit of the present invention encapsulates the material of the substrate of selecting for use metal or the good material conduct of thermal conductivity to hold chip, because substrate is coated on the periphery of chip with its depression, so help to increase the efficient of the heat radiation of chip, and then promote the operational effectiveness of chip.If when selecting metal for use, the above-mentioned advantage of tool not only, and for electromagnetic interference (Electro-MagneticInterference, screening effect EMI) is excellent, the substrate that can utilize this metal material simultaneously is as grounding function, and then promotes the overall package performance.
(6) integrated circuit of the present invention encapsulates the substrate that optional usefulness has internal wiring, and internal wiring is electrically connected the weld pad of chip or increase the line layer of layer circuit layer, makes the coiling design of integrated circuit encapsulation will have bigger elastic space.
(7) manufacture craft of integrated circuit of the present invention encapsulation can be carried out the making of build-up circuit to single crystal grain, and the device (set) that the great number of grains of adhering simultaneously on also can large-area substrate is finished carries out manufacture craft to be handled, significantly to reduce production costs.
Though the present invention with a preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims.

Claims (11)

1. the manufacture craft of integrated circuit encapsulation is characterized in that: comprise at least:
One substrate is provided, and this substrate has one first and at least one depression, and wherein this depression is depressed in this first of this substrate;
At least one chip is provided, and this chip has an active surface and a back side, and wherein this chip is attached at the bottom of this depression with this back side, and this chip has more a plurality of weld pads, and it is positioned at this active surface of this chip;
Form one and increase layer circuit layer on this substrate, wherein this increases a layer circuit layer and has at least one insulating barrier, at least one patterned line layer and a plurality of perforation, wherein this insulating barrier is between this active surface and this patterned line layer, and be filled between this chip and this substrate, and corresponding respectively those weld pads of those perforations and run through this insulating barrier, and has a conductive material among those perforations, and this patterned line layer electrically connects with those weld pads mutually with this conductive material, and this patterned line layer of part extends to this zone in addition, active surface top of this chip.
2. the manufacture craft of integrated circuit encapsulation as claimed in claim 1 is characterized in that: wherein this insulating barrier of part is filled between this chip and this depression.
3. the manufacture craft of integrated circuit encapsulation as claimed in claim 1 is characterized in that: wherein form this method that increases layer circuit layer and comprise:
Form an insulation material layer, cover this active surface and fill up this chip and this substrate between the space;
This insulation material layer of patterning is to form this insulating barrier and those perforations that expose those weld pads;
Form a conductive material layer and cover this insulating barrier, and fill up those perforations; And
This conductive material layer of patterning is to form this patterned line layer.
4. the manufacture craft of integrated circuit encapsulation as claimed in claim 3, it is characterized in that: the method that wherein forms this insulation material layer comprises that rotary coating, screen painting and roll extrusion are coated with one of them.
5. the manufacture craft of integrated circuit as claimed in claim 3 encapsulation is characterized in that: wherein the material of this insulation material layer comprise light-sensitive medium, glass and resin one of them.
6. the manufacture craft of integrated circuit encapsulation as claimed in claim 3, it is characterized in that: wherein the material of this insulation material layer comprises curable materials.
7. the manufacture craft of integrated circuit encapsulation as claimed in claim 3, it is characterized in that: the method that wherein forms those perforations comprises sensitization pore-forming, radium-shine hole burning and plasma pit.
8. the manufacture craft of integrated circuit encapsulation as claimed in claim 1 is characterized in that: also comprise forming a plurality of solder ball pads on this patterned line layer.
9. the manufacture craft of integrated circuit encapsulation as claimed in claim 8 is characterized in that: also comprise forming a plurality of soldered balls respectively on those solder ball pads.
10. the manufacture craft of integrated circuit encapsulation as claimed in claim 1, it is characterized in that: wherein this substrate has more an internal circuit.
11. the manufacture craft of integrated circuit as claimed in claim 10 encapsulation is characterized in that: wherein this internal circuit electrically connects with one of those weld pads of this chip at least.
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CN106531644B (en) * 2016-12-09 2020-01-24 华进半导体封装先导技术研发中心有限公司 Chip packaging process and packaging structure

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