CN100416822C - Static discharge protective circuit - Google Patents
Static discharge protective circuit Download PDFInfo
- Publication number
- CN100416822C CN100416822C CNB021471983A CN02147198A CN100416822C CN 100416822 C CN100416822 C CN 100416822C CN B021471983 A CNB021471983 A CN B021471983A CN 02147198 A CN02147198 A CN 02147198A CN 100416822 C CN100416822 C CN 100416822C
- Authority
- CN
- China
- Prior art keywords
- trap
- circuit
- esd protection
- npn
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The present invention discloses an electrostatic discharge protection circuit. The electrostatic discharge protection circuit comprises an NPN darlington circuit and an N-shaped MOS-transistor, wherein a drain electrode of the N-shaped MOS-transistor is connected with the input end of the NPN darlington circuit, a source electrode of the N-shaped MOS-transistor is connected with the control end of the NPN darlington circuit, and a grid electrode of the N-shaped MOS-transistor is connected with the output end of the NPN darlington circuit.
Description
Technical field
The present invention relates to a kind of ESD protection circuit, relate in particular to a kind of NPN Darlington (Darlington) ESD protection circuit.
Background technology
Static (Static Electricity) can be described as immanent, and the object friction of any two unlike materials all might produce static.And the instantaneous pressure that when the object that has static touches the metal pin of IC (integrated circuit), is produced discharge, can influence internal circuit (internalcircuit) via the metal pin, thus via static discharge (electrostatic discharge, ESD) caused infringement causes the inefficacy of electronic system probably.The major function of ESD protection circuit is when static discharge takes place; before pulse (pulse) the no show internal circuit of static discharge, start in advance; promptly to eliminate too high voltage; and then reducing the destruction that the static discharge phenomenon is caused, this protective circuit also must can be born the energy of electrostatic discharge pulses and can not caused damage to protective circuit itself simultaneously.Be exactly that this ESD protection circuit must only just can move when static discharge takes place in addition, other time then is failure to actuate, in order to avoid influence the normal operation of electronic system.
Please refer to Fig. 1, Fig. 1 is the circuit diagram of the ESD protection circuit of existing bipolar junction transistor.As shown in Figure 1; in bipolar CMOS transistor (BiCMOS) technology; with a NPN bipolar junction transistor (NPN BJT) as ESD protection circuit; the base stage of this NPN bipolar junction transistor (base) is floated; emitter (emitter) ground connection; collector electrode (collector) then is connected to the input attenuator (input pad) or the voltage source attenuator (VDD pad) of an internal circuit; when the input attenuator of this internal circuit or voltage source attenuator are disturbed by an electrostatic discharge pulses; this NPN bipolar junction transistor promptly punctures conducting, with static discharge current ground connection.Use open base NPN bipolar junction transistor less as the input capacitance of NPN bipolar junction transistor as the advantage of ESD protection circuit; so NPN bipolar junction transistor conducting fast; but the electric current that the NPN bipolar junction transistor can draw is limited; so the poor effect of electrostatic discharge (ESD) protection is to use the base stage shortcoming of NPN bipolar junction transistor as ESD protection circuit of floating.
Please refer to Fig. 2, Fig. 2 is the circuit diagram of the ESD protection circuit of existing metal oxide semiconductor transistor.As shown in Figure 2; with a metal oxide semiconductor transistor (MOS) as ESD protection circuit; the grid of this metal oxide semiconductor transistor (gate) is connected in its source electrode (source) back ground connection; its drain electrode (drain) is connected to the input attenuator or the voltage source attenuator of an internal circuit; when the input attenuator of this internal circuit or voltage source attenuator were disturbed by an electrostatic discharge pulses, this metal oxide semiconductor transistor made electrostatic induced current ground connection with conducting.Use the advantage of grounded-grid metal oxide semiconductor transistor can draw bigger electric current as metal oxide semiconductor transistor; effect for electrostatic discharge (ESD) protection is preferable; but because the input capacitance of metal oxide semiconductor transistor is bigger; so the service speed of metal oxide semiconductor transistor is slower; possibly can't provide the internal electron system to protect completely, be to use the shortcoming of grounded-grid metal oxide semiconductor transistor as ESD protection circuit.
From the above, use base stage to float the NPN bipolar junction transistor as ESD protection circuit, the effect of electrostatic discharge (ESD) protection is not good though service speed is fast; And use the grounded-grid metal oxide semiconductor transistor can improve the shortcoming that base stage is floated the NPN bipolar junction transistor as ESD protection circuit; obtain the effect of electrostatic discharge (ESD) protection preferably, but because there is bigger input capacitance to make service speed be restricted.
Other relevant technology can be with reference to United States Patent (USP) 5,530, and 612, United States Patent (USP) 5,986,863, United States Patent (USP) 6,028,758, United States Patent (USP) 6,320,735, United States Patent (USP) 6,400,540, U.S. patent application case 20020027755A1, and European patent 651,490, European patent 477,429.
Summary of the invention
Therefore main purpose of the present invention provides a NPN Darlington ESD protection circuit, to address the above problem.
The invention provides a kind of ESD protection circuit, it comprises a NPN Darlington circuit, and a N type metal oxide semiconductor transistor.This NPN Darlington circuit has an input, a control end and an output, its output head grounding.This N type metal oxide semiconductor transistor drain is connected in the input of this NPN Darlington circuit, the transistorized source electrode of this N type metal oxide semiconductor is connected in the control end of this NPN Darlington circuit, and the transistorized grid of this N type metal oxide semiconductor is connected in the output of this NPN Darlington circuit.
Description of drawings
Fig. 1 is the circuit diagram of the ESD protection circuit of existing bipolar junction transistor;
Fig. 2 is the circuit diagram of the ESD protection circuit of existing metal oxide semiconductor transistor;
Fig. 3 is the circuit diagram of ESD protection circuit of the present invention;
Fig. 4 A and Fig. 4 B are the schematic diagram of ESD protection circuit of the present invention component structure in ambipolar complementary transistor technology;
Fig. 5 A and Fig. 5 B are the schematic diagram of ESD protection circuit of the present invention component structure in complementary transistor technology;
Fig. 6 connects the circuit diagram of voltage source attenuator for ESD protection circuit of the present invention; And
Fig. 7 is the circuit diagram of the complementary ESD protection circuit of the present invention.
Description of reference numerals in the accompanying drawing is as follows:
10 ESD protection circuits of the present invention
12N type metal oxide semiconductor transistor
14 the one NPN bipolar junction transistors
16 the 2nd NPN bipolar junction transistors
18 first resistance, 20 second resistance
22 input attenuators, 24 voltage source attenuators
The complementary circuit of 26 ESD protection circuits of the present invention
30P type substrate 32P type epitaxial loayer or N type epitaxial loayer
34N+ buried layer 36N trap
The 38P trap 40N+ utmost point
42 insulating barrier 50P type substrates
52N deep trap 54P trap
The 56N+ utmost point 58 insulating barriers
Embodiment
Please refer to Fig. 3, Fig. 3 is the circuit diagram of ESD protection circuit of the present invention.ESD protection circuit 10 of the present invention comprises a N type metal oxide semiconductor transistor (NMOS) 12, one the one NPN bipolar junction transistors (NPN BJT) 14, one the 2nd NPN bipolar junction transistors, 16, one first resistance 18 and one second resistance 20.Wherein the collector electrode (collector) of two NPN bipolar junction transistors 14,16 is connected together, the emitter of the one NPN bipolar junction transistor 14 (emitter) is connected in the base stage (base) of the 2nd NPN bipolar junction transistor 16, form a NPN Darlington circuit (NPNDarlington circuit), the base stage of the one NPN bipolar junction transistor 14 is the control end of this NPN Darlington circuit, its current collection is the input of this NPN Darlington circuit very, and the emission of NPN bipolar junction transistor 16 is the output of this NPN Darlington circuit very.The drain electrode (drain) of N type metal oxide semiconductor transistor 12 is connected in the input of this NPN Darlington circuit, the grid (gate) of N type metal oxide semiconductor transistor 12 is connected in the output of this NPN Darlington circuit, and source electrode (source) is connected in the control end of this NPN Darlington circuit.The input of this NPN Darlington circuit is connected in the input attenuator (I/P) 22 of an internal circuit, its output is connected in earth point, and first resistance 18 is connected between the base stage and earth point of a NPN bipolar junction transistor 14, and second resistance 20 is connected between the base stage and earth point of the 2nd NPN bipolar junction transistor 16.When the input attenuator 22 of this internal circuit is disturbed by an electrostatic discharge pulses; N type metal oxide semiconductor transistor 12 is triggering and conducting immediately; make a part of electrostatic induced current flow through first resistance 18 and form a pressure drop at its two ends; this pressure drop drives a NPN bipolar junction transistor 14 conductings; make the electrostatic induced current of a part cross second resistance 20 and form another pressure drop again at its two ends; this pressure drop drives 16 conductings of the 2nd NPN bipolar junction transistor; make most electrostatic induced current through path ground thus, reach the effect of electrostatic discharge (ESD) protection.In the present embodiment, the emitter width of the 2nd NPN bipolar junction transistor 16 is the twice of a NPN bipolar junction transistor 14, mainly be in order to reach better static discharge effect, and first resistance 18 and second resistance 20 just are used for forming a pressure drop with the conducting of driving N PN bipolar junction transistor, are 500 ohm in this resistance value of selecting for use.The resistance value of the emitter width of the one NPN bipolar junction transistor 14 and the 2nd NPN bipolar junction transistor 16 and first resistance 18 and second resistance 20 also can be selected suitable value for use according to actual needs, all should belong to the scope that the present invention is contained.
Please refer to Fig. 4 A and Fig. 4 B, Fig. 4 A and Fig. 4 B are the schematic diagram of ESD protection circuit of the present invention component structure in bipolar CMOS transistor (BiCMOS) technology.Shown in Fig. 4 A, in the bipolar CMOS transistor technology, on a P type substrate (P-substrate) 30, generate a P type epitaxial loayer (P-epi layer) or a N type epitaxial loayer (N-epilayer) 32 earlier, then reinject a N+ buried layer (N+buried layer) 34 on epitaxial loayer 32, on N+ buried layer 34, form a P trap (P well) 38, then inject a N trap (NW+sink) 36 around the P trap 38 and be formed at the upside of N+ buried layer 34 in mode P trap 38 and 30 isolation of P type substrate, the injection N+ utmost point (N+node) 40 in P trap 38 at last around P trap 38.In above-mentioned structure, NPN bipolar junction transistor be with the N+ utmost point 40 as emitter, P trap 38 is as base stage, and N+ buried layer 34 is as collector electrode, shown in Fig. 4 A.N type metal oxide semiconductor transistor then is to serve as drain electrode and source electrode with two N+ utmost points 40, and forms an insulating barrier 42 as grid, shown in Fig. 4 B above the passage of two N+ utmost points 40.N type metal oxide semiconductor transistor in P trap 38 is completely cut off by N trap (NW+sink) 36 and N+ buried layer 34, as shown in Figure 3 surround N type metal oxide semiconductor transistor 12 expressions with circle.Because present embodiment adopts above-mentioned special isolation structure,, reach the effect of electrostatic discharge (ESD) protection preferably so can come driving N PN Darlington circuit as a trigger (trigger) with N type metal oxide semiconductor transistor.
Please refer to Fig. 5 A and Fig. 5 B, Fig. 5 A and Fig. 5 B are applied in the schematic diagram of component structure in CMOS transistor (CMOS) technology for ESD protection circuit of the present invention.Similarly, in CMOS transistor technology, also can utilize a N deep trap (deep Nwell) 52 to isolate a P trap 54 and a P type substrate 50.Shown in Fig. 5 A, on P type substrate 50, inject N deep trap 52 earlier, the P trap 54 that then reinjects on N deep trap 52 injects the N+ utmost point 56 at last in P trap 54.NPN bipolar junction transistor be with the N+ utmost point 56 as emitter, P trap 54 is as base stage, and N deep trap 52 is as collector electrode, shown in Fig. 5 A.N type metal oxide semiconductor transistor then is to serve as drain electrode and source electrode with two N+ utmost points 56, and forms an insulating barrier 58 as grid, shown in Fig. 5 B above the passage of two N+ utmost points.N type metal oxide semiconductor transistor in P trap 54 is completely cut off by N deep trap 52, as shown in Figure 3 surround N type metal oxide semiconductor transistor 12 expressions with circle.
Please refer to Fig. 6, Fig. 6 connects the circuit diagram of voltage source attenuator 24 for ESD protection circuit of the present invention.For making explanation more succinct, among Fig. 6 with Fig. 3 among components identical identical functions is arranged and uses identical label.Among Fig. 3, the input of this NPN Darlington circuit is connected in the input attenuator 22 of internal circuit, and when the input attenuator 22 of this internal circuit was disturbed by an electrostatic discharge pulses, ESD protection circuit 10 of the present invention starts immediately made electrostatic induced current ground connection.Similarly; the input of the NPN Darlington circuit in the ESD protection circuit 10 of the present invention also can be connected in a voltage source attenuator 24; when voltage source attenuator 24 was disturbed by an electrostatic discharge pulses, ESD protection circuit 10 of the present invention can start immediately electrostatic induced current is imported earth point.General human body discharging model (Human-Body Model commonly used; HBM) and machine discharging model (Machine Model; MM) these two kinds of types are simulated the situation that static discharge produces; can learn the effect of an ESD protection circuit for electrostatic discharge (ESD) protection by measuring HBM value or MM value, the effect of bigger its electrostatic discharge (ESD) protection of expression of HBM value or MM value better.When an ESD protection circuit was connected in the input attenuator of an internal circuit, the HBM value of existing ESD protection circuit was about 2.5KV, and the MM value is about 200V, and the HBM value of ESD protection circuit of the present invention 10 can reach 5.5KV, and the MM value can reach 500V.When an ESD protection circuit was connected in a voltage source attenuator, the HBM value of existing ESD protection circuit was about 5KV, and the MM value is about 200V, and the HBM value of ESD protection circuit of the present invention 10 can reach 8KV, and the MM value can reach 400V.By above data as can be known, ESD protection circuit 10 of the present invention can reach electrostatic discharge (ESD) protection effectively.
Please refer to Fig. 7, Fig. 7 is the circuit diagram of the complementary ESD protection circuit of the present invention.Among Fig. 3, if electrostatic discharge pulses is entered by voltage source, static discharge current is by the input attenuator 22 of earth point through ESD protection circuit arrival internal circuit, and then the effect of electrostatic discharge (ESD) protection may be not enough to satisfy higher demand.As shown in Figure 7; if 22 circuit of being formed by PNP bipolar junction transistor and P-type mos transistor with the notions adding one of complementation 26 of input attenuator at voltage source and internal circuit; ESD protection circuit 10 among itself and Fig. 3 is complementary fully; then when an electrostatic discharge pulses is entered by voltage source; promptly directly arrive the input attenuator 22 of this internal circuit, improve the effect of electrostatic discharge (ESD) protection via circuit 26.
Compared with prior art; the N type metal oxide semiconductor transistor that ESD protection circuit 10 of the present invention is isolated in the P trap 38 with N trap 36 and N+ buried layer 34 in the bipolar CMOS transistor technology; the N type metal oxide semiconductor transistor of in CMOS transistor technology, isolating in the P trap 54 with N deep trap 52; utilize the fabrication techniques N type metal oxide semiconductor transistor 12 of this isolation to drive by two NPN bipolar junction transistors 14 as trigger; the 16 NPN Darlington circuits of being formed make the electrostatic induced current can be fast by reaching the effect of electrostatic discharge (ESD) protection.By experiment value as can be known, no matter ESD protection circuit of the present invention 10 is connected in the input attenuator 22 or the voltage source attenuator 24 of internal circuit, can both more effectively reach the protection of static discharge than prior art.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to spirit of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (12)
1. ESD protection circuit, it comprises:
One NPN Darlington circuit, it has an input, a control end and an output, the output head grounding of this NPN Darlington circuit; And
One N type metal oxide semiconductor transistor, its drain electrode is connected in the input of this NPN Darlington circuit, the transistorized source electrode of this N type metal oxide semiconductor is connected in the control end of this NPN Darlington circuit, and the transistorized grid of this N type metal oxide semiconductor is connected in the output of this NPN Darlington circuit.
2. ESD protection circuit as claimed in claim 1, wherein this NPN Darlington circuit comprises two NPN bipolar junction transistors, each NPN bipolar junction transistor comprises a N+ buried layer, one P trap, be formed at the upside of this N+ buried layer, a N trap is formed at the upside of this N+ buried layer in the mode around this P trap, and a N+ utmost point, be formed at the upside of this P trap; And this N type metal oxide semiconductor transistor comprises a N+ buried layer, and a P trap is formed at the upside of this N+ buried layer, and a N trap is formed at the upside of this N+ buried layer in the mode around this P trap, and two N+ utmost points, is formed at the upside of this P trap.
3. ESD protection circuit as claimed in claim 2; wherein these two bipolar junction transistors and this N type metal oxide semiconductor transistor are formed on the P type substrate, and these two NPN bipolar junction transistors and the transistorized N trap of this N type metal oxide semiconductor are used for its P trap and this P type substrate isolation.
4. ESD protection circuit as claimed in claim 3 wherein be formed with a P type epitaxial loayer on this P type substrate, and these two bipolar junction transistors and this N type metal oxide semiconductor transistor is formed on this P type epitaxial loayer.
5. ESD protection circuit as claimed in claim 3 wherein be formed with a N type epitaxial loayer on this P type substrate, and these two bipolar junction transistors and this N type metal oxide semiconductor transistor is formed on this N type epitaxial loayer.
6. ESD protection circuit as claimed in claim 3, it forms via a bipolar CMOS transistor technology.
7. ESD protection circuit as claimed in claim 1, wherein this NPN Darlington circuit comprises two NPN bipolar junction transistors, and each NPN bipolar junction transistor comprises a N deep trap, one P trap, be formed at the upside of this N deep trap, and a N+ utmost point, be formed at the upside of this P trap; And this N type metal oxide semiconductor transistor comprises a N deep trap, and a P trap is formed at the upside of this N deep trap, and two N+ utmost points, is formed at the upside of this P trap.
8. ESD protection circuit as claimed in claim 7; wherein these two bipolar junction transistors and this N type metal oxide semiconductor transistor are formed on the P type substrate, and these two NPN bipolar junction transistors and the transistorized N deep trap of this N type metal oxide semiconductor can be with its P trap and this P type substrate isolation.
9. ESD protection circuit as claimed in claim 8, it forms via a CMOS transistor technology.
10. ESD protection circuit as claimed in claim 1, wherein the input of this NPN Darlington circuit is connected in the input of a circuit.
11. ESD protection circuit as claimed in claim 1, wherein the input of this NPN Darlington circuit is connected in a voltage source.
12. ESD protection circuit as claimed in claim 1, it also comprises:
A PNP Darlington circuit, its input is connected in the input of this NPN Darlington circuit, and the output of this PNP Darlington circuit is connected in a voltage source; And
One P-type mos transistor, its drain electrode is connected in the input of this PNP Darlington circuit, the transistorized source electrode of this P-type mos is connected in the control end of this PNP Darlington circuit, and the transistorized grid of this P-type mos is connected in the output of this PNP Darlington circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021471983A CN100416822C (en) | 2002-10-25 | 2002-10-25 | Static discharge protective circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021471983A CN100416822C (en) | 2002-10-25 | 2002-10-25 | Static discharge protective circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1492505A CN1492505A (en) | 2004-04-28 |
| CN100416822C true CN100416822C (en) | 2008-09-03 |
Family
ID=34232939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021471983A Expired - Lifetime CN100416822C (en) | 2002-10-25 | 2002-10-25 | Static discharge protective circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100416822C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220223580A1 (en) * | 2021-01-13 | 2022-07-14 | Texas Instruments Incorporated | Compact area electrostatic discharge protection circuit |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4926468B2 (en) * | 2005-12-07 | 2012-05-09 | ローム株式会社 | Electrostatic breakdown protection circuit and semiconductor integrated circuit device having the same |
| CN101373894B (en) * | 2007-08-20 | 2012-05-30 | 天津南大强芯半导体芯片设计有限公司 | Electrostatic discharge protecting circuit |
| CN107731813A (en) * | 2017-11-07 | 2018-02-23 | 福建晋润半导体技术有限公司 | A kind of esd protection circuit and its manufacture method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US526289A (en) * | 1894-09-18 | Peter j | ||
| US5463520A (en) * | 1994-05-09 | 1995-10-31 | At&T Ipm Corp. | Electrostatic discharge protection with hysteresis trigger circuit |
| CN1132936A (en) * | 1995-04-06 | 1996-10-09 | 财团法人工业技术研究院 | Electrostatic discharge protection circuit |
| US5640299A (en) * | 1991-03-28 | 1997-06-17 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| US5748425A (en) * | 1995-10-20 | 1998-05-05 | Temic Telefunken Microelectronic Gmbh | Electrostatic discharge circuit layout |
| CN1213177A (en) * | 1997-09-26 | 1999-04-07 | Lg半导体株式会社 | Electrostatic discharge protection circuit |
| US6430016B1 (en) * | 2000-02-11 | 2002-08-06 | Micron Technology, Inc. | Setpoint silicon controlled rectifier (SCR) electrostatic discharge (ESD) core clamp |
| US6442008B1 (en) * | 1999-11-29 | 2002-08-27 | Compaq Information Technologies Group, L.P. | Low leakage clamp for E.S.D. protection |
-
2002
- 2002-10-25 CN CNB021471983A patent/CN100416822C/en not_active Expired - Lifetime
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US526289A (en) * | 1894-09-18 | Peter j | ||
| US5640299A (en) * | 1991-03-28 | 1997-06-17 | Texas Instruments Incorporated | Electrostatic discharge protection in integrated circuits, systems and methods |
| US5463520A (en) * | 1994-05-09 | 1995-10-31 | At&T Ipm Corp. | Electrostatic discharge protection with hysteresis trigger circuit |
| CN1132936A (en) * | 1995-04-06 | 1996-10-09 | 财团法人工业技术研究院 | Electrostatic discharge protection circuit |
| US5748425A (en) * | 1995-10-20 | 1998-05-05 | Temic Telefunken Microelectronic Gmbh | Electrostatic discharge circuit layout |
| CN1213177A (en) * | 1997-09-26 | 1999-04-07 | Lg半导体株式会社 | Electrostatic discharge protection circuit |
| US6442008B1 (en) * | 1999-11-29 | 2002-08-27 | Compaq Information Technologies Group, L.P. | Low leakage clamp for E.S.D. protection |
| US6430016B1 (en) * | 2000-02-11 | 2002-08-06 | Micron Technology, Inc. | Setpoint silicon controlled rectifier (SCR) electrostatic discharge (ESD) core clamp |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220223580A1 (en) * | 2021-01-13 | 2022-07-14 | Texas Instruments Incorporated | Compact area electrostatic discharge protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1492505A (en) | 2004-04-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101710700B (en) | Semiconductor integrated circuit | |
| US6858901B2 (en) | ESD protection circuit with high substrate-triggering efficiency | |
| CN108701693B (en) | Embedded PMOS-triggered silicon controlled rectifier for electrostatic discharge protection | |
| US6271999B1 (en) | ESD protection circuit for different power supplies | |
| US7203050B2 (en) | NPN Darlington ESD protection circuit | |
| Duvvury et al. | Substrate pump NMOS for ESD protection applications | |
| US5895940A (en) | Integrated circuit buffer devices having built-in electrostatic discharge protection thyristors | |
| US6448123B1 (en) | Low capacitance ESD protection device | |
| US7825473B2 (en) | Initial-on SCR device for on-chip ESD protection | |
| US8134813B2 (en) | Method and apparatus to reduce footprint of ESD protection within an integrated circuit | |
| US6479872B1 (en) | Dynamic substrate-coupled electrostatic discharging protection circuit | |
| US6912109B1 (en) | Power-rail ESD clamp circuits with well-triggered PMOS | |
| US20060215337A1 (en) | ESD protection circuit with low parasitic capacitance | |
| US20050045952A1 (en) | Pfet-based esd protection strategy for improved external latch-up robustness | |
| CN102263102B (en) | Backward diode-triggered thyristor for electrostatic protection | |
| CN102034811A (en) | Low-voltage SCR (Silicon Controlled Rectifier) structure for ESD (Electronic Static Discharge) protection of integrated circuit chip | |
| US20110133247A1 (en) | Zener-Triggered SCR-Based Electrostatic Discharge Protection Devices For CDM And HBM Stress Conditions | |
| KR100971431B1 (en) | Electro-static Discharge Protection Device | |
| CN113540070B (en) | Electrostatic protection circuit | |
| US7859804B1 (en) | ESD protection structure | |
| US7068482B2 (en) | BiCMOS electrostatic discharge power clamp | |
| CN100416822C (en) | Static discharge protective circuit | |
| US20100067155A1 (en) | Method and apparatus for enhancing the triggering of an electrostatic discharge protection device | |
| Do et al. | Design of All-Directional ESD Protection circuit with SCR-based I/O and LIGBT-based Power clamp | |
| KR100504203B1 (en) | Protecting device of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080903 |