CN100437134C - 电子电路的测试 - Google Patents
电子电路的测试 Download PDFInfo
- Publication number
- CN100437134C CN100437134C CNB2004800043942A CN200480004394A CN100437134C CN 100437134 C CN100437134 C CN 100437134C CN B2004800043942 A CNB2004800043942 A CN B2004800043942A CN 200480004394 A CN200480004394 A CN 200480004394A CN 100437134 C CN100437134 C CN 100437134C
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- test
- circuit
- order
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 320
- 230000005540 biological transmission Effects 0.000 claims description 27
- 230000004044 response Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 238000004891 communication Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 7
- 230000010354 integration Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 230000008672 reprogramming Effects 0.000 claims description 3
- 238000009795 derivation Methods 0.000 claims description 2
- 238000004088 simulation Methods 0.000 claims 1
- 230000006870 function Effects 0.000 description 22
- 230000008859 change Effects 0.000 description 8
- 238000012546 transfer Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000006073 displacement reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000001429 stepping effect Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318558—Addressing or selecting of subparts of the device under test
Abstract
Description
Claims (24)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03100370 | 2003-02-18 | ||
EP03100370.0 | 2003-02-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1751245A CN1751245A (zh) | 2006-03-22 |
CN100437134C true CN100437134C (zh) | 2008-11-26 |
Family
ID=32892946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800043942A Expired - Fee Related CN100437134C (zh) | 2003-02-18 | 2004-02-05 | 电子电路的测试 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7447963B2 (zh) |
EP (1) | EP1597605B1 (zh) |
JP (1) | JP2006518040A (zh) |
KR (1) | KR20050105221A (zh) |
CN (1) | CN100437134C (zh) |
AT (1) | ATE361474T1 (zh) |
DE (1) | DE602004006236T2 (zh) |
WO (1) | WO2004075250A2 (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060045123A1 (en) * | 2004-07-14 | 2006-03-02 | Sundar Gopalan | Method of forming a communication system, a communication card with increased bandwidth, and a method of forming a communication device |
US7899641B2 (en) * | 2005-02-01 | 2011-03-01 | Nxp B.V. | Testable electronic circuit |
US7900108B2 (en) | 2006-08-31 | 2011-03-01 | Nxp B.V. | Multi-clock system-on-chip with universal clock control modules for transition fault test at speed multi-core |
DE102009000698A1 (de) * | 2009-02-06 | 2010-08-12 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Prüfschaltung zur Prüfung einer Durchführung eines Handshake-Protokolls und Verfahren zur Prüfung einer Durchführung eines Handshake-Protokolls |
US8935583B2 (en) * | 2012-05-22 | 2015-01-13 | Cisco Technology, Inc. | Removing scan channel limitation on semiconductor devices |
JP6062795B2 (ja) * | 2013-04-25 | 2017-01-18 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
JP2016045123A (ja) * | 2014-08-25 | 2016-04-04 | 株式会社メガチップス | テスト回路 |
CN105988075B (zh) * | 2015-02-17 | 2019-12-20 | 恩智浦美国有限公司 | 用于扫描测试的增强状态监视器 |
DE102016203270B3 (de) * | 2016-02-29 | 2017-08-10 | Infineon Technologies Ag | Mikrocontroller und Verfahren zum Testen eines Mikrocontrollers |
KR20190066482A (ko) * | 2017-12-05 | 2019-06-13 | 삼성전자주식회사 | 인터포저를 사용하는 번 인 테스트 장치 및 테스트 방법 |
KR20200106732A (ko) * | 2019-03-05 | 2020-09-15 | 에스케이하이닉스 주식회사 | 반도체장치 |
FR3101449B1 (fr) * | 2019-09-27 | 2021-10-15 | St Microelectronics Sa | Détection et correction d'erreurs |
CN114200284A (zh) * | 2021-10-28 | 2022-03-18 | 成绎半导体(苏州)有限公司 | 一种集成电路的测试校准方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4703484A (en) * | 1985-12-19 | 1987-10-27 | Harris Corporation | Programmable integrated circuit fault detection apparatus |
GB2234142A (en) * | 1989-05-29 | 1991-01-23 | Nec Corp | Interference minimisation mobile radio system |
US5627842A (en) * | 1993-01-21 | 1997-05-06 | Digital Equipment Corporation | Architecture for system-wide standardized intra-module and inter-module fault testing |
EP0855654A2 (en) * | 1992-06-17 | 1998-07-29 | Texas Instruments Incorporated | Hierarchical connection method apparatus and protocol |
US6378090B1 (en) * | 1998-04-24 | 2002-04-23 | Texas Instruments Incorporated | Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port |
US6456961B1 (en) * | 1999-04-30 | 2002-09-24 | Srinivas Patil | Method and apparatus for creating testable circuit designs having embedded cores |
US20020168015A1 (en) * | 1999-11-19 | 2002-11-14 | Whetsel Lee D. | Plural circuit selection using role reversing control inputs |
US6499125B1 (en) * | 1998-11-24 | 2002-12-24 | Matsushita Electric Industrial Co., Ltd. | Method for inserting test circuit and method for converting test data |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5132635A (en) * | 1991-03-05 | 1992-07-21 | Ast Research, Inc. | Serial testing of removable circuit boards on a backplane bus |
US5343478A (en) * | 1991-11-27 | 1994-08-30 | Ncr Corporation | Computer system configuration via test bus |
JP3610095B2 (ja) * | 1993-07-30 | 2005-01-12 | テキサス インスツルメンツ インコーポレイテツド | 電気回路のストリームライン化(Streamlined)された同時試験方法と装置 |
US5790561A (en) * | 1997-01-17 | 1998-08-04 | Rockwell International Corporation | Internal testability system for microprocessor-based integrated circuit |
US5768289A (en) * | 1997-05-22 | 1998-06-16 | Intel Corporation | Dynamically controlling the number of boundary-scan cells in a boundary-scan path |
US7003707B2 (en) * | 2000-04-28 | 2006-02-21 | Texas Instruments Incorporated | IC tap/scan test port access with tap lock circuitry |
US20020095633A1 (en) * | 2000-10-05 | 2002-07-18 | Ulf Pillkahn | Electronic component, a test configuration and a method for testing connections of electronic components on a printed circuit board |
-
2004
- 2004-02-05 WO PCT/IB2004/050075 patent/WO2004075250A2/en active IP Right Grant
- 2004-02-05 EP EP04708421A patent/EP1597605B1/en not_active Expired - Lifetime
- 2004-02-05 DE DE602004006236T patent/DE602004006236T2/de not_active Expired - Lifetime
- 2004-02-05 KR KR1020057015094A patent/KR20050105221A/ko not_active Application Discontinuation
- 2004-02-05 US US10/545,735 patent/US7447963B2/en active Active
- 2004-02-05 AT AT04708421T patent/ATE361474T1/de not_active IP Right Cessation
- 2004-02-05 CN CNB2004800043942A patent/CN100437134C/zh not_active Expired - Fee Related
- 2004-02-05 JP JP2006502561A patent/JP2006518040A/ja not_active Withdrawn
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4703484A (en) * | 1985-12-19 | 1987-10-27 | Harris Corporation | Programmable integrated circuit fault detection apparatus |
GB2234142A (en) * | 1989-05-29 | 1991-01-23 | Nec Corp | Interference minimisation mobile radio system |
EP0855654A2 (en) * | 1992-06-17 | 1998-07-29 | Texas Instruments Incorporated | Hierarchical connection method apparatus and protocol |
US5627842A (en) * | 1993-01-21 | 1997-05-06 | Digital Equipment Corporation | Architecture for system-wide standardized intra-module and inter-module fault testing |
US6378090B1 (en) * | 1998-04-24 | 2002-04-23 | Texas Instruments Incorporated | Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port |
US6499125B1 (en) * | 1998-11-24 | 2002-12-24 | Matsushita Electric Industrial Co., Ltd. | Method for inserting test circuit and method for converting test data |
US6456961B1 (en) * | 1999-04-30 | 2002-09-24 | Srinivas Patil | Method and apparatus for creating testable circuit designs having embedded cores |
US20020168015A1 (en) * | 1999-11-19 | 2002-11-14 | Whetsel Lee D. | Plural circuit selection using role reversing control inputs |
Non-Patent Citations (2)
Title |
---|
Addressable Test Ports An Approach to Testing Embedded Cores. WHETSEL L ED. INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS PROCEEDING INTERNATIONAL TEST CONFERENCE 1999. ITC'99. INTERNATIONAL CITY NJ, SEPT.28-30,1999,INTERNATIONAL TEST CONFERENCE,NEW YORK,NY:IEEE,US,VOL.CONF.30. 1999 * |
Addressable Test Ports An Approach toTestingEmbeddedCores. WHETSEL L ED.INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS PROCEEDING INTERNATIONAL TEST CONFERENCE 1999. ITC'99. INTERNATIONAL CITY NJ, SEPT.28-30,1999,INTERNATIONAL TEST CONFERENCE,NEW YORK,NY:IEEE,US,VOL.CONF.30. 1999 |
Also Published As
Publication number | Publication date |
---|---|
US20060150042A1 (en) | 2006-07-06 |
ATE361474T1 (de) | 2007-05-15 |
DE602004006236T2 (de) | 2008-01-10 |
WO2004075250A2 (en) | 2004-09-02 |
WO2004075250A3 (en) | 2004-11-25 |
US7447963B2 (en) | 2008-11-04 |
EP1597605B1 (en) | 2007-05-02 |
JP2006518040A (ja) | 2006-08-03 |
EP1597605A2 (en) | 2005-11-23 |
KR20050105221A (ko) | 2005-11-03 |
CN1751245A (zh) | 2006-03-22 |
DE602004006236D1 (de) | 2007-06-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100437134C (zh) | 电子电路的测试 | |
US6965648B1 (en) | Source synchronous link integrity validation | |
US7191371B2 (en) | System and method for sequential testing of high speed serial link core | |
US6977960B2 (en) | Self test circuit for evaluating a high-speed serial interface | |
TWI280001B (en) | Programmable measurement mode for a serial point to point link | |
CN109644020A (zh) | 用于自适应均衡、自适应边沿跟踪以及延迟校准的c-phy训练模式 | |
KR20090077015A (ko) | 듀얼-모드 메모리 상호접속을 포함하는 메모리 제어기 | |
US7177965B2 (en) | Linking addressable shadow port and protocol for serial bus networks | |
US20070198882A1 (en) | Method and circuit for lssd testing | |
CN101545949B (zh) | 用于通过连接触点串行发送数据的电路装置、设备和方法 | |
JP2000322378A (ja) | プログラム可能クロックシフトを用いた調節可能データ遅延 | |
KR20170115041A (ko) | 조정된 단일 클록 소스 동기 직렬화기역직렬화기 프로토콜을 사용하는 고속 데이터 전송 | |
CN1926799B (zh) | 包括相互异步电路模块的电路 | |
JPS63503481A (ja) | マルチモードカウンタ回路網 | |
US20050262363A1 (en) | Method for signaling during a transaction and receiving unit and system for use therewith | |
US20030061527A1 (en) | Method and apparatus for realigning bits on a parallel bus | |
EP1150451A2 (en) | Method and apparatus for initializing a synchronizer | |
JP3408486B2 (ja) | 装置間の同期回路 | |
KR100665918B1 (ko) | 번인 테스트 시스템을 위한 선로 인터페이스 장치 | |
US7603541B2 (en) | Array synchronization with counters | |
US20110113310A1 (en) | Apparatus and method for clock signal synchronization in jtag testing in systems having selectable modules processing data signals at different rates | |
US7644208B2 (en) | Serial transmission system with a return signal generator from the farthest terminal to synchronize return signals/data from the farthest terminal with any specified intervening terminals | |
SU1751767A1 (ru) | Устройство дл контрол тестопригодных программ | |
JPH06334642A (ja) | シリアルバス通信システム | |
NO161348B (no) | Framgangsmaate og apparat for selvregulert transmisjon av digitale datasignaler. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NXP CO., LTD. Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20071012 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20071012 Address after: Holland Ian Deho Finn Applicant after: NXP B.V. Address before: Holland Ian Deho Finn Applicant before: Koninklijke Philips Electronics N.V. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150914 Address after: Delaware Patentee after: III Holdings 6 LLC Address before: Holland Ian Deho Finn Patentee before: NXP B.V. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081126 |